Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	75.00						75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	51945028	6018483	0	0
MemTLResponseWithoutDebugIsError_A	51945028	12	0	0
NdmResetAckNeedsDebug_A	51945028	0	0	0
SbaTLRequestNeedsDebug_A	51945028	10663	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51945028	6018483	0	0
T2	75441	25248	0	0
T3	452369	0	0	0
T4	782749	193200	0	0
T5	232117	123968	0	0
T6	0	57232	0	0
T7	80604	61885	0	0
T8	15762	11476	0	0
T13	37203	0	0	0
T24	90031	0	0	0
T25	0	60929	0	0
T27	761242	0	0	0
T29	0	4426	0	0
T30	0	65968	0	0
T31	0	97615	0	0
T32	38212	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51945028	12	0	0
T33	1849	10	0	0
T34	0	2	0	0
T35	119009	0	0	0
T36	265071	0	0	0
T37	5281	0	0	0
T38	661145	0	0	0
T39	1549	0	0	0
T40	16426	0	0	0
T41	28755	0	0	0
T42	298568	0	0	0
T43	3555	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51945028	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51945028	10663	0	0
T1	174080	23	0	0
T2	75441	0	0	0
T3	452369	223	0	0
T4	782749	0	0	0
T5	232117	0	0	0
T7	80604	0	0	0
T8	15762	0	0	0
T13	37203	35	0	0
T24	90031	52	0	0
T27	761242	1376	0	0
T28	0	70	0	0
T32	0	48	0	0
T44	0	157	0	0
T45	0	16	0	0
T46	0	122	0	0