Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9251251 |
9249931 |
0 |
0 |
selKnown1 |
58673929 |
58672605 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9251251 |
9249931 |
0 |
0 |
T1 |
26782 |
26780 |
0 |
0 |
T2 |
11560 |
11558 |
0 |
0 |
T3 |
38000 |
37996 |
0 |
0 |
T4 |
39218 |
39214 |
0 |
0 |
T5 |
45410 |
45406 |
0 |
0 |
T6 |
0 |
2 |
0 |
0 |
T7 |
3803 |
3799 |
0 |
0 |
T8 |
3067 |
3063 |
0 |
0 |
T13 |
13340 |
13336 |
0 |
0 |
T24 |
33966 |
33962 |
0 |
0 |
T25 |
0 |
22 |
0 |
0 |
T26 |
0 |
1 |
0 |
0 |
T27 |
236479 |
236475 |
0 |
0 |
T30 |
0 |
25 |
0 |
0 |
T32 |
6 |
4 |
0 |
0 |
T52 |
2 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
58673929 |
58672605 |
0 |
0 |
T1 |
187471 |
187469 |
0 |
0 |
T2 |
81221 |
81219 |
0 |
0 |
T3 |
471373 |
471369 |
0 |
0 |
T4 |
802360 |
802356 |
0 |
0 |
T5 |
254829 |
254825 |
0 |
0 |
T6 |
0 |
2 |
0 |
0 |
T7 |
82506 |
82502 |
0 |
0 |
T8 |
17296 |
17292 |
0 |
0 |
T13 |
43877 |
43873 |
0 |
0 |
T24 |
107019 |
107015 |
0 |
0 |
T25 |
0 |
10 |
0 |
0 |
T27 |
879487 |
879484 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T32 |
6 |
4 |
0 |
0 |
T52 |
2 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2521619 |
2521398 |
0 |
0 |
selKnown1 |
51945028 |
51944805 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2521619 |
2521398 |
0 |
0 |
T1 |
13391 |
13390 |
0 |
0 |
T2 |
5780 |
5779 |
0 |
0 |
T3 |
18996 |
18995 |
0 |
0 |
T4 |
19597 |
19596 |
0 |
0 |
T5 |
22698 |
22697 |
0 |
0 |
T7 |
1900 |
1899 |
0 |
0 |
T8 |
1532 |
1531 |
0 |
0 |
T13 |
6666 |
6665 |
0 |
0 |
T24 |
16978 |
16977 |
0 |
0 |
T27 |
118233 |
118232 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
51945028 |
51944805 |
0 |
0 |
T1 |
174080 |
174079 |
0 |
0 |
T2 |
75441 |
75440 |
0 |
0 |
T3 |
452369 |
452368 |
0 |
0 |
T4 |
782749 |
782748 |
0 |
0 |
T5 |
232117 |
232116 |
0 |
0 |
T7 |
80604 |
80603 |
0 |
0 |
T8 |
15762 |
15761 |
0 |
0 |
T13 |
37203 |
37202 |
0 |
0 |
T24 |
90031 |
90030 |
0 |
0 |
T27 |
761242 |
761242 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
767 |
546 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
7 |
6 |
0 |
0 |
T6 |
0 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T13 |
4 |
3 |
0 |
0 |
T24 |
5 |
4 |
0 |
0 |
T25 |
0 |
5 |
0 |
0 |
T27 |
6 |
5 |
0 |
0 |
T30 |
0 |
25 |
0 |
0 |
T32 |
3 |
2 |
0 |
0 |
T52 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
626 |
403 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
7 |
6 |
0 |
0 |
T6 |
0 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T13 |
4 |
3 |
0 |
0 |
T24 |
5 |
4 |
0 |
0 |
T25 |
0 |
5 |
0 |
0 |
T27 |
6 |
5 |
0 |
0 |
T30 |
0 |
3 |
0 |
0 |
T32 |
3 |
2 |
0 |
0 |
T52 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6726717 |
6726277 |
0 |
0 |
selKnown1 |
6726512 |
6726074 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6726717 |
6726277 |
0 |
0 |
T1 |
13391 |
13390 |
0 |
0 |
T2 |
5780 |
5779 |
0 |
0 |
T3 |
18996 |
18995 |
0 |
0 |
T4 |
19597 |
19596 |
0 |
0 |
T5 |
22698 |
22697 |
0 |
0 |
T7 |
1901 |
1900 |
0 |
0 |
T8 |
1533 |
1532 |
0 |
0 |
T13 |
6666 |
6665 |
0 |
0 |
T24 |
16978 |
16977 |
0 |
0 |
T27 |
118234 |
118233 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6726512 |
6726074 |
0 |
0 |
T1 |
13391 |
13390 |
0 |
0 |
T2 |
5780 |
5779 |
0 |
0 |
T3 |
18996 |
18995 |
0 |
0 |
T4 |
19597 |
19596 |
0 |
0 |
T5 |
22698 |
22697 |
0 |
0 |
T7 |
1900 |
1899 |
0 |
0 |
T8 |
1532 |
1531 |
0 |
0 |
T13 |
6666 |
6665 |
0 |
0 |
T24 |
16978 |
16977 |
0 |
0 |
T27 |
118233 |
118232 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2148 |
1710 |
0 |
0 |
selKnown1 |
1763 |
1323 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2148 |
1710 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T4 |
17 |
16 |
0 |
0 |
T5 |
7 |
6 |
0 |
0 |
T6 |
0 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T13 |
4 |
3 |
0 |
0 |
T24 |
5 |
4 |
0 |
0 |
T25 |
0 |
17 |
0 |
0 |
T26 |
0 |
1 |
0 |
0 |
T27 |
6 |
5 |
0 |
0 |
T32 |
3 |
2 |
0 |
0 |
T52 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1763 |
1323 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
7 |
6 |
0 |
0 |
T6 |
0 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T13 |
4 |
3 |
0 |
0 |
T24 |
5 |
4 |
0 |
0 |
T25 |
0 |
5 |
0 |
0 |
T27 |
6 |
5 |
0 |
0 |
T30 |
0 |
3 |
0 |
0 |
T32 |
3 |
2 |
0 |
0 |
T52 |
1 |
0 |
0 |
0 |