SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
82.66 | 98.04 | 77.78 | 100.00 | 87.50 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1338 | 1338 | 0 | 0 |
OutputsKnown_A | 311670168 | 311423286 | 0 | 0 |
gen_flops.OutputDelay_A | 155835084 | 155706009 | 0 | 2007 |
gen_no_flops.OutputDelay_A | 155835084 | 155711643 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1338 | 1338 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T13 | 6 | 6 | 0 | 0 |
T24 | 6 | 6 | 0 | 0 |
T27 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 311670168 | 311423286 | 0 | 0 |
T1 | 1044480 | 1044144 | 0 | 0 |
T2 | 452646 | 452232 | 0 | 0 |
T3 | 2714214 | 2712756 | 0 | 0 |
T4 | 4696494 | 4693674 | 0 | 0 |
T5 | 1392702 | 1389828 | 0 | 0 |
T7 | 483624 | 483198 | 0 | 0 |
T8 | 94572 | 94236 | 0 | 0 |
T13 | 223218 | 221808 | 0 | 0 |
T24 | 540186 | 538092 | 0 | 0 |
T27 | 4567452 | 4567206 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 155835084 | 155706009 | 0 | 2007 |
T1 | 522240 | 522063 | 0 | 9 |
T2 | 226323 | 226107 | 0 | 9 |
T3 | 1357107 | 1356342 | 0 | 9 |
T4 | 2348247 | 2346774 | 0 | 9 |
T5 | 696351 | 694851 | 0 | 9 |
T7 | 241812 | 241590 | 0 | 9 |
T8 | 47286 | 47109 | 0 | 9 |
T13 | 111609 | 110868 | 0 | 9 |
T24 | 270093 | 269001 | 0 | 9 |
T27 | 2283726 | 2283597 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 155835084 | 155711643 | 0 | 0 |
T1 | 522240 | 522072 | 0 | 0 |
T2 | 226323 | 226116 | 0 | 0 |
T3 | 1357107 | 1356378 | 0 | 0 |
T4 | 2348247 | 2346837 | 0 | 0 |
T5 | 696351 | 694914 | 0 | 0 |
T7 | 241812 | 241599 | 0 | 0 |
T8 | 47286 | 47118 | 0 | 0 |
T13 | 111609 | 110904 | 0 | 0 |
T24 | 270093 | 269046 | 0 | 0 |
T27 | 2283726 | 2283603 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 223 | 223 | 0 | 0 |
OutputsKnown_A | 51945028 | 51903881 | 0 | 0 |
gen_flops.OutputDelay_A | 51945028 | 51902003 | 0 | 669 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223 | 223 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51945028 | 51903881 | 0 | 0 |
T1 | 174080 | 174024 | 0 | 0 |
T2 | 75441 | 75372 | 0 | 0 |
T3 | 452369 | 452126 | 0 | 0 |
T4 | 782749 | 782279 | 0 | 0 |
T5 | 232117 | 231638 | 0 | 0 |
T7 | 80604 | 80533 | 0 | 0 |
T8 | 15762 | 15706 | 0 | 0 |
T13 | 37203 | 36968 | 0 | 0 |
T24 | 90031 | 89682 | 0 | 0 |
T27 | 761242 | 761201 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51945028 | 51902003 | 0 | 669 |
T1 | 174080 | 174021 | 0 | 3 |
T2 | 75441 | 75369 | 0 | 3 |
T3 | 452369 | 452114 | 0 | 3 |
T4 | 782749 | 782258 | 0 | 3 |
T5 | 232117 | 231617 | 0 | 3 |
T7 | 80604 | 80530 | 0 | 3 |
T8 | 15762 | 15703 | 0 | 3 |
T13 | 37203 | 36956 | 0 | 3 |
T24 | 90031 | 89667 | 0 | 3 |
T27 | 761242 | 761199 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 223 | 223 | 0 | 0 |
OutputsKnown_A | 51945028 | 51903881 | 0 | 0 |
gen_flops.OutputDelay_A | 51945028 | 51902003 | 0 | 669 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223 | 223 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51945028 | 51903881 | 0 | 0 |
T1 | 174080 | 174024 | 0 | 0 |
T2 | 75441 | 75372 | 0 | 0 |
T3 | 452369 | 452126 | 0 | 0 |
T4 | 782749 | 782279 | 0 | 0 |
T5 | 232117 | 231638 | 0 | 0 |
T7 | 80604 | 80533 | 0 | 0 |
T8 | 15762 | 15706 | 0 | 0 |
T13 | 37203 | 36968 | 0 | 0 |
T24 | 90031 | 89682 | 0 | 0 |
T27 | 761242 | 761201 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51945028 | 51902003 | 0 | 669 |
T1 | 174080 | 174021 | 0 | 3 |
T2 | 75441 | 75369 | 0 | 3 |
T3 | 452369 | 452114 | 0 | 3 |
T4 | 782749 | 782258 | 0 | 3 |
T5 | 232117 | 231617 | 0 | 3 |
T7 | 80604 | 80530 | 0 | 3 |
T8 | 15762 | 15703 | 0 | 3 |
T13 | 37203 | 36956 | 0 | 3 |
T24 | 90031 | 89667 | 0 | 3 |
T27 | 761242 | 761199 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 223 | 223 | 0 | 0 |
OutputsKnown_A | 51945028 | 51903881 | 0 | 0 |
gen_no_flops.OutputDelay_A | 51945028 | 51903881 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223 | 223 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51945028 | 51903881 | 0 | 0 |
T1 | 174080 | 174024 | 0 | 0 |
T2 | 75441 | 75372 | 0 | 0 |
T3 | 452369 | 452126 | 0 | 0 |
T4 | 782749 | 782279 | 0 | 0 |
T5 | 232117 | 231638 | 0 | 0 |
T7 | 80604 | 80533 | 0 | 0 |
T8 | 15762 | 15706 | 0 | 0 |
T13 | 37203 | 36968 | 0 | 0 |
T24 | 90031 | 89682 | 0 | 0 |
T27 | 761242 | 761201 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51945028 | 51903881 | 0 | 0 |
T1 | 174080 | 174024 | 0 | 0 |
T2 | 75441 | 75372 | 0 | 0 |
T3 | 452369 | 452126 | 0 | 0 |
T4 | 782749 | 782279 | 0 | 0 |
T5 | 232117 | 231638 | 0 | 0 |
T7 | 80604 | 80533 | 0 | 0 |
T8 | 15762 | 15706 | 0 | 0 |
T13 | 37203 | 36968 | 0 | 0 |
T24 | 90031 | 89682 | 0 | 0 |
T27 | 761242 | 761201 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 223 | 223 | 0 | 0 |
OutputsKnown_A | 51945028 | 51903881 | 0 | 0 |
gen_flops.OutputDelay_A | 51945028 | 51902003 | 0 | 669 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223 | 223 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51945028 | 51903881 | 0 | 0 |
T1 | 174080 | 174024 | 0 | 0 |
T2 | 75441 | 75372 | 0 | 0 |
T3 | 452369 | 452126 | 0 | 0 |
T4 | 782749 | 782279 | 0 | 0 |
T5 | 232117 | 231638 | 0 | 0 |
T7 | 80604 | 80533 | 0 | 0 |
T8 | 15762 | 15706 | 0 | 0 |
T13 | 37203 | 36968 | 0 | 0 |
T24 | 90031 | 89682 | 0 | 0 |
T27 | 761242 | 761201 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51945028 | 51902003 | 0 | 669 |
T1 | 174080 | 174021 | 0 | 3 |
T2 | 75441 | 75369 | 0 | 3 |
T3 | 452369 | 452114 | 0 | 3 |
T4 | 782749 | 782258 | 0 | 3 |
T5 | 232117 | 231617 | 0 | 3 |
T7 | 80604 | 80530 | 0 | 3 |
T8 | 15762 | 15703 | 0 | 3 |
T13 | 37203 | 36956 | 0 | 3 |
T24 | 90031 | 89667 | 0 | 3 |
T27 | 761242 | 761199 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 223 | 223 | 0 | 0 |
OutputsKnown_A | 51945028 | 51903881 | 0 | 0 |
gen_no_flops.OutputDelay_A | 51945028 | 51903881 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223 | 223 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51945028 | 51903881 | 0 | 0 |
T1 | 174080 | 174024 | 0 | 0 |
T2 | 75441 | 75372 | 0 | 0 |
T3 | 452369 | 452126 | 0 | 0 |
T4 | 782749 | 782279 | 0 | 0 |
T5 | 232117 | 231638 | 0 | 0 |
T7 | 80604 | 80533 | 0 | 0 |
T8 | 15762 | 15706 | 0 | 0 |
T13 | 37203 | 36968 | 0 | 0 |
T24 | 90031 | 89682 | 0 | 0 |
T27 | 761242 | 761201 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51945028 | 51903881 | 0 | 0 |
T1 | 174080 | 174024 | 0 | 0 |
T2 | 75441 | 75372 | 0 | 0 |
T3 | 452369 | 452126 | 0 | 0 |
T4 | 782749 | 782279 | 0 | 0 |
T5 | 232117 | 231638 | 0 | 0 |
T7 | 80604 | 80533 | 0 | 0 |
T8 | 15762 | 15706 | 0 | 0 |
T13 | 37203 | 36968 | 0 | 0 |
T24 | 90031 | 89682 | 0 | 0 |
T27 | 761242 | 761201 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 223 | 223 | 0 | 0 |
OutputsKnown_A | 51945028 | 51903881 | 0 | 0 |
gen_no_flops.OutputDelay_A | 51945028 | 51903881 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223 | 223 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51945028 | 51903881 | 0 | 0 |
T1 | 174080 | 174024 | 0 | 0 |
T2 | 75441 | 75372 | 0 | 0 |
T3 | 452369 | 452126 | 0 | 0 |
T4 | 782749 | 782279 | 0 | 0 |
T5 | 232117 | 231638 | 0 | 0 |
T7 | 80604 | 80533 | 0 | 0 |
T8 | 15762 | 15706 | 0 | 0 |
T13 | 37203 | 36968 | 0 | 0 |
T24 | 90031 | 89682 | 0 | 0 |
T27 | 761242 | 761201 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51945028 | 51903881 | 0 | 0 |
T1 | 174080 | 174024 | 0 | 0 |
T2 | 75441 | 75372 | 0 | 0 |
T3 | 452369 | 452126 | 0 | 0 |
T4 | 782749 | 782279 | 0 | 0 |
T5 | 232117 | 231638 | 0 | 0 |
T7 | 80604 | 80533 | 0 | 0 |
T8 | 15762 | 15706 | 0 | 0 |
T13 | 37203 | 36968 | 0 | 0 |
T24 | 90031 | 89682 | 0 | 0 |
T27 | 761242 | 761201 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |