SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 223 | 223 | 0 | 0 |
OutputsKnown_A | 51945028 | 51903881 | 0 | 0 |
gen_no_flops.OutputDelay_A | 51945028 | 51903881 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223 | 223 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51945028 | 51903881 | 0 | 0 |
T1 | 174080 | 174024 | 0 | 0 |
T2 | 75441 | 75372 | 0 | 0 |
T3 | 452369 | 452126 | 0 | 0 |
T4 | 782749 | 782279 | 0 | 0 |
T5 | 232117 | 231638 | 0 | 0 |
T7 | 80604 | 80533 | 0 | 0 |
T8 | 15762 | 15706 | 0 | 0 |
T13 | 37203 | 36968 | 0 | 0 |
T24 | 90031 | 89682 | 0 | 0 |
T27 | 761242 | 761201 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 51945028 | 51903881 | 0 | 0 |
T1 | 174080 | 174024 | 0 | 0 |
T2 | 75441 | 75372 | 0 | 0 |
T3 | 452369 | 452126 | 0 | 0 |
T4 | 782749 | 782279 | 0 | 0 |
T5 | 232117 | 231638 | 0 | 0 |
T7 | 80604 | 80533 | 0 | 0 |
T8 | 15762 | 15706 | 0 | 0 |
T13 | 37203 | 36968 | 0 | 0 |
T24 | 90031 | 89682 | 0 | 0 |
T27 | 761242 | 761201 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |