Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 218651 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 593941 1 T1 8 T4 12 T5 9



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 507724 1 T1 6 T4 7 T51 80
values[0x0] 148934 1 T1 4 T4 12 T5 11
values[0x1] 155934 1 T1 9 T4 20 T5 17



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 165673 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 646919 1 T1 11 T4 17 T5 13



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2664 1 T18 1 T29 1 T177 1
valid_sources[0x01] 3215 1 T146 2 T54 1 T69 11
valid_sources[0x02] 2985 1 T18 1 T31 9 T162 1
valid_sources[0x03] 4081 1 T10 1 T178 1 T69 8
valid_sources[0x04] 3137 1 T16 6 T69 13 T75 2
valid_sources[0x05] 2809 1 T18 1 T54 1 T179 1
valid_sources[0x06] 3068 1 T180 10 T11 1 T178 2
valid_sources[0x07] 2747 1 T178 2 T69 8 T74 3
valid_sources[0x08] 3043 1 T181 3 T182 1 T69 2
valid_sources[0x09] 3130 1 T54 1 T69 11 T75 13
valid_sources[0x0a] 2969 1 T69 7 T75 8 T71 1
valid_sources[0x0b] 2873 1 T69 7 T75 2 T74 2
valid_sources[0x0c] 2997 1 T31 6 T159 2 T54 1
valid_sources[0x0d] 3018 1 T183 1 T69 8 T71 1
valid_sources[0x0e] 3141 1 T9 1 T184 3 T69 5
valid_sources[0x0f] 3071 1 T159 1 T54 1 T155 3
valid_sources[0x10] 3059 1 T69 8 T75 4 T74 2
valid_sources[0x11] 3009 1 T9 1 T54 1 T69 5
valid_sources[0x12] 2721 1 T179 2 T69 1 T75 5
valid_sources[0x13] 3205 1 T18 1 T159 2 T17 5
valid_sources[0x14] 3104 1 T185 3 T186 1 T179 1
valid_sources[0x15] 3423 1 T33 29 T54 1 T187 2
valid_sources[0x16] 3020 1 T69 8 T74 3 T72 5
valid_sources[0x17] 2851 1 T20 1 T185 1 T69 6
valid_sources[0x18] 3448 1 T18 1 T22 1 T69 5
valid_sources[0x19] 2696 1 T146 1 T54 1 T182 1
valid_sources[0x1a] 2882 1 T18 1 T54 1 T177 1
valid_sources[0x1b] 3050 1 T18 1 T9 4 T69 2
valid_sources[0x1c] 3256 1 T181 3 T69 8 T75 2
valid_sources[0x1d] 3102 1 T29 1 T159 1 T54 1
valid_sources[0x1e] 3343 1 T69 4 T75 5 T74 3
valid_sources[0x1f] 3176 1 T24 17 T155 1 T69 6
valid_sources[0x20] 3064 1 T5 1 T160 2 T166 3
valid_sources[0x21] 3145 1 T23 5 T22 2 T69 3
valid_sources[0x22] 2986 1 T69 6 T75 5 T71 1
valid_sources[0x23] 2855 1 T182 1 T69 5 T74 4
valid_sources[0x24] 3129 1 T147 1 T54 1 T69 5
valid_sources[0x25] 3364 1 T11 1 T182 1 T69 5
valid_sources[0x26] 3459 1 T9 2 T22 1 T69 4
valid_sources[0x27] 3260 1 T5 1 T69 7 T74 1
valid_sources[0x28] 3197 1 T21 10 T12 2 T179 1
valid_sources[0x29] 3252 1 T69 5 T75 1 T71 4
valid_sources[0x2a] 2931 1 T32 1 T54 1 T179 1
valid_sources[0x2b] 3289 1 T5 3 T9 1 T29 2
valid_sources[0x2c] 2926 1 T185 1 T187 5 T69 7
valid_sources[0x2d] 2900 1 T29 1 T11 1 T69 5
valid_sources[0x2e] 2791 1 T54 1 T69 7 T75 9
valid_sources[0x2f] 3103 1 T29 2 T69 10 T75 2
valid_sources[0x30] 4019 1 T18 1 T36 1 T184 2
valid_sources[0x31] 3436 1 T69 3 T75 2 T71 2
valid_sources[0x32] 2938 1 T69 4 T75 1 T71 1
valid_sources[0x33] 3410 1 T181 1 T69 6 T72 2
valid_sources[0x34] 3309 1 T162 1 T177 1 T69 3
valid_sources[0x35] 3237 1 T69 4 T75 8 T74 5
valid_sources[0x36] 2979 1 T185 3 T186 1 T69 12
valid_sources[0x37] 3332 1 T162 1 T69 4 T71 2
valid_sources[0x38] 3211 1 T69 5 T75 4 T74 1
valid_sources[0x39] 3293 1 T5 1 T146 1 T69 3
valid_sources[0x3a] 3183 1 T20 1 T69 3 T73 39
valid_sources[0x3b] 3334 1 T162 1 T183 3 T69 7
valid_sources[0x3c] 3228 1 T15 7 T186 1 T69 7
valid_sources[0x3d] 2970 1 T31 2 T54 2 T69 11
valid_sources[0x3e] 3297 1 T5 1 T146 1 T17 3
valid_sources[0x3f] 3392 1 T184 2 T69 5 T75 4
valid_sources[0x40] 3206 1 T54 1 T69 6 T73 14
valid_sources[0x41] 3212 1 T54 2 T69 8 T71 3
valid_sources[0x42] 3611 1 T163 14 T17 2 T69 8
valid_sources[0x43] 2758 1 T179 1 T69 4 T75 12
valid_sources[0x44] 3393 1 T69 11 T75 3 T74 4
valid_sources[0x45] 3057 1 T162 1 T185 1 T187 2
valid_sources[0x46] 2942 1 T185 2 T57 3 T69 7
valid_sources[0x47] 3233 1 T69 6 T74 2 T72 3
valid_sources[0x48] 3346 1 T54 1 T69 7 T74 2
valid_sources[0x49] 2990 1 T179 2 T69 12 T71 1
valid_sources[0x4a] 2846 1 T5 2 T10 1 T54 1
valid_sources[0x4b] 2725 1 T1 8 T5 3 T186 1
valid_sources[0x4c] 2837 1 T11 1 T179 1 T69 13
valid_sources[0x4d] 3378 1 T188 1 T69 4 T75 2
valid_sources[0x4e] 3081 1 T1 6 T178 2 T184 2
valid_sources[0x4f] 2942 1 T150 14 T177 1 T69 4
valid_sources[0x50] 3004 1 T54 1 T22 1 T69 10
valid_sources[0x51] 3067 1 T26 1 T69 7 T75 5
valid_sources[0x52] 3054 1 T159 1 T69 4 T72 5
valid_sources[0x53] 3602 1 T185 1 T69 9 T75 8
valid_sources[0x54] 2779 1 T69 6 T75 4 T74 2
valid_sources[0x55] 3041 1 T69 7 T74 1 T72 1
valid_sources[0x56] 2941 1 T69 2 T75 10 T72 5
valid_sources[0x57] 4157 1 T31 16 T29 1 T69 9
valid_sources[0x58] 3274 1 T54 1 T69 11 T75 2
valid_sources[0x59] 2717 1 T9 5 T69 1 T75 2
valid_sources[0x5a] 2999 1 T12 1 T189 1 T69 4
valid_sources[0x5b] 4160 1 T29 1 T69 5 T75 5
valid_sources[0x5c] 3686 1 T69 5 T74 1 T72 1
valid_sources[0x5d] 3207 1 T18 1 T54 1 T190 2
valid_sources[0x5e] 3197 1 T69 8 T75 1 T72 4
valid_sources[0x5f] 3281 1 T69 3 T75 2 T73 38
valid_sources[0x60] 3367 1 T191 6 T11 1 T185 1
valid_sources[0x61] 3196 1 T54 1 T177 1 T179 1
valid_sources[0x62] 3036 1 T69 4 T71 2 T74 1
valid_sources[0x63] 3102 1 T25 1 T159 1 T54 1
valid_sources[0x64] 3206 1 T9 3 T69 8 T75 2
valid_sources[0x65] 3359 1 T18 1 T69 8 T75 5
valid_sources[0x66] 3443 1 T162 1 T192 1 T188 2
valid_sources[0x67] 2853 1 T153 13 T182 1 T69 6
valid_sources[0x68] 3203 1 T162 1 T69 6 T71 1
valid_sources[0x69] 3168 1 T181 4 T54 1 T69 9
valid_sources[0x6a] 3032 1 T183 1 T69 8 T75 1
valid_sources[0x6b] 3305 1 T69 6 T75 1 T74 4
valid_sources[0x6c] 2926 1 T10 1 T54 1 T69 5
valid_sources[0x6d] 2638 1 T29 1 T54 1 T69 9
valid_sources[0x6e] 3060 1 T160 10 T178 1 T69 3
valid_sources[0x6f] 3066 1 T160 7 T17 11 T69 3
valid_sources[0x70] 3131 1 T9 3 T29 1 T183 2
valid_sources[0x71] 2951 1 T150 3 T54 1 T69 6
valid_sources[0x72] 3095 1 T54 1 T69 9 T74 2
valid_sources[0x73] 3024 1 T18 1 T54 1 T42 1
valid_sources[0x74] 3558 1 T5 2 T29 1 T177 1
valid_sources[0x75] 3238 1 T184 2 T69 8 T74 2
valid_sources[0x76] 3990 1 T29 1 T54 2 T69 7
valid_sources[0x77] 4226 1 T184 1 T69 3 T75 3
valid_sources[0x78] 3290 1 T54 1 T190 7 T177 1
valid_sources[0x79] 2985 1 T146 1 T185 2 T69 6
valid_sources[0x7a] 3243 1 T177 1 T187 3 T69 7
valid_sources[0x7b] 4877 1 T54 1 T69 3 T74 4
valid_sources[0x7c] 3252 1 T25 2 T17 1 T69 7
valid_sources[0x7d] 3223 1 T10 1 T177 1 T69 6
valid_sources[0x7e] 2922 1 T177 3 T69 13 T71 1
valid_sources[0x7f] 3076 1 T69 7 T75 12 T72 2
valid_sources[0x80] 3403 1 T5 2 T69 7 T74 3



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 301338 1 T1 5 T51 80 T31 2
values[0x0] all_enables biggest_size 146628 1 T1 2 T4 5 T5 4
values[0x1] all_enables biggest_size 145975 1 T1 1 T4 7 T5 5


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5527 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 30476 1 T6 1 T1 6 T2 8



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 12800 1 T69 65 T75 3 T71 42
values[0x0] 11427 1 T1 1 T2 11 T3 2
values[0x1] 11776 1 T6 1 T1 5 T2 8



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4143 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 31860 1 T6 1 T1 6 T2 9



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 100 1 T193 1 T69 1 T91 1
valid_sources[0x01] 182 1 T82 2 T194 16 T195 1
valid_sources[0x02] 138 1 T28 1 T196 1 T72 6
valid_sources[0x03] 112 1 T134 1 T197 1 T69 1
valid_sources[0x04] 118 1 T5 1 T69 1 T89 3
valid_sources[0x05] 170 1 T150 1 T29 3 T196 1
valid_sources[0x06] 84 1 T198 1 T199 1 T191 1
valid_sources[0x07] 132 1 T76 1 T38 1 T200 1
valid_sources[0x08] 75 1 T1 1 T89 5 T136 1
valid_sources[0x09] 128 1 T201 5 T69 2 T89 1
valid_sources[0x0a] 162 1 T69 1 T72 15 T89 2
valid_sources[0x0b] 88 1 T76 1 T202 1 T187 1
valid_sources[0x0c] 146 1 T39 1 T89 3 T91 2
valid_sources[0x0d] 353 1 T2 2 T84 1 T69 1
valid_sources[0x0e] 94 1 T203 1 T103 1 T94 2
valid_sources[0x0f] 157 1 T69 2 T72 12 T70 1
valid_sources[0x10] 94 1 T84 1 T196 1 T204 2
valid_sources[0x11] 261 1 T203 1 T22 8 T69 1
valid_sources[0x12] 80 1 T9 1 T203 1 T75 1
valid_sources[0x13] 198 1 T35 1 T185 1 T69 1
valid_sources[0x14] 162 1 T2 1 T69 2 T89 3
valid_sources[0x15] 123 1 T142 11 T71 3 T72 8
valid_sources[0x16] 209 1 T69 2 T89 4 T70 1
valid_sources[0x17] 104 1 T182 1 T69 1 T72 5
valid_sources[0x18] 95 1 T2 1 T162 1 T69 1
valid_sources[0x19] 117 1 T150 1 T152 1 T72 1
valid_sources[0x1a] 114 1 T145 2 T69 2 T72 7
valid_sources[0x1b] 123 1 T205 1 T154 3 T206 1
valid_sources[0x1c] 94 1 T203 2 T91 1 T92 5
valid_sources[0x1d] 102 1 T207 1 T40 1 T201 1
valid_sources[0x1e] 145 1 T208 1 T74 1 T72 24
valid_sources[0x1f] 168 1 T196 1 T191 1 T69 1
valid_sources[0x20] 117 1 T204 1 T89 3 T91 2
valid_sources[0x21] 84 1 T181 2 T209 1 T192 1
valid_sources[0x22] 99 1 T15 4 T210 2 T201 2
valid_sources[0x23] 77 1 T16 1 T211 1 T212 3
valid_sources[0x24] 176 1 T3 1 T35 1 T76 1
valid_sources[0x25] 126 1 T181 2 T73 1 T89 2
valid_sources[0x26] 330 1 T2 2 T133 14 T213 1
valid_sources[0x27] 110 1 T214 4 T211 1 T69 5
valid_sources[0x28] 117 1 T134 2 T9 1 T215 2
valid_sources[0x29] 247 1 T31 1 T216 1 T185 2
valid_sources[0x2a] 268 1 T217 10 T146 1 T73 1
valid_sources[0x2b] 126 1 T63 1 T197 1 T218 2
valid_sources[0x2c] 142 1 T69 1 T73 1 T94 1
valid_sources[0x2d] 162 1 T27 1 T10 1 T177 6
valid_sources[0x2e] 92 1 T208 1 T219 1 T220 1
valid_sources[0x2f] 86 1 T221 1 T191 1 T69 1
valid_sources[0x30] 114 1 T143 1 T222 1 T206 1
valid_sources[0x31] 97 1 T14 9 T223 1 T224 1
valid_sources[0x32] 79 1 T5 1 T62 1 T159 1
valid_sources[0x33] 94 1 T225 1 T89 2 T97 1
valid_sources[0x34] 100 1 T210 1 T11 4 T203 1
valid_sources[0x35] 172 1 T226 1 T85 1 T8 7
valid_sources[0x36] 146 1 T35 1 T10 1 T180 1
valid_sources[0x37] 98 1 T4 2 T50 1 T33 4
valid_sources[0x38] 108 1 T53 1 T71 3 T72 2
valid_sources[0x39] 80 1 T166 1 T69 1 T89 1
valid_sources[0x3a] 128 1 T18 1 T159 1 T38 1
valid_sources[0x3b] 117 1 T152 1 T153 1 T69 1
valid_sources[0x3c] 142 1 T227 1 T72 6 T89 6
valid_sources[0x3d] 143 1 T151 7 T228 1 T200 1
valid_sources[0x3e] 152 1 T12 1 T206 1 T89 1
valid_sources[0x3f] 113 1 T47 1 T134 1 T17 2
valid_sources[0x40] 182 1 T229 1 T36 1 T220 8
valid_sources[0x41] 115 1 T76 1 T230 1 T209 3
valid_sources[0x42] 121 1 T76 3 T156 1 T150 1
valid_sources[0x43] 83 1 T153 1 T69 2 T89 1
valid_sources[0x44] 125 1 T231 1 T220 3 T69 4
valid_sources[0x45] 84 1 T232 1 T60 1 T103 2
valid_sources[0x46] 104 1 T146 1 T38 1 T206 1
valid_sources[0x47] 106 1 T69 2 T89 2 T91 1
valid_sources[0x48] 138 1 T82 1 T89 2 T90 1
valid_sources[0x49] 113 1 T48 1 T76 1 T233 1
valid_sources[0x4a] 120 1 T4 2 T226 1 T195 1
valid_sources[0x4b] 150 1 T2 1 T38 1 T12 3
valid_sources[0x4c] 246 1 T73 3 T96 2 T70 2
valid_sources[0x4d] 105 1 T41 1 T89 2 T70 1
valid_sources[0x4e] 165 1 T68 13 T134 1 T145 7
valid_sources[0x4f] 239 1 T29 5 T234 1 T235 1
valid_sources[0x50] 103 1 T89 4 T135 1 T102 1
valid_sources[0x51] 121 1 T210 1 T202 1 T12 2
valid_sources[0x52] 115 1 T210 1 T195 1 T69 1
valid_sources[0x53] 158 1 T207 1 T161 1 T236 11
valid_sources[0x54] 176 1 T204 1 T89 3 T103 1
valid_sources[0x55] 216 1 T28 1 T43 1 T103 1
valid_sources[0x56] 102 1 T160 7 T145 1 T71 15
valid_sources[0x57] 106 1 T237 4 T73 1 T97 1
valid_sources[0x58] 100 1 T134 1 T102 1 T109 2
valid_sources[0x59] 100 1 T69 2 T60 1 T97 1
valid_sources[0x5a] 160 1 T23 9 T76 1 T58 1
valid_sources[0x5b] 85 1 T1 1 T210 2 T211 1
valid_sources[0x5c] 143 1 T146 1 T103 3 T99 18
valid_sources[0x5d] 105 1 T51 1 T208 3 T69 1
valid_sources[0x5e] 101 1 T208 1 T238 1 T206 1
valid_sources[0x5f] 128 1 T45 1 T89 1 T91 1
valid_sources[0x60] 100 1 T206 1 T69 1 T89 1
valid_sources[0x61] 136 1 T191 1 T201 1 T69 2
valid_sources[0x62] 128 1 T2 1 T89 2 T70 2
valid_sources[0x63] 74 1 T69 1 T91 2 T102 3
valid_sources[0x64] 115 1 T24 6 T206 1 T89 3
valid_sources[0x65] 152 1 T187 1 T89 1 T90 5
valid_sources[0x66] 117 1 T210 1 T220 3 T89 1
valid_sources[0x67] 245 1 T207 1 T16 1 T57 1
valid_sources[0x68] 334 1 T202 2 T69 1 T72 5
valid_sources[0x69] 199 1 T69 1 T73 2 T60 94
valid_sources[0x6a] 103 1 T10 1 T150 1 T239 5
valid_sources[0x6b] 122 1 T69 1 T72 9 T70 1
valid_sources[0x6c] 115 1 T28 1 T96 1 T90 2
valid_sources[0x6d] 90 1 T69 2 T89 1 T90 3
valid_sources[0x6e] 318 1 T69 1 T89 2 T138 3
valid_sources[0x6f] 408 1 T38 1 T17 1 T70 1
valid_sources[0x70] 261 1 T240 1 T96 2 T92 3
valid_sources[0x71] 90 1 T159 2 T206 1 T73 1
valid_sources[0x72] 75 1 T31 1 T219 2 T165 1
valid_sources[0x73] 115 1 T215 1 T153 1 T89 1
valid_sources[0x74] 133 1 T69 1 T89 2 T136 1
valid_sources[0x75] 555 1 T241 1 T69 4 T89 5
valid_sources[0x76] 127 1 T69 1 T89 8 T90 1
valid_sources[0x77] 217 1 T134 1 T147 1 T69 2
valid_sources[0x78] 101 1 T150 1 T242 1 T210 1
valid_sources[0x79] 124 1 T2 1 T69 3 T90 19
valid_sources[0x7a] 126 1 T183 1 T203 1 T211 1
valid_sources[0x7b] 135 1 T69 1 T71 3 T73 1
valid_sources[0x7c] 117 1 T69 1 T71 15 T89 2
valid_sources[0x7d] 80 1 T2 1 T146 1 T148 1
valid_sources[0x7e] 94 1 T72 7 T60 1 T89 8
valid_sources[0x7f] 160 1 T69 1 T72 9 T93 7
valid_sources[0x80] 168 1 T166 1 T243 1 T38 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 9440 1 T69 60 T75 1 T71 37
values[0x0] all_enables biggest_size 10631 1 T1 1 T2 5 T3 1
values[0x1] all_enables biggest_size 10405 1 T6 1 T1 5 T2 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%