Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
284358 |
1 |
|
T1 |
11 |
|
T4 |
27 |
|
T5 |
19 |
full_word |
596781 |
1 |
|
T1 |
8 |
|
T4 |
12 |
|
T5 |
9 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
880859 |
1 |
|
T1 |
19 |
|
T4 |
39 |
|
T5 |
28 |
auto[TlIntgErrCmd] |
103 |
1 |
|
T91 |
10 |
|
T92 |
6 |
|
T93 |
9 |
auto[TlIntgErrData] |
79 |
1 |
|
T91 |
4 |
|
T92 |
6 |
|
T93 |
6 |
auto[TlIntgErrBoth] |
98 |
1 |
|
T91 |
6 |
|
T92 |
8 |
|
T93 |
5 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
511266 |
1 |
|
T1 |
6 |
|
T4 |
7 |
|
T51 |
80 |
auto[1] |
369873 |
1 |
|
T1 |
13 |
|
T4 |
32 |
|
T5 |
28 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
209486 |
1 |
|
T1 |
1 |
|
T4 |
7 |
|
T31 |
10 |
auto[TlIntgErrNone] |
partial |
auto[1] |
74616 |
1 |
|
T1 |
10 |
|
T4 |
20 |
|
T5 |
19 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
301663 |
1 |
|
T1 |
5 |
|
T51 |
80 |
|
T31 |
2 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
295094 |
1 |
|
T1 |
3 |
|
T4 |
12 |
|
T5 |
9 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
44 |
1 |
|
T91 |
4 |
|
T92 |
5 |
|
T93 |
4 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
52 |
1 |
|
T91 |
6 |
|
T93 |
4 |
|
T103 |
3 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
1 |
1 |
|
T103 |
1 |
|
- |
- |
|
- |
- |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
6 |
1 |
|
T92 |
1 |
|
T93 |
1 |
|
T136 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
19 |
1 |
|
T91 |
1 |
|
T92 |
1 |
|
T93 |
2 |
auto[TlIntgErrData] |
partial |
auto[1] |
53 |
1 |
|
T91 |
3 |
|
T92 |
3 |
|
T93 |
3 |
auto[TlIntgErrData] |
full_word |
auto[0] |
5 |
1 |
|
T92 |
2 |
|
T93 |
1 |
|
T171 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
2 |
1 |
|
T103 |
1 |
|
T170 |
1 |
|
- |
- |
auto[TlIntgErrBoth] |
partial |
auto[0] |
43 |
1 |
|
T91 |
1 |
|
T92 |
4 |
|
T93 |
2 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
45 |
1 |
|
T91 |
4 |
|
T92 |
3 |
|
T93 |
3 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
5 |
1 |
|
T92 |
1 |
|
T135 |
1 |
|
T174 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
5 |
1 |
|
T91 |
1 |
|
T103 |
1 |
|
T175 |
1 |