Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.12 96.97 59.57 91.58 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 157045515 23070 0 0
late_debug_enable_rd_A 157045515 4284 0 0
late_debug_enable_regwen_rd_A 157045515 4107 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 157045515 23070 0 0
T60 544345 837 0 0
T69 197644 54 0 0
T70 102196 71 0 0
T71 11438 279 0 0
T72 26129 526 0 0
T89 20151 688 0 0
T90 15064 247 0 0
T91 190004 6 0 0
T92 300617 7 0 0
T93 314499 5 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 157045515 4284 0 0
T61 206022 812 0 0
T70 102196 32 0 0
T72 26129 203 0 0
T94 24246 57 0 0
T135 44407 36 0 0
T136 443204 76 0 0
T137 62310 22 0 0
T138 24623 262 0 0
T139 177725 216 0 0
T140 26220 234 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 157045515 4107 0 0
T61 206022 719 0 0
T70 102196 36 0 0
T72 26129 162 0 0
T94 24246 58 0 0
T135 44407 42 0 0
T136 443204 97 0 0
T137 62310 41 0 0
T138 24623 266 0 0
T139 177725 223 0 0
T140 26220 169 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%