Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	75.00						75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	56764357	5941931	0	0
MemTLResponseWithoutDebugIsError_A	56764357	1	0	0
NdmResetAckNeedsDebug_A	56764357	0	0	0
SbaTLRequestNeedsDebug_A	56764357	12038	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56764357	5941931	0	0
T1	993081	251685	0	0
T2	10461	0	0	0
T3	1692	0	0	0
T4	505708	152976	0	0
T5	0	291611	0	0
T7	895574	0	0	0
T8	0	29543	0	0
T13	344324	0	0	0
T14	68589	0	0	0
T18	0	130268	0	0
T23	0	75884	0	0
T25	0	69920	0	0
T27	22200	0	0	0
T31	0	283349	0	0
T32	0	2252	0	0
T33	0	443969	0	0
T34	62337	0	0	0
T35	4055	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56764357	1	0	0
T36	7860	1	0	0
T37	23098	0	0	0
T38	435375	0	0	0
T39	1278	0	0	0
T40	3115	0	0	0
T41	69317	0	0	0
T42	3605	0	0	0
T43	312521	0	0	0
T44	262562	0	0	0
T45	94349	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56764357	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56764357	12038	0	0
T5	180989	0	0	0
T7	895574	106	0	0
T13	344324	122	0	0
T14	68589	126	0	0
T23	125651	0	0	0
T27	22200	4	0	0
T34	62337	55	0	0
T35	4055	0	0	0
T46	370638	103	0	0
T47	0	96	0	0
T48	0	32	0	0
T49	0	31	0	0
T50	0	8	0	0
T51	10687	0	0	0