Module Definition
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Module : prim_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.62 100.00 62.50 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_dm_top.i_dm_csrs.i_fifo 90.62 100.00 62.50 100.00 100.00



Module Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.62 100.00 62.50 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.06 100.00 77.78 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
68.23 85.56 62.67 56.47 i_dm_csrs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 93.64 100.00 90.00 90.91


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Module : prim_fifo_sync
TotalCoveredPercent
Conditions161062.50
Logical161062.50
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT6,T1,T2
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (34'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T1,T2

Branch Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T6,T1,T2
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T6,T1,T2


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 56764357 19370 0 0
DepthKnown_A 56764357 55521744 0 0
RvalidKnown_A 56764357 55521744 0 0
WreadyKnown_A 56764357 55521744 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 56764357 19370 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 56764357 19370 0 0
T1 993081 78 0 0
T2 10461 1 0 0
T3 1692 1 0 0
T4 505708 194 0 0
T7 895574 347 0 0
T13 344324 122 0 0
T14 68589 178 0 0
T27 22200 44 0 0
T34 62337 66 0 0
T35 4055 1 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 56764357 55521744 0 0
T1 993081 785867 0 0
T2 10461 9773 0 0
T3 1692 1581 0 0
T4 505708 481122 0 0
T7 895574 892689 0 0
T13 344324 344041 0 0
T14 68589 67910 0 0
T27 22200 22067 0 0
T34 62337 62248 0 0
T35 4055 3665 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 56764357 55521744 0 0
T1 993081 785867 0 0
T2 10461 9773 0 0
T3 1692 1581 0 0
T4 505708 481122 0 0
T7 895574 892689 0 0
T13 344324 344041 0 0
T14 68589 67910 0 0
T27 22200 22067 0 0
T34 62337 62248 0 0
T35 4055 3665 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 56764357 55521744 0 0
T1 993081 785867 0 0
T2 10461 9773 0 0
T3 1692 1581 0 0
T4 505708 481122 0 0
T7 895574 892689 0 0
T13 344324 344041 0 0
T14 68589 67910 0 0
T27 22200 22067 0 0
T34 62337 62248 0 0
T35 4055 3665 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 56764357 19370 0 0
T1 993081 78 0 0
T2 10461 1 0 0
T3 1692 1 0 0
T4 505708 194 0 0
T7 895574 347 0 0
T13 344324 122 0 0
T14 68589 178 0 0
T27 22200 44 0 0
T34 62337 66 0 0
T35 4055 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%