Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T1,T2
01CoveredT6,T1,T2
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T1,T2
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT6,T1,T2
11CoveredT6,T1,T2

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8652405 8651081 0 0
selKnown1 63038080 63036752 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8652405 8651081 0 0
T1 18806 18802 0 0
T2 1148 1144 0 0
T3 609 605 0 0
T4 48884 48880 0 0
T5 0 30 0 0
T7 79276 79272 0 0
T13 27862 27858 0 0
T14 41880 41876 0 0
T23 0 25 0 0
T27 10685 10681 0 0
T31 0 12 0 0
T34 15090 15086 0 0
T35 326 322 0 0
T64 0 40 0 0
T67 0 10 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 63038080 63036752 0 0
T1 1002476 1002472 0 0
T2 11036 11032 0 0
T3 1997 1993 0 0
T4 530144 530140 0 0
T5 0 6 0 0
T6 16395 16394 0 0
T7 935222 935218 0 0
T13 358256 358252 0 0
T14 89538 89534 0 0
T23 0 8 0 0
T27 5344 5341 0 0
T31 0 8 0 0
T34 69883 69879 0 0
T35 4219 4215 0 0
T64 0 40 0 0
T67 0 10 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T1,T2
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T1,T2
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT6,T1,T2
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2377849 2377628 0 0
selKnown1 56764357 56764134 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2377849 2377628 0 0
T1 9391 9390 0 0
T2 573 572 0 0
T3 303 302 0 0
T4 24428 24427 0 0
T7 39628 39627 0 0
T13 13930 13929 0 0
T14 20931 20930 0 0
T27 5340 5339 0 0
T34 7544 7543 0 0
T35 162 161 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 56764357 56764134 0 0
T1 993081 993080 0 0
T2 10461 10460 0 0
T3 1692 1691 0 0
T4 505708 505707 0 0
T6 16395 16394 0 0
T7 895574 895573 0 0
T13 344324 344323 0 0
T14 68589 68588 0 0
T34 62337 62336 0 0
T35 4055 4054 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T1,T2
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T1,T2
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT6,T1,T2
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 810 589 0 0
selKnown1 626 403 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 810 589 0 0
T1 12 11 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 14 13 0 0
T5 0 8 0 0
T7 10 9 0 0
T13 1 0 0 0
T14 9 8 0 0
T23 0 4 0 0
T27 2 1 0 0
T31 0 6 0 0
T34 1 0 0 0
T35 1 0 0 0
T64 0 20 0 0
T67 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 626 403 0 0
T1 2 1 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 4 3 0 0
T5 0 3 0 0
T7 10 9 0 0
T13 1 0 0 0
T14 9 8 0 0
T23 0 4 0 0
T27 2 1 0 0
T31 0 4 0 0
T34 1 0 0 0
T35 1 0 0 0
T64 0 20 0 0
T67 0 5 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T1,T2
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT6,T1,T2

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6271590 6271148 0 0
selKnown1 6271390 6270950 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6271590 6271148 0 0
T1 9391 9390 0 0
T2 573 572 0 0
T3 304 303 0 0
T4 24428 24427 0 0
T7 39628 39627 0 0
T13 13930 13929 0 0
T14 20931 20930 0 0
T27 5341 5340 0 0
T34 7544 7543 0 0
T35 162 161 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6271390 6270950 0 0
T1 9391 9390 0 0
T2 573 572 0 0
T3 303 302 0 0
T4 24428 24427 0 0
T7 39628 39627 0 0
T13 13930 13929 0 0
T14 20931 20930 0 0
T27 5340 5339 0 0
T34 7544 7543 0 0
T35 162 161 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T1,T2
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T1,T2
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT6,T1,T2
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2156 1716 0 0
selKnown1 1707 1265 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2156 1716 0 0
T1 12 11 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 14 13 0 0
T5 0 22 0 0
T7 10 9 0 0
T13 1 0 0 0
T14 9 8 0 0
T23 0 21 0 0
T27 2 1 0 0
T31 0 6 0 0
T34 1 0 0 0
T35 1 0 0 0
T64 0 20 0 0
T67 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1707 1265 0 0
T1 2 1 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 4 3 0 0
T5 0 3 0 0
T7 10 9 0 0
T13 1 0 0 0
T14 9 8 0 0
T23 0 4 0 0
T27 2 1 0 0
T31 0 4 0 0
T34 1 0 0 0
T35 1 0 0 0
T64 0 20 0 0
T67 0 5 0 0

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