Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	181224	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	516231	1		T4	3		T7	2		T5	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	434636	1		T4	2		T7	1		T5	7
values[0x0]	128424	1		T4	1		T7	3		T5	6
values[0x1]	134395	1		T4	4		T7	2		T5	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	137651	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	559804	1		T4	6		T7	4		T5	7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2507	1		T25	1		T82	25		T79	57
valid_sources[0x01]	2492	1		T12	1		T67	9		T82	24
valid_sources[0x02]	2420	1		T11	1		T168	4		T69	11
valid_sources[0x03]	2549	1		T6	1		T33	4		T82	44
valid_sources[0x04]	3323	1		T170	2		T168	1		T82	4
valid_sources[0x05]	2807	1		T25	1		T170	9		T82	10
valid_sources[0x06]	2226	1		T161	1		T82	54		T79	10
valid_sources[0x07]	3614	1		T93	1		T21	14		T79	74
valid_sources[0x08]	1989	1		T82	37		T80	47		T117	102
valid_sources[0x09]	2820	1		T187	4		T82	4		T79	314
valid_sources[0x0a]	2184	1		T82	57		T80	40		T104	5
valid_sources[0x0b]	3090	1		T33	2		T188	1		T12	1
valid_sources[0x0c]	3098	1		T82	5		T83	3		T80	38
valid_sources[0x0d]	2685	1		T82	14		T79	16		T80	60
valid_sources[0x0e]	2381	1		T161	1		T82	1		T79	50
valid_sources[0x0f]	2329	1		T6	1		T168	1		T12	3
valid_sources[0x10]	2412	1		T63	4		T82	61		T83	4
valid_sources[0x11]	2724	1		T172	12		T82	11		T83	3
valid_sources[0x12]	2281	1		T82	5		T83	38		T80	31
valid_sources[0x13]	3027	1		T6	1		T37	12		T16	1
valid_sources[0x14]	2613	1		T82	27		T79	77		T80	32
valid_sources[0x15]	2245	1		T156	3		T189	1		T190	1
valid_sources[0x16]	3091	1		T82	22		T79	8		T80	48
valid_sources[0x17]	2566	1		T82	20		T83	16		T80	40
valid_sources[0x18]	2784	1		T82	4		T79	25		T80	51
valid_sources[0x19]	2871	1		T17	3		T22	1		T80	31
valid_sources[0x1a]	2409	1		T93	1		T29	1		T189	1
valid_sources[0x1b]	2768	1		T11	1		T63	1		T82	45
valid_sources[0x1c]	2461	1		T189	1		T82	15		T83	19
valid_sources[0x1d]	2784	1		T11	1		T82	33		T79	24
valid_sources[0x1e]	2819	1		T190	10		T82	10		T80	31
valid_sources[0x1f]	2787	1		T6	1		T82	28		T79	7
valid_sources[0x20]	3110	1		T13	2		T97	19		T188	2
valid_sources[0x21]	2520	1		T191	2		T82	3		T80	52
valid_sources[0x22]	2307	1		T6	1		T93	1		T12	2
valid_sources[0x23]	2908	1		T188	1		T64	13		T82	9
valid_sources[0x24]	2847	1		T23	7		T160	1		T82	22
valid_sources[0x25]	3407	1		T6	1		T25	1		T26	1
valid_sources[0x26]	2372	1		T48	1		T82	33		T79	30
valid_sources[0x27]	2727	1		T14	1		T160	4		T82	24
valid_sources[0x28]	2284	1		T62	4		T93	1		T11	1
valid_sources[0x29]	3140	1		T82	46		T79	14		T80	54
valid_sources[0x2a]	3448	1		T16	1		T82	11		T79	6
valid_sources[0x2b]	3093	1		T189	1		T82	4		T83	278
valid_sources[0x2c]	2843	1		T7	1		T189	2		T192	1
valid_sources[0x2d]	2492	1		T12	1		T26	1		T82	26
valid_sources[0x2e]	2742	1		T6	2		T192	1		T172	2
valid_sources[0x2f]	2400	1		T63	1		T82	20		T79	149
valid_sources[0x30]	3238	1		T63	3		T26	1		T82	74
valid_sources[0x31]	2750	1		T93	1		T193	1		T189	1
valid_sources[0x32]	3360	1		T168	8		T82	37		T80	41
valid_sources[0x33]	2577	1		T192	1		T64	10		T82	65
valid_sources[0x34]	2308	1		T16	2		T82	25		T79	26
valid_sources[0x35]	2477	1		T63	3		T79	3		T80	35
valid_sources[0x36]	2124	1		T62	3		T93	1		T16	2
valid_sources[0x37]	2332	1		T82	25		T83	21		T80	44
valid_sources[0x38]	2170	1		T66	1		T82	8		T80	25
valid_sources[0x39]	2319	1		T194	1		T163	1		T82	57
valid_sources[0x3a]	2855	1		T168	2		T82	8		T79	152
valid_sources[0x3b]	2502	1		T82	27		T80	33		T104	8
valid_sources[0x3c]	2838	1		T187	1		T82	6		T79	56
valid_sources[0x3d]	3401	1		T6	2		T188	1		T82	10
valid_sources[0x3e]	2333	1		T195	3		T64	19		T82	17
valid_sources[0x3f]	2885	1		T82	23		T79	6		T80	65
valid_sources[0x40]	2629	1		T93	1		T172	2		T82	15
valid_sources[0x41]	3188	1		T6	1		T33	2		T160	2
valid_sources[0x42]	3406	1		T188	1		T82	30		T83	5
valid_sources[0x43]	2999	1		T6	2		T63	11		T68	1
valid_sources[0x44]	2736	1		T93	1		T82	28		T79	4
valid_sources[0x45]	3416	1		T93	1		T16	1		T26	1
valid_sources[0x46]	2075	1		T156	4		T26	1		T79	31
valid_sources[0x47]	2479	1		T188	1		T189	2		T187	9
valid_sources[0x48]	2392	1		T37	2		T93	1		T25	1
valid_sources[0x49]	2193	1		T188	1		T82	22		T79	8
valid_sources[0x4a]	3032	1		T82	25		T79	27		T80	49
valid_sources[0x4b]	2638	1		T82	42		T79	2		T80	36
valid_sources[0x4c]	2691	1		T66	1		T187	4		T82	49
valid_sources[0x4d]	3386	1		T37	1		T19	11		T82	34
valid_sources[0x4e]	2686	1		T62	1		T189	2		T79	44
valid_sources[0x4f]	2796	1		T93	1		T188	2		T83	6
valid_sources[0x50]	2897	1		T82	16		T79	12		T80	38
valid_sources[0x51]	2275	1		T93	1		T188	1		T82	4
valid_sources[0x52]	2770	1		T82	68		T83	6		T79	3
valid_sources[0x53]	2563	1		T160	1		T82	14		T80	42
valid_sources[0x54]	2540	1		T14	1		T82	64		T79	42
valid_sources[0x55]	3187	1		T4	1		T170	14		T55	2
valid_sources[0x56]	2642	1		T82	55		T83	5		T79	1
valid_sources[0x57]	2935	1		T188	2		T196	1		T82	9
valid_sources[0x58]	2736	1		T11	1		T170	4		T16	2
valid_sources[0x59]	3119	1		T11	1		T68	1		T161	5
valid_sources[0x5a]	2467	1		T189	1		T160	7		T82	14
valid_sources[0x5b]	2489	1		T33	1		T16	1		T82	13
valid_sources[0x5c]	2208	1		T62	1		T48	13		T196	1
valid_sources[0x5d]	2957	1		T93	1		T16	4		T156	2
valid_sources[0x5e]	2505	1		T14	1		T83	6		T79	5
valid_sources[0x5f]	3480	1		T6	2		T82	21		T83	26
valid_sources[0x60]	2894	1		T62	2		T16	2		T82	21
valid_sources[0x61]	2382	1		T187	2		T163	2		T82	10
valid_sources[0x62]	2521	1		T160	5		T163	2		T80	35
valid_sources[0x63]	2449	1		T82	19		T79	19		T80	46
valid_sources[0x64]	3545	1		T93	1		T156	2		T68	4
valid_sources[0x65]	4138	1		T93	1		T194	1		T82	6
valid_sources[0x66]	2195	1		T16	1		T82	24		T79	20
valid_sources[0x67]	2482	1		T15	1		T82	8		T80	44
valid_sources[0x68]	2432	1		T62	2		T189	1		T82	73
valid_sources[0x69]	2402	1		T93	2		T161	2		T82	19
valid_sources[0x6a]	2716	1		T189	1		T26	1		T82	10
valid_sources[0x6b]	2459	1		T93	1		T14	1		T172	2
valid_sources[0x6c]	3088	1		T15	1		T163	4		T82	6
valid_sources[0x6d]	2440	1		T33	2		T79	13		T80	54
valid_sources[0x6e]	3355	1		T82	54		T79	6		T80	36
valid_sources[0x6f]	2969	1		T25	1		T15	1		T188	1
valid_sources[0x70]	2355	1		T4	1		T82	46		T80	42
valid_sources[0x71]	2499	1		T12	1		T66	1		T194	3
valid_sources[0x72]	2931	1		T197	2		T161	1		T82	24
valid_sources[0x73]	2210	1		T188	1		T80	27		T104	1
valid_sources[0x74]	3293	1		T13	1		T93	2		T48	2
valid_sources[0x75]	2945	1		T6	1		T82	58		T79	72
valid_sources[0x76]	2235	1		T160	1		T82	23		T79	2
valid_sources[0x77]	2826	1		T4	1		T13	2		T82	29
valid_sources[0x78]	2524	1		T62	5		T63	11		T82	19
valid_sources[0x79]	2656	1		T7	1		T6	1		T93	1
valid_sources[0x7a]	2642	1		T37	8		T93	2		T82	10
valid_sources[0x7b]	2866	1		T198	2		T82	39		T79	73
valid_sources[0x7c]	2696	1		T62	4		T100	8		T156	3
valid_sources[0x7d]	2533	1		T83	15		T80	34		T104	2
valid_sources[0x7e]	2980	1		T82	27		T79	81		T80	34
valid_sources[0x7f]	2393	1		T189	1		T82	20		T79	22
valid_sources[0x80]	2214	1		T26	2		T82	55		T79	61

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

263004

1

T5

3

T6

8

T33

2

values[0x0]

all_enables

biggest_size

126616

1

T7

2

T5

1

T6

3

values[0x1]

all_enables

biggest_size

126611

1

T4

3

T5

1

T6

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4673	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	19285	1		T1	1		T2	1		T8	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9216	1		T82	22		T83	6		T79	67
values[0x0]	7236	1		T1	1		T2	1		T8	1
values[0x1]	7506	1		T3	3		T9	4		T56	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3527	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20431	1		T1	1		T2	1		T8	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	110	1		T3	2		T152	8		T199	1
valid_sources[0x01]	96	1		T200	1		T25	1		T23	1
valid_sources[0x02]	61	1		T10	1		T98	2		T189	1
valid_sources[0x03]	164	1		T11	1		T27	1		T201	1
valid_sources[0x04]	85	1		T35	5		T202	1		T189	2
valid_sources[0x05]	118	1		T158	1		T129	1		T113	3
valid_sources[0x06]	171	1		T6	1		T62	1		T203	1
valid_sources[0x07]	72	1		T198	2		T109	1		T105	2
valid_sources[0x08]	69	1		T9	1		T204	12		T161	1
valid_sources[0x09]	70	1		T205	1		T206	1		T80	6
valid_sources[0x0a]	88	1		T4	2		T189	1		T207	1
valid_sources[0x0b]	88	1		T28	2		T193	1		T208	1
valid_sources[0x0c]	62	1		T209	1		T161	1		T81	1
valid_sources[0x0d]	75	1		T36	1		T210	1		T211	1
valid_sources[0x0e]	53	1		T80	9		T113	2		T114	1
valid_sources[0x0f]	115	1		T41	1		T212	4		T213	1
valid_sources[0x10]	96	1		T206	1		T116	4		T154	2
valid_sources[0x11]	94	1		T104	1		T105	2		T111	1
valid_sources[0x12]	90	1		T107	2		T62	1		T214	2
valid_sources[0x13]	80	1		T160	1		T81	1		T105	6
valid_sources[0x14]	92	1		T24	3		T215	1		T94	1
valid_sources[0x15]	61	1		T19	1		T80	9		T104	3
valid_sources[0x16]	106	1		T90	1		T25	1		T63	1
valid_sources[0x17]	199	1		T216	1		T105	1		T111	4
valid_sources[0x18]	99	1		T217	1		T80	2		T113	4
valid_sources[0x19]	82	1		T7	3		T218	2		T219	1
valid_sources[0x1a]	95	1		T6	5		T79	7		T81	1
valid_sources[0x1b]	72	1		T105	7		T111	7		T113	8
valid_sources[0x1c]	146	1		T220	1		T221	1		T104	4
valid_sources[0x1d]	67	1		T219	1		T161	1		T104	3
valid_sources[0x1e]	88	1		T160	4		T82	4		T80	2
valid_sources[0x1f]	115	1		T222	2		T210	2		T104	24
valid_sources[0x20]	74	1		T1	1		T39	2		T106	1
valid_sources[0x21]	79	1		T34	1		T219	1		T211	1
valid_sources[0x22]	76	1		T98	1		T81	1		T120	1
valid_sources[0x23]	76	1		T41	1		T223	3		T82	3
valid_sources[0x24]	93	1		T203	4		T120	2		T124	2
valid_sources[0x25]	94	1		T24	3		T207	3		T109	1
valid_sources[0x26]	78	1		T106	1		T11	2		T210	2
valid_sources[0x27]	155	1		T224	6		T80	3		T104	1
valid_sources[0x28]	63	1		T105	1		T129	1		T115	1
valid_sources[0x29]	85	1		T225	6		T36	1		T226	1
valid_sources[0x2a]	60	1		T11	1		T109	1		T105	1
valid_sources[0x2b]	77	1		T206	1		T129	1		T116	2
valid_sources[0x2c]	110	1		T9	1		T25	1		T29	1
valid_sources[0x2d]	69	1		T81	1		T122	1		T105	5
valid_sources[0x2e]	84	1		T78	1		T94	1		T189	1
valid_sources[0x2f]	71	1		T227	1		T50	1		T219	1
valid_sources[0x30]	59	1		T200	1		T192	2		T109	4
valid_sources[0x31]	86	1		T155	1		T228	1		T161	1
valid_sources[0x32]	93	1		T94	3		T219	1		T194	2
valid_sources[0x33]	56	1		T229	2		T118	2		T113	4
valid_sources[0x34]	118	1		T82	1		T117	10		T105	4
valid_sources[0x35]	80	1		T81	1		T121	2		T122	1
valid_sources[0x36]	60	1		T202	1		T81	1		T122	1
valid_sources[0x37]	114	1		T230	1		T25	1		T82	8
valid_sources[0x38]	100	1		T202	1		T86	1		T11	2
valid_sources[0x39]	98	1		T159	3		T29	3		T224	7
valid_sources[0x3a]	77	1		T18	2		T119	2		T111	4
valid_sources[0x3b]	73	1		T28	1		T36	1		T231	1
valid_sources[0x3c]	74	1		T153	2		T105	3		T154	1
valid_sources[0x3d]	117	1		T232	1		T233	9		T81	1
valid_sources[0x3e]	73	1		T111	3		T112	1		T113	6
valid_sources[0x3f]	63	1		T78	1		T28	2		T86	1
valid_sources[0x40]	100	1		T174	1		T81	1		T114	1
valid_sources[0x41]	77	1		T80	2		T81	1		T105	1
valid_sources[0x42]	77	1		T83	1		T80	3		T104	1
valid_sources[0x43]	53	1		T202	1		T234	1		T217	1
valid_sources[0x44]	91	1		T86	1		T215	1		T232	1
valid_sources[0x45]	69	1		T3	1		T31	1		T37	6
valid_sources[0x46]	103	1		T215	1		T206	2		T117	27
valid_sources[0x47]	113	1		T94	1		T16	8		T214	1
valid_sources[0x48]	110	1		T11	1		T104	13		T120	2
valid_sources[0x49]	83	1		T174	1		T229	1		T235	1
valid_sources[0x4a]	84	1		T81	1		T119	2		T111	8
valid_sources[0x4b]	111	1		T117	28		T111	1		T113	1
valid_sources[0x4c]	116	1		T20	1		T192	2		T64	1
valid_sources[0x4d]	66	1		T236	12		T237	3		T238	2
valid_sources[0x4e]	70	1		T94	1		T81	1		T113	1
valid_sources[0x4f]	151	1		T206	1		T104	23		T129	1
valid_sources[0x50]	84	1		T86	1		T239	1		T219	1
valid_sources[0x51]	79	1		T31	1		T4	1		T190	3
valid_sources[0x52]	75	1		T205	1		T109	1		T105	1
valid_sources[0x53]	84	1		T39	1		T81	3		T104	6
valid_sources[0x54]	79	1		T104	2		T109	1		T110	1
valid_sources[0x55]	173	1		T59	1		T24	1		T18	1
valid_sources[0x56]	94	1		T234	1		T25	1		T208	1
valid_sources[0x57]	107	1		T36	1		T79	7		T81	2
valid_sources[0x58]	97	1		T86	1		T62	1		T162	8
valid_sources[0x59]	76	1		T65	8		T86	1		T210	1
valid_sources[0x5a]	122	1		T62	1		T240	8		T168	6
valid_sources[0x5b]	78	1		T241	1		T105	2		T113	7
valid_sources[0x5c]	187	1		T202	1		T242	1		T52	5
valid_sources[0x5d]	123	1		T3	1		T229	1		T81	1
valid_sources[0x5e]	80	1		T109	3		T110	1		T113	2
valid_sources[0x5f]	81	1		T243	1		T80	10		T109	1
valid_sources[0x60]	52	1		T81	1		T120	1		T111	3
valid_sources[0x61]	150	1		T243	2		T224	1		T229	1
valid_sources[0x62]	72	1		T61	1		T211	1		T81	1
valid_sources[0x63]	70	1		T23	1		T104	6		T109	1
valid_sources[0x64]	65	1		T43	1		T86	1		T232	1
valid_sources[0x65]	96	1		T243	1		T93	7		T244	1
valid_sources[0x66]	79	1		T245	9		T244	1		T104	2
valid_sources[0x67]	84	1		T17	1		T246	1		T83	2
valid_sources[0x68]	116	1		T78	1		T215	1		T82	4
valid_sources[0x69]	107	1		T234	1		T169	2		T247	1
valid_sources[0x6a]	103	1		T222	3		T54	1		T55	1
valid_sources[0x6b]	87	1		T244	3		T21	1		T81	2
valid_sources[0x6c]	54	1		T86	1		T189	1		T104	1
valid_sources[0x6d]	59	1		T31	2		T62	1		T229	2
valid_sources[0x6e]	95	1		T89	3		T53	1		T82	5
valid_sources[0x6f]	57	1		T174	1		T105	1		T113	6
valid_sources[0x70]	116	1		T78	1		T97	1		T80	3
valid_sources[0x71]	78	1		T82	1		T79	5		T81	1
valid_sources[0x72]	74	1		T18	1		T60	1		T248	1
valid_sources[0x73]	77	1		T14	1		T219	1		T82	1
valid_sources[0x74]	95	1		T94	1		T79	5		T104	1
valid_sources[0x75]	62	1		T3	1		T29	1		T109	1
valid_sources[0x76]	57	1		T222	2		T211	1		T109	1
valid_sources[0x77]	63	1		T249	1		T80	1		T237	1
valid_sources[0x78]	63	1		T206	1		T110	1		T105	1
valid_sources[0x79]	101	1		T217	2		T117	21		T118	1
valid_sources[0x7a]	118	1		T250	10		T26	8		T80	2
valid_sources[0x7b]	79	1		T174	1		T161	1		T81	1
valid_sources[0x7c]	81	1		T174	1		T104	2		T110	2
valid_sources[0x7d]	133	1		T215	1		T113	2		T116	3
valid_sources[0x7e]	79	1		T251	8		T252	1		T104	1
valid_sources[0x7f]	100	1		T202	1		T187	6		T206	1
valid_sources[0x80]	92	1		T9	1		T29	1		T253	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6389

1

T82

22

T83

3

T79

24

values[0x0]

all_enables

biggest_size

6585

1

T1

1

T2

1

T8

1

values[0x1]

all_enables

biggest_size

6311

1

T3

1

T9

4

T56

1