Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
224732 |
1 |
|
T4 |
4 |
|
T7 |
4 |
|
T5 |
12 |
full_word |
517847 |
1 |
|
T4 |
3 |
|
T7 |
2 |
|
T5 |
5 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
742289 |
1 |
|
T4 |
7 |
|
T7 |
6 |
|
T5 |
17 |
auto[TlIntgErrCmd] |
87 |
1 |
|
T79 |
3 |
|
T80 |
9 |
|
T110 |
5 |
auto[TlIntgErrData] |
100 |
1 |
|
T79 |
4 |
|
T80 |
6 |
|
T109 |
3 |
auto[TlIntgErrBoth] |
103 |
1 |
|
T79 |
13 |
|
T80 |
5 |
|
T109 |
7 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
436576 |
1 |
|
T4 |
2 |
|
T7 |
1 |
|
T5 |
7 |
auto[1] |
306003 |
1 |
|
T4 |
5 |
|
T7 |
5 |
|
T5 |
10 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
173268 |
1 |
|
T4 |
2 |
|
T7 |
1 |
|
T5 |
4 |
auto[TlIntgErrNone] |
partial |
auto[1] |
51199 |
1 |
|
T4 |
2 |
|
T7 |
3 |
|
T5 |
8 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
263190 |
1 |
|
T5 |
3 |
|
T6 |
8 |
|
T33 |
2 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
254632 |
1 |
|
T4 |
3 |
|
T7 |
2 |
|
T5 |
2 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
30 |
1 |
|
T80 |
4 |
|
T110 |
1 |
|
T179 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
50 |
1 |
|
T79 |
3 |
|
T80 |
4 |
|
T110 |
3 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
3 |
1 |
|
T110 |
1 |
|
T180 |
1 |
|
T181 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
4 |
1 |
|
T80 |
1 |
|
T178 |
1 |
|
T182 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
42 |
1 |
|
T79 |
2 |
|
T80 |
2 |
|
T109 |
1 |
auto[TlIntgErrData] |
partial |
auto[1] |
50 |
1 |
|
T79 |
2 |
|
T80 |
3 |
|
T109 |
1 |
auto[TlIntgErrData] |
full_word |
auto[0] |
3 |
1 |
|
T80 |
1 |
|
T180 |
1 |
|
T183 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
5 |
1 |
|
T109 |
1 |
|
T184 |
1 |
|
T182 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
38 |
1 |
|
T79 |
7 |
|
T109 |
2 |
|
T110 |
2 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
55 |
1 |
|
T79 |
6 |
|
T80 |
5 |
|
T109 |
4 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
2 |
1 |
|
T180 |
1 |
|
T185 |
1 |
|
- |
- |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
8 |
1 |
|
T109 |
1 |
|
T179 |
1 |
|
T175 |
1 |