Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.12 96.97 59.57 91.58 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 113297123 14202 0 0
late_debug_enable_rd_A 113297123 2693 0 0
late_debug_enable_regwen_rd_A 113297123 3028 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 113297123 14202 0 0
T79 438930 7 0 0
T80 44886 5 0 0
T81 56465 42 0 0
T104 12657 589 0 0
T105 21527 140 0 0
T109 63293 2 0 0
T110 102257 4 0 0
T111 26953 63 0 0
T112 4382 13 0 0
T113 6490 420 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 113297123 2693 0 0
T109 63293 34 0 0
T110 102257 40 0 0
T114 18926 28 0 0
T118 10595 1 0 0
T120 19884 33 0 0
T121 56818 41 0 0
T122 49372 23 0 0
T123 9583 8 0 0
T131 8536 5 0 0
T154 16618 44 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 113297123 3028 0 0
T109 63293 22 0 0
T110 102257 40 0 0
T114 18926 18 0 0
T118 10595 12 0 0
T120 19884 10 0 0
T121 56818 36 0 0
T122 49372 24 0 0
T123 9583 7 0 0
T131 8536 7 0 0
T154 16618 34 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%