Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	75.00						75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	44203368	5497808	0	0
MemTLResponseWithoutDebugIsError_A	44203368	9	0	0
NdmResetAckNeedsDebug_A	44203368	0	0	0
SbaTLRequestNeedsDebug_A	44203368	7946	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44203368	5497808	0	0
T4	306930	49392	0	0
T5	199657	45542	0	0
T6	0	15862	0	0
T7	380762	91203	0	0
T20	0	37375	0	0
T24	0	240549	0	0
T28	0	113367	0	0
T33	0	3241	0	0
T35	654933	0	0	0
T37	0	366862	0	0
T38	0	109323	0	0
T39	2725	0	0	0
T40	5164	0	0	0
T41	4677	0	0	0
T42	63639	0	0	0
T43	507999	0	0	0
T44	1557	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44203368	9	0	0
T45	2910	4	0	0
T46	0	5	0	0
T47	4726	0	0	0
T48	132521	0	0	0
T49	10583	0	0	0
T50	59984	0	0	0
T51	384207	0	0	0
T52	94232	0	0	0
T53	3781	0	0	0
T54	6868	0	0	0
T55	43079	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44203368	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44203368	7946	0	0
T1	280625	85	0	0
T2	139710	19	0	0
T3	1113	0	0	0
T8	5068	0	0	0
T9	377677	0	0	0
T10	123648	114	0	0
T30	0	72	0	0
T31	0	58	0	0
T32	0	16	0	0
T34	5070	0	0	0
T56	19086	79	0	0
T57	507681	114	0	0
T58	25693	150	0	0
T59	0	104	0	0