Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T8
01CoveredT1,T2,T8
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T8
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T8
11CoveredT1,T2,T8

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 7563757 7562439 0 0
selKnown1 49702324 49701002 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 7563757 7562439 0 0
T1 18777 18775 0 0
T2 23530 23528 0 0
T3 1836 1834 0 0
T4 0 10 0 0
T5 0 2 0 0
T6 0 20 0 0
T7 0 8 0 0
T8 1 0 0 0
T9 29196 29192 0 0
T10 27713 27711 0 0
T30 10 8 0 0
T31 12 10 0 0
T32 0 12 0 0
T34 599 595 0 0
T35 0 16 0 0
T42 0 12 0 0
T56 18971 18967 0 0
T57 28482 28478 0 0
T58 31668 31664 0 0
T70 139 273 0 0
T71 2 0 0 0
T78 2 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 49702324 49701002 0 0
T1 290013 290011 0 0
T2 151475 151473 0 0
T3 2031 2029 0 0
T4 0 6 0 0
T5 0 2 0 0
T6 0 10 0 0
T7 0 8 0 0
T8 5068 5067 0 0
T9 392267 392263 0 0
T10 137504 137502 0 0
T30 10 8 0 0
T31 12 10 0 0
T32 0 12 0 0
T34 5370 5366 0 0
T35 0 16 0 0
T42 0 12 0 0
T56 28572 28568 0 0
T57 521923 521919 0 0
T58 41528 41524 0 0
T70 139 136 0 0
T71 2 0 0 0
T78 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T8
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T8
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T8
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2064189 2063968 0 0
selKnown1 44203368 44203145 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2064189 2063968 0 0
T1 9388 9387 0 0
T2 11765 11764 0 0
T3 918 917 0 0
T9 14582 14581 0 0
T10 13856 13855 0 0
T34 298 297 0 0
T56 9484 9483 0 0
T57 14240 14239 0 0
T58 15833 15832 0 0
T70 137 136 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 44203368 44203145 0 0
T1 280625 280624 0 0
T2 139710 139709 0 0
T3 1113 1112 0 0
T8 5068 5067 0 0
T9 377677 377676 0 0
T10 123648 123647 0 0
T34 5070 5069 0 0
T56 19086 19085 0 0
T57 507681 507680 0 0
T58 25693 25692 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T8
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T8
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T8
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 732 511 0 0
selKnown1 632 409 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 732 511 0 0
T4 0 5 0 0
T5 0 1 0 0
T6 0 6 0 0
T7 0 4 0 0
T9 11 10 0 0
T30 5 4 0 0
T31 6 5 0 0
T32 0 6 0 0
T34 1 0 0 0
T35 0 8 0 0
T42 0 6 0 0
T56 1 0 0 0
T57 1 0 0 0
T58 1 0 0 0
T70 1 0 0 0
T71 1 0 0 0
T78 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 632 409 0 0
T4 0 3 0 0
T5 0 1 0 0
T6 0 5 0 0
T7 0 4 0 0
T9 4 3 0 0
T30 5 4 0 0
T31 6 5 0 0
T32 0 6 0 0
T34 1 0 0 0
T35 0 8 0 0
T42 0 6 0 0
T56 1 0 0 0
T57 1 0 0 0
T58 1 0 0 0
T70 1 0 0 0
T71 1 0 0 0
T78 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T8
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T8

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 5496903 5496464 0 0
selKnown1 5496699 5496262 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 5496903 5496464 0 0
T1 9389 9388 0 0
T2 11765 11764 0 0
T3 918 917 0 0
T8 1 0 0 0
T9 14583 14582 0 0
T10 13857 13856 0 0
T34 299 298 0 0
T56 9485 9484 0 0
T57 14240 14239 0 0
T58 15833 15832 0 0
T70 0 137 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 5496699 5496262 0 0
T1 9388 9387 0 0
T2 11765 11764 0 0
T3 918 917 0 0
T9 14582 14581 0 0
T10 13856 13855 0 0
T34 298 297 0 0
T56 9484 9483 0 0
T57 14240 14239 0 0
T58 15833 15832 0 0
T70 137 136 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T8
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T8
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T8
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1933 1496 0 0
selKnown1 1625 1186 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1933 1496 0 0
T4 0 5 0 0
T5 0 1 0 0
T6 0 14 0 0
T7 0 4 0 0
T9 20 19 0 0
T30 5 4 0 0
T31 6 5 0 0
T32 0 6 0 0
T34 1 0 0 0
T35 0 8 0 0
T42 0 6 0 0
T56 1 0 0 0
T57 1 0 0 0
T58 1 0 0 0
T70 1 0 0 0
T71 1 0 0 0
T78 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1625 1186 0 0
T4 0 3 0 0
T5 0 1 0 0
T6 0 5 0 0
T7 0 4 0 0
T9 4 3 0 0
T30 5 4 0 0
T31 6 5 0 0
T32 0 6 0 0
T34 1 0 0 0
T35 0 8 0 0
T42 0 6 0 0
T56 1 0 0 0
T57 1 0 0 0
T58 1 0 0 0
T70 1 0 0 0
T71 1 0 0 0
T78 1 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%