SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 223 | 223 | 0 | 0 |
OutputsKnown_A | 44203368 | 44161385 | 0 | 0 |
gen_no_flops.OutputDelay_A | 44203368 | 44161385 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223 | 223 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T56 | 1 | 1 | 0 | 0 |
T57 | 1 | 1 | 0 | 0 |
T58 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44203368 | 44161385 | 0 | 0 |
T1 | 280625 | 280563 | 0 | 0 |
T2 | 139710 | 139627 | 0 | 0 |
T3 | 1113 | 1061 | 0 | 0 |
T8 | 5068 | 5015 | 0 | 0 |
T9 | 377677 | 377438 | 0 | 0 |
T10 | 123648 | 123584 | 0 | 0 |
T34 | 5070 | 5019 | 0 | 0 |
T56 | 19086 | 19003 | 0 | 0 |
T57 | 507681 | 507616 | 0 | 0 |
T58 | 25693 | 25635 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44203368 | 44161385 | 0 | 0 |
T1 | 280625 | 280563 | 0 | 0 |
T2 | 139710 | 139627 | 0 | 0 |
T3 | 1113 | 1061 | 0 | 0 |
T8 | 5068 | 5015 | 0 | 0 |
T9 | 377677 | 377438 | 0 | 0 |
T10 | 123648 | 123584 | 0 | 0 |
T34 | 5070 | 5019 | 0 | 0 |
T56 | 19086 | 19003 | 0 | 0 |
T57 | 507681 | 507616 | 0 | 0 |
T58 | 25693 | 25635 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |