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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.84 95.32 80.00 89.42 74.36 85.67 98.32 56.79


Total test records in report: 443
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T91 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2442860338 Jul 01 10:40:24 AM PDT 24 Jul 01 10:40:51 AM PDT 24 3163661397 ps
T99 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2811487947 Jul 01 10:40:04 AM PDT 24 Jul 01 10:41:12 AM PDT 24 1104906467 ps
T302 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.657908160 Jul 01 10:40:20 AM PDT 24 Jul 01 10:40:24 AM PDT 24 171513827 ps
T303 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1508234159 Jul 01 10:40:37 AM PDT 24 Jul 01 10:40:47 AM PDT 24 14081376309 ps
T304 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2927642634 Jul 01 10:40:24 AM PDT 24 Jul 01 10:40:27 AM PDT 24 414127546 ps
T305 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3785410681 Jul 01 10:40:15 AM PDT 24 Jul 01 10:40:31 AM PDT 24 5243581398 ps
T306 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3510013835 Jul 01 10:40:09 AM PDT 24 Jul 01 10:40:15 AM PDT 24 3803556239 ps
T107 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2615495513 Jul 01 10:39:59 AM PDT 24 Jul 01 10:40:05 AM PDT 24 2778618959 ps
T67 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.641440115 Jul 01 10:40:39 AM PDT 24 Jul 01 10:41:18 AM PDT 24 40258302133 ps
T307 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.595865466 Jul 01 10:40:31 AM PDT 24 Jul 01 10:40:33 AM PDT 24 115840678 ps
T308 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.668808919 Jul 01 10:40:17 AM PDT 24 Jul 01 10:40:32 AM PDT 24 4154227273 ps
T92 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2876791398 Jul 01 10:40:24 AM PDT 24 Jul 01 10:40:34 AM PDT 24 3815666776 ps
T100 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.4064382863 Jul 01 10:40:36 AM PDT 24 Jul 01 10:40:43 AM PDT 24 235527425 ps
T309 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2018974705 Jul 01 10:40:19 AM PDT 24 Jul 01 10:40:25 AM PDT 24 542330601 ps
T310 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1595992477 Jul 01 10:41:06 AM PDT 24 Jul 01 10:41:16 AM PDT 24 13208103831 ps
T311 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2217546791 Jul 01 10:40:22 AM PDT 24 Jul 01 10:40:28 AM PDT 24 2060605737 ps
T101 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2772311807 Jul 01 10:40:41 AM PDT 24 Jul 01 10:40:43 AM PDT 24 90950929 ps
T312 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.145954114 Jul 01 10:40:21 AM PDT 24 Jul 01 10:40:25 AM PDT 24 197872620 ps
T102 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4071060186 Jul 01 10:40:26 AM PDT 24 Jul 01 10:41:34 AM PDT 24 2357998743 ps
T103 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.751709901 Jul 01 10:40:33 AM PDT 24 Jul 01 10:40:42 AM PDT 24 1014454189 ps
T313 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1311140242 Jul 01 10:40:11 AM PDT 24 Jul 01 10:40:29 AM PDT 24 5763535939 ps
T93 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.4249159186 Jul 01 10:40:15 AM PDT 24 Jul 01 10:40:25 AM PDT 24 1745898377 ps
T104 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1921710339 Jul 01 10:40:28 AM PDT 24 Jul 01 10:41:07 AM PDT 24 40713760312 ps
T94 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3277346161 Jul 01 10:40:27 AM PDT 24 Jul 01 10:40:37 AM PDT 24 216924466 ps
T314 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4066638824 Jul 01 10:40:32 AM PDT 24 Jul 01 10:40:34 AM PDT 24 427694795 ps
T95 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3146958357 Jul 01 10:40:52 AM PDT 24 Jul 01 10:40:57 AM PDT 24 562336034 ps
T105 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3130634174 Jul 01 10:40:35 AM PDT 24 Jul 01 10:40:38 AM PDT 24 377576690 ps
T109 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3720233549 Jul 01 10:40:30 AM PDT 24 Jul 01 10:40:34 AM PDT 24 130929615 ps
T163 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3775632740 Jul 01 10:40:18 AM PDT 24 Jul 01 10:40:32 AM PDT 24 4085672336 ps
T161 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1719531775 Jul 01 10:40:31 AM PDT 24 Jul 01 10:40:52 AM PDT 24 5291162268 ps
T315 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1582376119 Jul 01 10:40:22 AM PDT 24 Jul 01 10:40:28 AM PDT 24 131589155 ps
T110 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1651382915 Jul 01 10:40:19 AM PDT 24 Jul 01 10:40:59 AM PDT 24 3200677055 ps
T316 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2661405119 Jul 01 10:40:16 AM PDT 24 Jul 01 10:40:20 AM PDT 24 430125719 ps
T317 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.4172828088 Jul 01 10:40:23 AM PDT 24 Jul 01 10:40:28 AM PDT 24 832487120 ps
T318 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2791825933 Jul 01 10:40:24 AM PDT 24 Jul 01 10:41:04 AM PDT 24 62753392555 ps
T106 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1338727574 Jul 01 10:40:40 AM PDT 24 Jul 01 10:40:44 AM PDT 24 177140086 ps
T111 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.831610223 Jul 01 10:40:35 AM PDT 24 Jul 01 10:40:38 AM PDT 24 179917874 ps
T319 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2796816355 Jul 01 10:40:58 AM PDT 24 Jul 01 10:41:02 AM PDT 24 2078433509 ps
T129 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3794897560 Jul 01 10:40:19 AM PDT 24 Jul 01 10:40:25 AM PDT 24 363401294 ps
T320 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.739444502 Jul 01 10:40:00 AM PDT 24 Jul 01 10:40:07 AM PDT 24 2952664924 ps
T130 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4108216211 Jul 01 10:40:50 AM PDT 24 Jul 01 10:40:53 AM PDT 24 114974395 ps
T321 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3879498031 Jul 01 10:40:20 AM PDT 24 Jul 01 10:40:25 AM PDT 24 44637608 ps
T322 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3247964177 Jul 01 10:40:24 AM PDT 24 Jul 01 10:40:35 AM PDT 24 4501910756 ps
T112 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1222755227 Jul 01 10:40:32 AM PDT 24 Jul 01 10:40:35 AM PDT 24 416809589 ps
T113 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1363403960 Jul 01 10:40:20 AM PDT 24 Jul 01 10:40:52 AM PDT 24 2218538914 ps
T159 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.343006760 Jul 01 10:40:33 AM PDT 24 Jul 01 10:40:53 AM PDT 24 1405473545 ps
T323 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4279843998 Jul 01 10:40:42 AM PDT 24 Jul 01 10:40:45 AM PDT 24 83210748 ps
T324 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3295898386 Jul 01 10:40:29 AM PDT 24 Jul 01 10:40:32 AM PDT 24 48327271 ps
T325 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.25033003 Jul 01 10:40:05 AM PDT 24 Jul 01 10:40:07 AM PDT 24 574448080 ps
T326 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2992739797 Jul 01 10:40:15 AM PDT 24 Jul 01 10:40:25 AM PDT 24 767664764 ps
T327 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4100765202 Jul 01 10:40:45 AM PDT 24 Jul 01 10:40:48 AM PDT 24 133597388 ps
T114 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3522947098 Jul 01 10:40:25 AM PDT 24 Jul 01 10:40:30 AM PDT 24 134021317 ps
T117 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3746013340 Jul 01 10:40:33 AM PDT 24 Jul 01 10:40:37 AM PDT 24 319499079 ps
T115 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3412679302 Jul 01 10:40:21 AM PDT 24 Jul 01 10:40:29 AM PDT 24 292589393 ps
T125 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.168184472 Jul 01 10:40:10 AM PDT 24 Jul 01 10:40:21 AM PDT 24 1128750948 ps
T328 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.84060150 Jul 01 10:41:07 AM PDT 24 Jul 01 10:41:09 AM PDT 24 367734720 ps
T121 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1400177521 Jul 01 10:40:00 AM PDT 24 Jul 01 10:41:14 AM PDT 24 10185702984 ps
T329 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.356139746 Jul 01 10:41:12 AM PDT 24 Jul 01 10:41:15 AM PDT 24 462626344 ps
T118 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.392949504 Jul 01 10:40:23 AM PDT 24 Jul 01 10:41:23 AM PDT 24 2981170473 ps
T164 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1507386725 Jul 01 10:40:10 AM PDT 24 Jul 01 10:40:29 AM PDT 24 4258369152 ps
T330 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3373816184 Jul 01 10:40:25 AM PDT 24 Jul 01 10:40:33 AM PDT 24 1905848644 ps
T68 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.261032880 Jul 01 10:40:29 AM PDT 24 Jul 01 10:40:50 AM PDT 24 24332233627 ps
T331 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2484533624 Jul 01 10:40:26 AM PDT 24 Jul 01 10:40:29 AM PDT 24 153282463 ps
T332 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1864675969 Jul 01 10:40:02 AM PDT 24 Jul 01 10:40:12 AM PDT 24 4802695290 ps
T333 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2458666614 Jul 01 10:40:19 AM PDT 24 Jul 01 10:40:26 AM PDT 24 105607979 ps
T334 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1405544616 Jul 01 10:41:03 AM PDT 24 Jul 01 10:41:12 AM PDT 24 2899615451 ps
T335 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1118513890 Jul 01 10:41:11 AM PDT 24 Jul 01 10:41:16 AM PDT 24 1168955854 ps
T336 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2127028656 Jul 01 10:41:13 AM PDT 24 Jul 01 10:41:21 AM PDT 24 363567451 ps
T337 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.846173461 Jul 01 10:40:40 AM PDT 24 Jul 01 10:40:44 AM PDT 24 192434406 ps
T338 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3989259996 Jul 01 10:40:31 AM PDT 24 Jul 01 10:40:36 AM PDT 24 809035339 ps
T339 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3170632492 Jul 01 10:40:43 AM PDT 24 Jul 01 10:41:31 AM PDT 24 31968145306 ps
T69 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1267564931 Jul 01 10:40:27 AM PDT 24 Jul 01 10:42:06 AM PDT 24 48885522638 ps
T340 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3334744819 Jul 01 10:40:30 AM PDT 24 Jul 01 10:40:34 AM PDT 24 286334419 ps
T341 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.842801024 Jul 01 10:40:07 AM PDT 24 Jul 01 10:40:13 AM PDT 24 309025556 ps
T342 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1142474869 Jul 01 10:41:05 AM PDT 24 Jul 01 10:41:07 AM PDT 24 821443547 ps
T166 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2905210099 Jul 01 10:40:20 AM PDT 24 Jul 01 10:40:52 AM PDT 24 29791039143 ps
T343 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3712490879 Jul 01 10:40:20 AM PDT 24 Jul 01 10:40:25 AM PDT 24 119452432 ps
T344 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2899747808 Jul 01 10:40:11 AM PDT 24 Jul 01 10:40:22 AM PDT 24 4962669376 ps
T126 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3162819052 Jul 01 10:40:28 AM PDT 24 Jul 01 10:40:33 AM PDT 24 538062040 ps
T345 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.570942017 Jul 01 10:40:24 AM PDT 24 Jul 01 10:40:37 AM PDT 24 2425083462 ps
T346 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2182778849 Jul 01 10:40:18 AM PDT 24 Jul 01 10:40:23 AM PDT 24 290386854 ps
T127 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.142625544 Jul 01 10:41:03 AM PDT 24 Jul 01 10:41:09 AM PDT 24 637348496 ps
T347 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3774052492 Jul 01 10:40:51 AM PDT 24 Jul 01 10:40:53 AM PDT 24 75481949 ps
T348 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2787143420 Jul 01 10:40:21 AM PDT 24 Jul 01 10:40:41 AM PDT 24 20835737475 ps
T349 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2903475171 Jul 01 10:40:32 AM PDT 24 Jul 01 10:40:35 AM PDT 24 158636965 ps
T108 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3979331827 Jul 01 10:40:33 AM PDT 24 Jul 01 10:40:53 AM PDT 24 8807507746 ps
T350 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2920134803 Jul 01 10:40:32 AM PDT 24 Jul 01 10:41:05 AM PDT 24 18378638051 ps
T351 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2162946200 Jul 01 10:40:23 AM PDT 24 Jul 01 10:40:37 AM PDT 24 4168226308 ps
T157 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.771778497 Jul 01 10:40:19 AM PDT 24 Jul 01 10:41:12 AM PDT 24 16573318720 ps
T116 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2467752626 Jul 01 10:41:11 AM PDT 24 Jul 01 10:41:16 AM PDT 24 923764237 ps
T352 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3565124640 Jul 01 10:40:28 AM PDT 24 Jul 01 10:40:47 AM PDT 24 4503482742 ps
T353 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1419453731 Jul 01 10:40:20 AM PDT 24 Jul 01 10:40:25 AM PDT 24 244480337 ps
T354 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.324851099 Jul 01 10:40:31 AM PDT 24 Jul 01 10:40:33 AM PDT 24 161070770 ps
T355 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1642093976 Jul 01 10:40:24 AM PDT 24 Jul 01 10:40:27 AM PDT 24 143379243 ps
T356 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1860949834 Jul 01 10:40:50 AM PDT 24 Jul 01 10:41:51 AM PDT 24 20274712913 ps
T128 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1606492819 Jul 01 10:39:55 AM PDT 24 Jul 01 10:40:00 AM PDT 24 450238081 ps
T158 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1393290498 Jul 01 10:40:27 AM PDT 24 Jul 01 10:40:34 AM PDT 24 105148361 ps
T357 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1122953943 Jul 01 10:40:26 AM PDT 24 Jul 01 10:40:32 AM PDT 24 2978308441 ps
T358 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.766044467 Jul 01 10:40:25 AM PDT 24 Jul 01 10:42:25 AM PDT 24 47627194336 ps
T165 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2192520495 Jul 01 10:40:30 AM PDT 24 Jul 01 10:40:53 AM PDT 24 6131112736 ps
T359 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3769544707 Jul 01 10:40:24 AM PDT 24 Jul 01 10:40:30 AM PDT 24 182119812 ps
T360 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.505989424 Jul 01 10:41:13 AM PDT 24 Jul 01 10:41:18 AM PDT 24 738789255 ps
T361 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3922008271 Jul 01 10:40:28 AM PDT 24 Jul 01 10:40:33 AM PDT 24 275733651 ps
T362 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3140016693 Jul 01 10:40:51 AM PDT 24 Jul 01 10:40:59 AM PDT 24 384464328 ps
T363 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1159255567 Jul 01 10:40:03 AM PDT 24 Jul 01 10:40:05 AM PDT 24 160042142 ps
T364 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3458288900 Jul 01 10:41:07 AM PDT 24 Jul 01 10:41:10 AM PDT 24 402804350 ps
T365 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2803363083 Jul 01 10:39:57 AM PDT 24 Jul 01 10:40:00 AM PDT 24 226331425 ps
T366 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3709341715 Jul 01 10:40:06 AM PDT 24 Jul 01 10:40:26 AM PDT 24 3654468080 ps
T367 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.4149467924 Jul 01 10:40:53 AM PDT 24 Jul 01 10:40:57 AM PDT 24 134835361 ps
T368 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.618136258 Jul 01 10:40:42 AM PDT 24 Jul 01 10:40:57 AM PDT 24 2277410776 ps
T70 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.304866953 Jul 01 10:41:00 AM PDT 24 Jul 01 10:41:02 AM PDT 24 3504302740 ps
T369 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.4238282511 Jul 01 10:40:10 AM PDT 24 Jul 01 10:40:13 AM PDT 24 151492267 ps
T370 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.725855306 Jul 01 10:40:30 AM PDT 24 Jul 01 10:40:39 AM PDT 24 2366645607 ps
T371 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.124437860 Jul 01 10:40:54 AM PDT 24 Jul 01 10:41:03 AM PDT 24 1276627107 ps
T372 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3821445813 Jul 01 10:40:33 AM PDT 24 Jul 01 10:40:38 AM PDT 24 2009948918 ps
T373 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2614306757 Jul 01 10:40:43 AM PDT 24 Jul 01 10:40:53 AM PDT 24 2432724858 ps
T374 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.590676298 Jul 01 10:40:56 AM PDT 24 Jul 01 10:40:59 AM PDT 24 145033599 ps
T375 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.42586511 Jul 01 10:41:13 AM PDT 24 Jul 01 10:41:19 AM PDT 24 289604672 ps
T376 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1828587720 Jul 01 10:40:20 AM PDT 24 Jul 01 10:40:32 AM PDT 24 11760913790 ps
T377 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.956151134 Jul 01 10:40:24 AM PDT 24 Jul 01 10:40:27 AM PDT 24 127596268 ps
T378 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3054279000 Jul 01 10:40:14 AM PDT 24 Jul 01 10:40:28 AM PDT 24 12764417760 ps
T379 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1401747069 Jul 01 10:40:41 AM PDT 24 Jul 01 10:40:49 AM PDT 24 98687920 ps
T380 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3791164638 Jul 01 10:40:09 AM PDT 24 Jul 01 10:40:12 AM PDT 24 45710982 ps
T381 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2795355009 Jul 01 10:40:11 AM PDT 24 Jul 01 10:40:15 AM PDT 24 210699498 ps
T382 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3777026480 Jul 01 10:40:41 AM PDT 24 Jul 01 10:40:45 AM PDT 24 569365908 ps
T383 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.225839586 Jul 01 10:40:23 AM PDT 24 Jul 01 10:40:31 AM PDT 24 323040553 ps
T384 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2339600419 Jul 01 10:40:58 AM PDT 24 Jul 01 10:41:01 AM PDT 24 418019775 ps
T162 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3738944522 Jul 01 10:41:04 AM PDT 24 Jul 01 10:41:16 AM PDT 24 3294633248 ps
T385 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1738717770 Jul 01 10:40:18 AM PDT 24 Jul 01 10:40:21 AM PDT 24 59150700 ps
T386 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2686626126 Jul 01 10:40:31 AM PDT 24 Jul 01 10:40:33 AM PDT 24 79473835 ps
T387 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.154404550 Jul 01 10:40:19 AM PDT 24 Jul 01 10:40:25 AM PDT 24 133612046 ps
T388 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3664983661 Jul 01 10:40:36 AM PDT 24 Jul 01 10:40:51 AM PDT 24 5058173673 ps
T389 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1234103394 Jul 01 10:40:15 AM PDT 24 Jul 01 10:40:21 AM PDT 24 263588876 ps
T390 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.778744701 Jul 01 10:40:15 AM PDT 24 Jul 01 10:41:24 AM PDT 24 5824087837 ps
T391 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2507466716 Jul 01 10:40:34 AM PDT 24 Jul 01 10:40:39 AM PDT 24 442303563 ps
T392 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2016693527 Jul 01 10:40:26 AM PDT 24 Jul 01 10:41:58 AM PDT 24 32524750582 ps
T393 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3122878199 Jul 01 10:40:27 AM PDT 24 Jul 01 10:41:13 AM PDT 24 27687818222 ps
T394 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1941136195 Jul 01 10:40:20 AM PDT 24 Jul 01 10:41:42 AM PDT 24 30466333938 ps
T395 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4106642486 Jul 01 10:40:13 AM PDT 24 Jul 01 10:41:18 AM PDT 24 197726701761 ps
T396 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.847996682 Jul 01 10:40:22 AM PDT 24 Jul 01 10:41:13 AM PDT 24 21155938133 ps
T397 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1716492951 Jul 01 10:41:05 AM PDT 24 Jul 01 10:41:07 AM PDT 24 102097156 ps
T398 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1739076708 Jul 01 10:40:00 AM PDT 24 Jul 01 10:40:02 AM PDT 24 76198942 ps
T399 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.318288476 Jul 01 10:40:29 AM PDT 24 Jul 01 10:40:35 AM PDT 24 1266248081 ps
T400 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1338579255 Jul 01 10:40:28 AM PDT 24 Jul 01 10:41:26 AM PDT 24 17436400989 ps
T401 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1484478842 Jul 01 10:40:31 AM PDT 24 Jul 01 10:40:33 AM PDT 24 362467425 ps
T402 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1168699232 Jul 01 10:40:23 AM PDT 24 Jul 01 10:40:29 AM PDT 24 306099724 ps
T403 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3114609120 Jul 01 10:41:10 AM PDT 24 Jul 01 10:41:13 AM PDT 24 407903929 ps
T120 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3753828609 Jul 01 10:40:38 AM PDT 24 Jul 01 10:40:41 AM PDT 24 258674998 ps
T122 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4226356656 Jul 01 10:40:20 AM PDT 24 Jul 01 10:40:26 AM PDT 24 186729259 ps
T404 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2548693644 Jul 01 10:40:28 AM PDT 24 Jul 01 10:40:31 AM PDT 24 229032055 ps
T405 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1063952261 Jul 01 10:40:25 AM PDT 24 Jul 01 10:40:31 AM PDT 24 548658212 ps
T406 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2734188246 Jul 01 10:40:26 AM PDT 24 Jul 01 10:40:30 AM PDT 24 468744367 ps
T407 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3776921001 Jul 01 10:40:51 AM PDT 24 Jul 01 10:40:56 AM PDT 24 679864772 ps
T408 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1235464812 Jul 01 10:40:23 AM PDT 24 Jul 01 10:40:30 AM PDT 24 4314657055 ps
T160 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1429346215 Jul 01 10:40:04 AM PDT 24 Jul 01 10:40:24 AM PDT 24 2457093298 ps
T409 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3168476759 Jul 01 10:40:24 AM PDT 24 Jul 01 10:40:58 AM PDT 24 10559843094 ps
T410 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.239944029 Jul 01 10:40:29 AM PDT 24 Jul 01 10:40:36 AM PDT 24 2014902935 ps
T411 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.874584079 Jul 01 10:40:51 AM PDT 24 Jul 01 10:40:54 AM PDT 24 373349268 ps
T412 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.151410331 Jul 01 10:40:23 AM PDT 24 Jul 01 10:40:37 AM PDT 24 18096741990 ps
T413 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.363926001 Jul 01 10:40:34 AM PDT 24 Jul 01 10:40:44 AM PDT 24 337598786 ps
T414 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4114673348 Jul 01 10:40:46 AM PDT 24 Jul 01 10:41:07 AM PDT 24 14342151398 ps
T415 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4122089715 Jul 01 10:40:39 AM PDT 24 Jul 01 10:40:44 AM PDT 24 9536928140 ps
T416 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2860226634 Jul 01 10:39:56 AM PDT 24 Jul 01 10:40:24 AM PDT 24 966181451 ps
T417 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.808053076 Jul 01 10:40:21 AM PDT 24 Jul 01 10:40:27 AM PDT 24 164886284 ps
T418 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3499607175 Jul 01 10:40:38 AM PDT 24 Jul 01 10:40:41 AM PDT 24 116157535 ps
T419 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4212783338 Jul 01 10:39:59 AM PDT 24 Jul 01 10:40:13 AM PDT 24 4412746375 ps
T420 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3575826072 Jul 01 10:40:25 AM PDT 24 Jul 01 10:40:32 AM PDT 24 3484772996 ps
T421 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3314199282 Jul 01 10:40:18 AM PDT 24 Jul 01 10:40:23 AM PDT 24 106545579 ps
T422 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2945622401 Jul 01 10:40:19 AM PDT 24 Jul 01 10:40:29 AM PDT 24 2037372238 ps
T123 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3418072942 Jul 01 10:40:10 AM PDT 24 Jul 01 10:40:13 AM PDT 24 592409514 ps
T124 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.101990221 Jul 01 10:39:56 AM PDT 24 Jul 01 10:41:13 AM PDT 24 3401329923 ps
T423 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.402003439 Jul 01 10:40:20 AM PDT 24 Jul 01 10:40:28 AM PDT 24 93568320 ps
T424 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3093403314 Jul 01 10:40:28 AM PDT 24 Jul 01 10:40:30 AM PDT 24 162030773 ps
T425 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3333911365 Jul 01 10:40:04 AM PDT 24 Jul 01 10:40:34 AM PDT 24 35586979191 ps
T426 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2904330095 Jul 01 10:40:20 AM PDT 24 Jul 01 10:40:30 AM PDT 24 585942189 ps
T427 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3671872078 Jul 01 10:40:52 AM PDT 24 Jul 01 10:40:55 AM PDT 24 1051146350 ps
T428 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1643277245 Jul 01 10:40:36 AM PDT 24 Jul 01 10:40:52 AM PDT 24 11249913369 ps
T429 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2329822466 Jul 01 10:40:18 AM PDT 24 Jul 01 10:40:24 AM PDT 24 7174464949 ps
T430 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3352529305 Jul 01 10:40:17 AM PDT 24 Jul 01 10:40:47 AM PDT 24 9824265374 ps
T431 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3725711823 Jul 01 10:39:59 AM PDT 24 Jul 01 10:40:10 AM PDT 24 5089062133 ps
T432 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1703493084 Jul 01 10:41:06 AM PDT 24 Jul 01 10:41:08 AM PDT 24 129371721 ps
T433 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.625868955 Jul 01 10:40:03 AM PDT 24 Jul 01 10:40:08 AM PDT 24 1263902211 ps
T434 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2186578688 Jul 01 10:40:45 AM PDT 24 Jul 01 10:42:00 AM PDT 24 26674194462 ps
T435 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.378797350 Jul 01 10:40:39 AM PDT 24 Jul 01 10:40:43 AM PDT 24 311925310 ps
T436 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2505519880 Jul 01 10:40:39 AM PDT 24 Jul 01 10:40:47 AM PDT 24 5404246207 ps
T437 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.538854448 Jul 01 10:40:02 AM PDT 24 Jul 01 10:40:05 AM PDT 24 98786514 ps
T438 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1437333810 Jul 01 10:40:22 AM PDT 24 Jul 01 10:40:33 AM PDT 24 2630776656 ps
T439 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.360935475 Jul 01 10:40:05 AM PDT 24 Jul 01 10:40:09 AM PDT 24 278221463 ps
T119 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.53207153 Jul 01 10:40:42 AM PDT 24 Jul 01 10:40:46 AM PDT 24 382199192 ps
T440 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.108422388 Jul 01 10:40:50 AM PDT 24 Jul 01 10:40:55 AM PDT 24 2114613130 ps
T441 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3692623072 Jul 01 10:40:02 AM PDT 24 Jul 01 10:40:07 AM PDT 24 3565136647 ps
T442 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3941387825 Jul 01 10:40:42 AM PDT 24 Jul 01 10:40:44 AM PDT 24 654751899 ps
T443 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1733245555 Jul 01 10:40:43 AM PDT 24 Jul 01 10:41:02 AM PDT 24 12041355818 ps

Test location /workspace/coverage/default/10.rv_dm_stress_all.1698775349
Short name T4
Test name
Test status
Simulation time 3388691921 ps
CPU time 3.61 seconds
Started Jul 01 10:52:13 AM PDT 24
Finished Jul 01 10:52:20 AM PDT 24
Peak memory 213352 kb
Host smart-c628531a-81d0-4c6f-ad8b-e306bd9c971a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698775349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1698775349
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.2169889607
Short name T28
Test name
Test status
Simulation time 39155576378 ps
CPU time 32.11 seconds
Started Jul 01 10:52:37 AM PDT 24
Finished Jul 01 10:53:10 AM PDT 24
Peak memory 213480 kb
Host smart-c90110eb-e429-4f84-a96b-65bbdd0d9348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169889607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2169889607
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3496031245
Short name T83
Test name
Test status
Simulation time 126945455 ps
CPU time 5.56 seconds
Started Jul 01 10:41:04 AM PDT 24
Finished Jul 01 10:41:09 AM PDT 24
Peak memory 213188 kb
Host smart-8a1ab61f-2915-444a-a00d-bb119fae5d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496031245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3496031245
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.1299932555
Short name T8
Test name
Test status
Simulation time 6705785745 ps
CPU time 2.75 seconds
Started Jul 01 10:52:40 AM PDT 24
Finished Jul 01 10:52:46 AM PDT 24
Peak memory 213380 kb
Host smart-8ea1ed7e-bbf2-4e29-aae5-e48cc58ee602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299932555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1299932555
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1443237187
Short name T86
Test name
Test status
Simulation time 8447915761 ps
CPU time 21.87 seconds
Started Jul 01 10:40:56 AM PDT 24
Finished Jul 01 10:41:19 AM PDT 24
Peak memory 213196 kb
Host smart-d7c96c4e-d247-4dbe-b624-f794e1d3c68b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443237187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
443237187
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.641440115
Short name T67
Test name
Test status
Simulation time 40258302133 ps
CPU time 38.91 seconds
Started Jul 01 10:40:39 AM PDT 24
Finished Jul 01 10:41:18 AM PDT 24
Peak memory 218500 kb
Host smart-0be517ec-802a-462f-8a85-c0ce5b68c608
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641440115 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.641440115
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2811487947
Short name T99
Test name
Test status
Simulation time 1104906467 ps
CPU time 66.08 seconds
Started Jul 01 10:40:04 AM PDT 24
Finished Jul 01 10:41:12 AM PDT 24
Peak memory 213088 kb
Host smart-d6211173-99b8-43d7-931a-78a7864e34c9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811487947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2811487947
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1751973560
Short name T76
Test name
Test status
Simulation time 113268235 ps
CPU time 0.99 seconds
Started Jul 01 10:52:38 AM PDT 24
Finished Jul 01 10:52:41 AM PDT 24
Peak memory 204880 kb
Host smart-59bae03e-fb3a-478a-94c2-ce1462d7e0db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751973560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1751973560
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.176687050
Short name T43
Test name
Test status
Simulation time 45129753 ps
CPU time 0.86 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:03 AM PDT 24
Peak memory 215520 kb
Host smart-e751b609-df0b-4135-a845-374d675bf1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176687050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.176687050
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3748722313
Short name T18
Test name
Test status
Simulation time 422784279 ps
CPU time 1.73 seconds
Started Jul 01 10:51:59 AM PDT 24
Finished Jul 01 10:52:01 AM PDT 24
Peak memory 204880 kb
Host smart-338caad5-82e5-45f8-b8db-937be73047ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748722313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3748722313
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.3108276317
Short name T24
Test name
Test status
Simulation time 6720102349 ps
CPU time 18.18 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:53:00 AM PDT 24
Peak memory 213284 kb
Host smart-23b5413d-2a92-4470-b426-f593ef894042
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108276317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3108276317
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2307781167
Short name T38
Test name
Test status
Simulation time 50781865 ps
CPU time 0.86 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:03 AM PDT 24
Peak memory 213136 kb
Host smart-5dd0145a-118e-4208-8f79-74caa0b15d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307781167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2307781167
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.3100208657
Short name T16
Test name
Test status
Simulation time 5874155238 ps
CPU time 16.59 seconds
Started Jul 01 10:52:31 AM PDT 24
Finished Jul 01 10:52:49 AM PDT 24
Peak memory 213368 kb
Host smart-c188e976-acf0-46b2-92c2-df416d6f1296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100208657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.3100208657
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.155211605
Short name T10
Test name
Test status
Simulation time 7642474694 ps
CPU time 4.07 seconds
Started Jul 01 10:52:28 AM PDT 24
Finished Jul 01 10:52:33 AM PDT 24
Peak memory 213468 kb
Host smart-4c3a3f83-348b-466a-bd31-f8d178fae68f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155211605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.155211605
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.792800002
Short name T78
Test name
Test status
Simulation time 1211670900 ps
CPU time 1.9 seconds
Started Jul 01 10:51:59 AM PDT 24
Finished Jul 01 10:52:02 AM PDT 24
Peak memory 236436 kb
Host smart-0b75e363-7d1a-4627-b7d6-868e44a8dc49
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792800002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.792800002
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3618606655
Short name T19
Test name
Test status
Simulation time 5508954102 ps
CPU time 15.44 seconds
Started Jul 01 10:52:01 AM PDT 24
Finished Jul 01 10:52:20 AM PDT 24
Peak memory 205156 kb
Host smart-b8973fe2-16eb-4943-932f-749534b66296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618606655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3618606655
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.242714554
Short name T32
Test name
Test status
Simulation time 21009015036 ps
CPU time 19.33 seconds
Started Jul 01 10:52:21 AM PDT 24
Finished Jul 01 10:52:42 AM PDT 24
Peak memory 213480 kb
Host smart-5512a173-3e99-4e4a-b260-de7cd26ff1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242714554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.242714554
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.2457126870
Short name T57
Test name
Test status
Simulation time 600138190 ps
CPU time 2.32 seconds
Started Jul 01 10:52:04 AM PDT 24
Finished Jul 01 10:52:14 AM PDT 24
Peak memory 204764 kb
Host smart-8b139b3a-9069-4ec5-86ca-7aeb0a1e8bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457126870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2457126870
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1719531775
Short name T161
Test name
Test status
Simulation time 5291162268 ps
CPU time 19.75 seconds
Started Jul 01 10:40:31 AM PDT 24
Finished Jul 01 10:40:52 AM PDT 24
Peak memory 213204 kb
Host smart-f591e8a5-b2ac-48f3-90a7-0d90b3fbc733
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719531775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1719531775
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.304866953
Short name T70
Test name
Test status
Simulation time 3504302740 ps
CPU time 1.91 seconds
Started Jul 01 10:41:00 AM PDT 24
Finished Jul 01 10:41:02 AM PDT 24
Peak memory 204880 kb
Host smart-6b789cdb-a837-44e7-b5b7-40753cd32a97
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304866953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
v_dm_jtag_dmi_csr_bit_bash.304866953
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2072368399
Short name T144
Test name
Test status
Simulation time 3289730403 ps
CPU time 4.85 seconds
Started Jul 01 10:52:24 AM PDT 24
Finished Jul 01 10:52:31 AM PDT 24
Peak memory 213476 kb
Host smart-43736e80-058c-4c82-a413-bf892ed47835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072368399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2072368399
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1679226016
Short name T63
Test name
Test status
Simulation time 946595641 ps
CPU time 1.42 seconds
Started Jul 01 10:52:03 AM PDT 24
Finished Jul 01 10:52:07 AM PDT 24
Peak memory 204860 kb
Host smart-e287f15a-0600-45e7-ac7b-a102e9e384bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679226016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1679226016
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.973621546
Short name T17
Test name
Test status
Simulation time 17234328485 ps
CPU time 14.62 seconds
Started Jul 01 10:52:37 AM PDT 24
Finished Jul 01 10:52:52 AM PDT 24
Peak memory 205068 kb
Host smart-9e2f9893-c63d-488b-9f22-567c6e128b2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973621546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.973621546
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2363768621
Short name T72
Test name
Test status
Simulation time 2625738769 ps
CPU time 10.54 seconds
Started Jul 01 10:41:02 AM PDT 24
Finished Jul 01 10:41:12 AM PDT 24
Peak memory 213240 kb
Host smart-6521d1ee-a00f-4259-a065-950634191090
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363768621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
363768621
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.4015323862
Short name T172
Test name
Test status
Simulation time 11105458827 ps
CPU time 3.68 seconds
Started Jul 01 10:52:32 AM PDT 24
Finished Jul 01 10:52:37 AM PDT 24
Peak memory 213276 kb
Host smart-670b6af6-70f0-460e-891f-5c2f45776c95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015323862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.4015323862
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.601983403
Short name T26
Test name
Test status
Simulation time 3848230446 ps
CPU time 6.46 seconds
Started Jul 01 10:52:44 AM PDT 24
Finished Jul 01 10:52:54 AM PDT 24
Peak memory 213120 kb
Host smart-c08fe4ab-2689-435c-8672-25cf668bc8f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601983403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.601983403
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3503617213
Short name T55
Test name
Test status
Simulation time 1017016189 ps
CPU time 1.5 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:03 AM PDT 24
Peak memory 204844 kb
Host smart-966e5e7b-3588-460a-aad4-d66da2eb1d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503617213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3503617213
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.1616034219
Short name T134
Test name
Test status
Simulation time 17518356986 ps
CPU time 10.52 seconds
Started Jul 01 10:52:29 AM PDT 24
Finished Jul 01 10:52:40 AM PDT 24
Peak memory 213356 kb
Host smart-7c36d1ce-2932-483f-ba81-28bc53246250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616034219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1616034219
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.670306457
Short name T297
Test name
Test status
Simulation time 217035972 ps
CPU time 0.84 seconds
Started Jul 01 10:40:31 AM PDT 24
Finished Jul 01 10:40:33 AM PDT 24
Peak memory 204600 kb
Host smart-4b4236dc-767f-42e3-add2-9bf9553ede5c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670306457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.670306457
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1606492819
Short name T128
Test name
Test status
Simulation time 450238081 ps
CPU time 3.91 seconds
Started Jul 01 10:39:55 AM PDT 24
Finished Jul 01 10:40:00 AM PDT 24
Peak memory 204964 kb
Host smart-7d1e83b6-73ad-43df-b18b-c5de25d5bf98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606492819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1606492819
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2615495513
Short name T107
Test name
Test status
Simulation time 2778618959 ps
CPU time 4.88 seconds
Started Jul 01 10:39:59 AM PDT 24
Finished Jul 01 10:40:05 AM PDT 24
Peak memory 204908 kb
Host smart-1680043c-001b-4704-8f07-877610efb61c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615495513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2615495513
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.392949504
Short name T118
Test name
Test status
Simulation time 2981170473 ps
CPU time 54.73 seconds
Started Jul 01 10:40:23 AM PDT 24
Finished Jul 01 10:41:23 AM PDT 24
Peak memory 213176 kb
Host smart-49e11ad4-3e9c-49c7-8fad-7b6921612503
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392949504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.392949504
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.771778497
Short name T157
Test name
Test status
Simulation time 16573318720 ps
CPU time 49.4 seconds
Started Jul 01 10:40:19 AM PDT 24
Finished Jul 01 10:41:12 AM PDT 24
Peak memory 221360 kb
Host smart-7dec8f88-784b-4009-bb00-3d1d3e0aa5fc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771778497 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.771778497
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.343006760
Short name T159
Test name
Test status
Simulation time 1405473545 ps
CPU time 17.81 seconds
Started Jul 01 10:40:33 AM PDT 24
Finished Jul 01 10:40:53 AM PDT 24
Peak memory 213184 kb
Host smart-0253ce55-a909-4f3f-bddb-5621fc81862a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343006760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.343006760
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.908691652
Short name T154
Test name
Test status
Simulation time 457415776 ps
CPU time 0.76 seconds
Started Jul 01 10:51:59 AM PDT 24
Finished Jul 01 10:52:00 AM PDT 24
Peak memory 204872 kb
Host smart-65b6ed39-ed8d-421b-afd7-d33bee8c5306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908691652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.908691652
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.801509026
Short name T285
Test name
Test status
Simulation time 2345764533 ps
CPU time 7.37 seconds
Started Jul 01 10:51:56 AM PDT 24
Finished Jul 01 10:52:04 AM PDT 24
Peak memory 205192 kb
Host smart-a8b52c7d-488e-4d13-b88c-3855f875a58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801509026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.801509026
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.3071810672
Short name T15
Test name
Test status
Simulation time 2612318893 ps
CPU time 7.25 seconds
Started Jul 01 10:52:37 AM PDT 24
Finished Jul 01 10:52:45 AM PDT 24
Peak memory 213272 kb
Host smart-e46027be-24e7-44d4-8dd1-89747e89ed7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071810672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3071810672
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.101990221
Short name T124
Test name
Test status
Simulation time 3401329923 ps
CPU time 75.54 seconds
Started Jul 01 10:39:56 AM PDT 24
Finished Jul 01 10:41:13 AM PDT 24
Peak memory 213176 kb
Host smart-bbe88ee9-685f-4733-bb2b-2b3b81dafc12
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101990221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.101990221
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1921710339
Short name T104
Test name
Test status
Simulation time 40713760312 ps
CPU time 37.55 seconds
Started Jul 01 10:40:28 AM PDT 24
Finished Jul 01 10:41:07 AM PDT 24
Peak memory 204992 kb
Host smart-94fdf35d-9eb9-4cf7-92ae-344c8fb093b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921710339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1921710339
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2803363083
Short name T365
Test name
Test status
Simulation time 226331425 ps
CPU time 1.63 seconds
Started Jul 01 10:39:57 AM PDT 24
Finished Jul 01 10:40:00 AM PDT 24
Peak memory 213120 kb
Host smart-e5ae8154-c4f8-42d4-8f83-e3df5ac13de9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803363083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2803363083
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3692623072
Short name T441
Test name
Test status
Simulation time 3565136647 ps
CPU time 4.11 seconds
Started Jul 01 10:40:02 AM PDT 24
Finished Jul 01 10:40:07 AM PDT 24
Peak memory 217584 kb
Host smart-9e2f7a97-3828-4cd5-931f-48ea2878b193
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692623072 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3692623072
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.831610223
Short name T111
Test name
Test status
Simulation time 179917874 ps
CPU time 1.85 seconds
Started Jul 01 10:40:35 AM PDT 24
Finished Jul 01 10:40:38 AM PDT 24
Peak memory 213012 kb
Host smart-685fa05e-7ae2-483f-a439-4d4b14c987be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831610223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.831610223
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2654832793
Short name T295
Test name
Test status
Simulation time 92223870673 ps
CPU time 231.6 seconds
Started Jul 01 10:40:15 AM PDT 24
Finished Jul 01 10:44:09 AM PDT 24
Peak memory 204892 kb
Host smart-0f6793d7-a0b8-4af9-8029-c6d7b1b74c92
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654832793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2654832793
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3664983661
Short name T388
Test name
Test status
Simulation time 5058173673 ps
CPU time 14.27 seconds
Started Jul 01 10:40:36 AM PDT 24
Finished Jul 01 10:40:51 AM PDT 24
Peak memory 204820 kb
Host smart-7151e31c-aa02-4d14-b20c-383d6886f41e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664983661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.3664983661
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1235464812
Short name T408
Test name
Test status
Simulation time 4314657055 ps
CPU time 4.52 seconds
Started Jul 01 10:40:23 AM PDT 24
Finished Jul 01 10:40:30 AM PDT 24
Peak memory 204840 kb
Host smart-d4d5bc20-53c5-45ab-8052-bcde71a974dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235464812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1235464812
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3725711823
Short name T431
Test name
Test status
Simulation time 5089062133 ps
CPU time 9.44 seconds
Started Jul 01 10:39:59 AM PDT 24
Finished Jul 01 10:40:10 AM PDT 24
Peak memory 204836 kb
Host smart-02c19c64-0a7e-424f-bf3b-94dfbf09e131
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725711823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
725711823
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.318288476
Short name T399
Test name
Test status
Simulation time 1266248081 ps
CPU time 3.97 seconds
Started Jul 01 10:40:29 AM PDT 24
Finished Jul 01 10:40:35 AM PDT 24
Peak memory 204596 kb
Host smart-ddd2e74e-c2a1-4665-bff0-432278f9faf6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318288476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.318288476
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1864675969
Short name T332
Test name
Test status
Simulation time 4802695290 ps
CPU time 9.53 seconds
Started Jul 01 10:40:02 AM PDT 24
Finished Jul 01 10:40:12 AM PDT 24
Peak memory 204864 kb
Host smart-ebecc854-7c89-4060-8ce9-b17f6f9d844a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864675969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1864675969
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1484478842
Short name T401
Test name
Test status
Simulation time 362467425 ps
CPU time 0.85 seconds
Started Jul 01 10:40:31 AM PDT 24
Finished Jul 01 10:40:33 AM PDT 24
Peak memory 204588 kb
Host smart-a5517c61-6934-4cb4-82b0-5b159f59bb2f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484478842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1484478842
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1642093976
Short name T355
Test name
Test status
Simulation time 143379243 ps
CPU time 0.86 seconds
Started Jul 01 10:40:24 AM PDT 24
Finished Jul 01 10:40:27 AM PDT 24
Peak memory 204716 kb
Host smart-be8fb096-088f-44dc-879a-4aee350eab2a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642093976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
642093976
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1738717770
Short name T385
Test name
Test status
Simulation time 59150700 ps
CPU time 0.75 seconds
Started Jul 01 10:40:18 AM PDT 24
Finished Jul 01 10:40:21 AM PDT 24
Peak memory 204588 kb
Host smart-78ce1724-31f2-46d0-af57-5f993a7c2a56
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738717770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1738717770
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3774052492
Short name T347
Test name
Test status
Simulation time 75481949 ps
CPU time 0.81 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:40:53 AM PDT 24
Peak memory 204572 kb
Host smart-ff402809-ff0f-4737-9fd7-bbf81d7b6b8d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774052492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3774052492
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.538854448
Short name T437
Test name
Test status
Simulation time 98786514 ps
CPU time 1.87 seconds
Started Jul 01 10:40:02 AM PDT 24
Finished Jul 01 10:40:05 AM PDT 24
Peak memory 213208 kb
Host smart-353cbdf9-6f1d-451e-a4de-203460e8db00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538854448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.538854448
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1507386725
Short name T164
Test name
Test status
Simulation time 4258369152 ps
CPU time 17.47 seconds
Started Jul 01 10:40:10 AM PDT 24
Finished Jul 01 10:40:29 AM PDT 24
Peak memory 213224 kb
Host smart-6775a0ad-1596-4e9a-995e-eff14e762da9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507386725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1507386725
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2860226634
Short name T416
Test name
Test status
Simulation time 966181451 ps
CPU time 27.33 seconds
Started Jul 01 10:39:56 AM PDT 24
Finished Jul 01 10:40:24 AM PDT 24
Peak memory 213176 kb
Host smart-f2e33632-2881-461c-bbf9-6bd3dcde57ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860226634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2860226634
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1401747069
Short name T379
Test name
Test status
Simulation time 98687920 ps
CPU time 1.7 seconds
Started Jul 01 10:40:41 AM PDT 24
Finished Jul 01 10:40:49 AM PDT 24
Peak memory 213108 kb
Host smart-d8a99a04-4daf-4731-8ebe-cf904f85b469
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401747069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1401747069
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.360935475
Short name T439
Test name
Test status
Simulation time 278221463 ps
CPU time 2.39 seconds
Started Jul 01 10:40:05 AM PDT 24
Finished Jul 01 10:40:09 AM PDT 24
Peak memory 214896 kb
Host smart-1c2aadf5-e611-4cd1-9bad-8189b45db27e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360935475 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.360935475
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1222755227
Short name T112
Test name
Test status
Simulation time 416809589 ps
CPU time 1.55 seconds
Started Jul 01 10:40:32 AM PDT 24
Finished Jul 01 10:40:35 AM PDT 24
Peak memory 213016 kb
Host smart-34847193-243a-47cb-a5f3-957c3733e54b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222755227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1222755227
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2791825933
Short name T318
Test name
Test status
Simulation time 62753392555 ps
CPU time 37.76 seconds
Started Jul 01 10:40:24 AM PDT 24
Finished Jul 01 10:41:04 AM PDT 24
Peak memory 204896 kb
Host smart-58cbde95-2e16-42c3-bb3b-7291146c7fe0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791825933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2791825933
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.668808919
Short name T308
Test name
Test status
Simulation time 4154227273 ps
CPU time 11.49 seconds
Started Jul 01 10:40:17 AM PDT 24
Finished Jul 01 10:40:32 AM PDT 24
Peak memory 204828 kb
Host smart-72909963-8b38-45d0-9ff9-55809f4f1319
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668808919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r
v_dm_jtag_dmi_csr_bit_bash.668808919
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1311140242
Short name T313
Test name
Test status
Simulation time 5763535939 ps
CPU time 16.44 seconds
Started Jul 01 10:40:11 AM PDT 24
Finished Jul 01 10:40:29 AM PDT 24
Peak memory 204848 kb
Host smart-1a89948b-f92b-4163-b77c-55e83be7461f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311140242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1311140242
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3352529305
Short name T430
Test name
Test status
Simulation time 9824265374 ps
CPU time 27.13 seconds
Started Jul 01 10:40:17 AM PDT 24
Finished Jul 01 10:40:47 AM PDT 24
Peak memory 204824 kb
Host smart-eb2ba928-b217-4e70-9257-edd46658579b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352529305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
352529305
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.25033003
Short name T325
Test name
Test status
Simulation time 574448080 ps
CPU time 0.91 seconds
Started Jul 01 10:40:05 AM PDT 24
Finished Jul 01 10:40:07 AM PDT 24
Peak memory 204568 kb
Host smart-d6260346-8827-4fd4-a254-446084dc9fed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25033003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_
aliasing.25033003
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.151410331
Short name T412
Test name
Test status
Simulation time 18096741990 ps
CPU time 10.82 seconds
Started Jul 01 10:40:23 AM PDT 24
Finished Jul 01 10:40:37 AM PDT 24
Peak memory 204944 kb
Host smart-6cab0b71-f481-4a32-936d-eac4718a770d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151410331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.151410331
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2548693644
Short name T404
Test name
Test status
Simulation time 229032055 ps
CPU time 0.96 seconds
Started Jul 01 10:40:28 AM PDT 24
Finished Jul 01 10:40:31 AM PDT 24
Peak memory 204580 kb
Host smart-7a0fe01b-5945-474c-bf81-5f83dd63d1ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548693644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2548693644
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3093403314
Short name T424
Test name
Test status
Simulation time 162030773 ps
CPU time 0.86 seconds
Started Jul 01 10:40:28 AM PDT 24
Finished Jul 01 10:40:30 AM PDT 24
Peak memory 204584 kb
Host smart-32a79887-ed3f-4868-a056-1d03d143eb6a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093403314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
093403314
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3791164638
Short name T380
Test name
Test status
Simulation time 45710982 ps
CPU time 0.77 seconds
Started Jul 01 10:40:09 AM PDT 24
Finished Jul 01 10:40:12 AM PDT 24
Peak memory 204484 kb
Host smart-0daa6313-5028-44e1-9aeb-871921c6c64a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791164638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3791164638
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3953996156
Short name T298
Test name
Test status
Simulation time 55293200 ps
CPU time 0.67 seconds
Started Jul 01 10:40:29 AM PDT 24
Finished Jul 01 10:40:31 AM PDT 24
Peak memory 204596 kb
Host smart-adf3858b-efce-4ef3-802e-362f1062d428
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953996156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3953996156
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1063952261
Short name T405
Test name
Test status
Simulation time 548658212 ps
CPU time 3.84 seconds
Started Jul 01 10:40:25 AM PDT 24
Finished Jul 01 10:40:31 AM PDT 24
Peak memory 204936 kb
Host smart-c994fa51-022f-45cb-ac30-f19b4174e62b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063952261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1063952261
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.154404550
Short name T387
Test name
Test status
Simulation time 133612046 ps
CPU time 2.52 seconds
Started Jul 01 10:40:19 AM PDT 24
Finished Jul 01 10:40:25 AM PDT 24
Peak memory 213168 kb
Host smart-1bfa6d42-29a0-4593-915b-6684818ffcb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154404550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.154404550
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4212783338
Short name T419
Test name
Test status
Simulation time 4412746375 ps
CPU time 12.27 seconds
Started Jul 01 10:39:59 AM PDT 24
Finished Jul 01 10:40:13 AM PDT 24
Peak memory 213284 kb
Host smart-8af52c5c-cc4a-468c-91e9-f55afdb52305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212783338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.4212783338
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.4249159186
Short name T93
Test name
Test status
Simulation time 1745898377 ps
CPU time 4.65 seconds
Started Jul 01 10:40:15 AM PDT 24
Finished Jul 01 10:40:25 AM PDT 24
Peak memory 220900 kb
Host smart-841191f3-0f78-48b5-a254-63adeb0aebd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249159186 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.4249159186
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2734188246
Short name T406
Test name
Test status
Simulation time 468744367 ps
CPU time 1.64 seconds
Started Jul 01 10:40:26 AM PDT 24
Finished Jul 01 10:40:30 AM PDT 24
Peak memory 213172 kb
Host smart-9e631885-cd42-439d-b6f6-2b5f042c219c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734188246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2734188246
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2162946200
Short name T351
Test name
Test status
Simulation time 4168226308 ps
CPU time 11.36 seconds
Started Jul 01 10:40:23 AM PDT 24
Finished Jul 01 10:40:37 AM PDT 24
Peak memory 204812 kb
Host smart-22299f49-d37f-4245-855f-f876696c10bf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162946200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.2162946200
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1405544616
Short name T334
Test name
Test status
Simulation time 2899615451 ps
CPU time 8.2 seconds
Started Jul 01 10:41:03 AM PDT 24
Finished Jul 01 10:41:12 AM PDT 24
Peak memory 204828 kb
Host smart-c1e201b6-e889-47e8-bf0e-a12b9c4728fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405544616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1405544616
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.239944029
Short name T410
Test name
Test status
Simulation time 2014902935 ps
CPU time 4.3 seconds
Started Jul 01 10:40:29 AM PDT 24
Finished Jul 01 10:40:36 AM PDT 24
Peak memory 204892 kb
Host smart-44cd0581-014f-428b-b39e-4c5f93618762
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239944029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.239944029
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2127028656
Short name T336
Test name
Test status
Simulation time 363567451 ps
CPU time 6.54 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:41:21 AM PDT 24
Peak memory 213140 kb
Host smart-c859f908-e239-4205-802b-834c6e759042
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127028656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2127028656
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2507466716
Short name T391
Test name
Test status
Simulation time 442303563 ps
CPU time 3.89 seconds
Started Jul 01 10:40:34 AM PDT 24
Finished Jul 01 10:40:39 AM PDT 24
Peak memory 221308 kb
Host smart-7b38364f-fe69-4e43-903c-321b690c0136
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507466716 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2507466716
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4226356656
Short name T122
Test name
Test status
Simulation time 186729259 ps
CPU time 2.54 seconds
Started Jul 01 10:40:20 AM PDT 24
Finished Jul 01 10:40:26 AM PDT 24
Peak memory 213120 kb
Host smart-50d97a28-201b-41ee-920f-b7c15a4c5b5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226356656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4226356656
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3168476759
Short name T409
Test name
Test status
Simulation time 10559843094 ps
CPU time 31.41 seconds
Started Jul 01 10:40:24 AM PDT 24
Finished Jul 01 10:40:58 AM PDT 24
Peak memory 204816 kb
Host smart-61c091fa-fd62-47dc-b8b1-6bd189a5e038
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168476759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.3168476759
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1293685389
Short name T294
Test name
Test status
Simulation time 2605030961 ps
CPU time 5.23 seconds
Started Jul 01 10:40:25 AM PDT 24
Finished Jul 01 10:40:32 AM PDT 24
Peak memory 204832 kb
Host smart-de1156a6-46eb-4e88-9986-2e603a8b8b3c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293685389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1293685389
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.956151134
Short name T377
Test name
Test status
Simulation time 127596268 ps
CPU time 0.77 seconds
Started Jul 01 10:40:24 AM PDT 24
Finished Jul 01 10:40:27 AM PDT 24
Peak memory 204600 kb
Host smart-38f33810-926c-4d24-9fbd-e80f9d681ac6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956151134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.956151134
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.751709901
Short name T103
Test name
Test status
Simulation time 1014454189 ps
CPU time 7.79 seconds
Started Jul 01 10:40:33 AM PDT 24
Finished Jul 01 10:40:42 AM PDT 24
Peak memory 205020 kb
Host smart-df1266b3-cdf8-4b98-bfa9-dd19dd6961ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751709901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.751709901
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.4149467924
Short name T367
Test name
Test status
Simulation time 134835361 ps
CPU time 2.75 seconds
Started Jul 01 10:40:53 AM PDT 24
Finished Jul 01 10:40:57 AM PDT 24
Peak memory 213164 kb
Host smart-58089260-5188-4c33-a523-319d2675bac4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149467924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.4149467924
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2442860338
Short name T91
Test name
Test status
Simulation time 3163661397 ps
CPU time 25.01 seconds
Started Jul 01 10:40:24 AM PDT 24
Finished Jul 01 10:40:51 AM PDT 24
Peak memory 213212 kb
Host smart-3f528dec-6dfd-4184-8ba0-160e8edc1025
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442860338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
442860338
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2505519880
Short name T436
Test name
Test status
Simulation time 5404246207 ps
CPU time 2.64 seconds
Started Jul 01 10:40:39 AM PDT 24
Finished Jul 01 10:40:47 AM PDT 24
Peak memory 215664 kb
Host smart-1616830e-3223-4f9d-8682-79687eb8fbb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505519880 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2505519880
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.356139746
Short name T329
Test name
Test status
Simulation time 462626344 ps
CPU time 2.38 seconds
Started Jul 01 10:41:12 AM PDT 24
Finished Jul 01 10:41:15 AM PDT 24
Peak memory 213188 kb
Host smart-93274fd4-f5ab-498c-a570-b6b8b1fe76b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356139746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.356139746
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2920134803
Short name T350
Test name
Test status
Simulation time 18378638051 ps
CPU time 31.58 seconds
Started Jul 01 10:40:32 AM PDT 24
Finished Jul 01 10:41:05 AM PDT 24
Peak memory 204808 kb
Host smart-fa3ab8dd-f044-4530-8cf7-1d9f760d75c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920134803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.2920134803
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2796816355
Short name T319
Test name
Test status
Simulation time 2078433509 ps
CPU time 3.52 seconds
Started Jul 01 10:40:58 AM PDT 24
Finished Jul 01 10:41:02 AM PDT 24
Peak memory 205060 kb
Host smart-c0785613-32c5-49c3-a850-f8613b2764f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796816355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2796816355
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3941387825
Short name T442
Test name
Test status
Simulation time 654751899 ps
CPU time 1.2 seconds
Started Jul 01 10:40:42 AM PDT 24
Finished Jul 01 10:40:44 AM PDT 24
Peak memory 204596 kb
Host smart-5aff9f28-58bd-4f33-80b7-2fb81e3296be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941387825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3941387825
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3140016693
Short name T362
Test name
Test status
Simulation time 384464328 ps
CPU time 6.56 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:40:59 AM PDT 24
Peak memory 204960 kb
Host smart-cdc6a151-8c1f-4178-8731-018693defd9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140016693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3140016693
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.846173461
Short name T337
Test name
Test status
Simulation time 192434406 ps
CPU time 3.94 seconds
Started Jul 01 10:40:40 AM PDT 24
Finished Jul 01 10:40:44 AM PDT 24
Peak memory 213240 kb
Host smart-a342c911-ab99-4503-9fde-95bdc6ebe55b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846173461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.846173461
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2614306757
Short name T373
Test name
Test status
Simulation time 2432724858 ps
CPU time 8.36 seconds
Started Jul 01 10:40:43 AM PDT 24
Finished Jul 01 10:40:53 AM PDT 24
Peak memory 213200 kb
Host smart-5d302e83-6a95-4d7c-81b4-ecf55bc103b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614306757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
614306757
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3776921001
Short name T407
Test name
Test status
Simulation time 679864772 ps
CPU time 3.66 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:40:56 AM PDT 24
Peak memory 218912 kb
Host smart-dd8dce86-3f88-4dcb-a0f8-510f4dbd5085
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776921001 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3776921001
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1419453731
Short name T353
Test name
Test status
Simulation time 244480337 ps
CPU time 1.6 seconds
Started Jul 01 10:40:20 AM PDT 24
Finished Jul 01 10:40:25 AM PDT 24
Peak memory 213012 kb
Host smart-a28b395e-d701-4b50-831b-d207f96a7c6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419453731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1419453731
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2484533624
Short name T331
Test name
Test status
Simulation time 153282463 ps
CPU time 0.79 seconds
Started Jul 01 10:40:26 AM PDT 24
Finished Jul 01 10:40:29 AM PDT 24
Peak memory 204600 kb
Host smart-11224fab-4664-46b4-82e4-ce59c6d4a4ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484533624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2484533624
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1931566944
Short name T292
Test name
Test status
Simulation time 2034825073 ps
CPU time 2.73 seconds
Started Jul 01 10:41:05 AM PDT 24
Finished Jul 01 10:41:08 AM PDT 24
Peak memory 204776 kb
Host smart-4d1b95b6-f2b7-4839-a53b-0174dca44a3c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931566944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1931566944
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.595865466
Short name T307
Test name
Test status
Simulation time 115840678 ps
CPU time 0.76 seconds
Started Jul 01 10:40:31 AM PDT 24
Finished Jul 01 10:40:33 AM PDT 24
Peak memory 204596 kb
Host smart-2ec5b151-7cc3-4b29-9108-a821e9d6d82b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595865466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.595865466
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3777026480
Short name T382
Test name
Test status
Simulation time 569365908 ps
CPU time 4.24 seconds
Started Jul 01 10:40:41 AM PDT 24
Finished Jul 01 10:40:45 AM PDT 24
Peak memory 204968 kb
Host smart-1c8fad97-d7c7-493d-b49b-27580bb332bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777026480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3777026480
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3130634174
Short name T105
Test name
Test status
Simulation time 377576690 ps
CPU time 2.75 seconds
Started Jul 01 10:40:35 AM PDT 24
Finished Jul 01 10:40:38 AM PDT 24
Peak memory 221324 kb
Host smart-9c5baa80-41b2-419f-80ce-f53eb80c2d0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130634174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3130634174
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.726383044
Short name T74
Test name
Test status
Simulation time 2379815513 ps
CPU time 9.39 seconds
Started Jul 01 10:40:57 AM PDT 24
Finished Jul 01 10:41:07 AM PDT 24
Peak memory 213292 kb
Host smart-5ff66b92-4857-47e3-a191-e815a0044337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726383044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.726383044
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3114609120
Short name T403
Test name
Test status
Simulation time 407903929 ps
CPU time 2.43 seconds
Started Jul 01 10:41:10 AM PDT 24
Finished Jul 01 10:41:13 AM PDT 24
Peak memory 217128 kb
Host smart-cb73dc05-55b6-4a3e-9808-977462dc0ce7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114609120 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3114609120
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1703493084
Short name T432
Test name
Test status
Simulation time 129371721 ps
CPU time 1.51 seconds
Started Jul 01 10:41:06 AM PDT 24
Finished Jul 01 10:41:08 AM PDT 24
Peak memory 213036 kb
Host smart-eba6b1f2-46c2-4f2c-b1ae-1fde5411c39c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703493084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1703493084
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1733245555
Short name T443
Test name
Test status
Simulation time 12041355818 ps
CPU time 18.39 seconds
Started Jul 01 10:40:43 AM PDT 24
Finished Jul 01 10:41:02 AM PDT 24
Peak memory 204816 kb
Host smart-ca185fee-10f2-4197-9246-4ecec637c120
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733245555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.1733245555
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3821445813
Short name T372
Test name
Test status
Simulation time 2009948918 ps
CPU time 3.71 seconds
Started Jul 01 10:40:33 AM PDT 24
Finished Jul 01 10:40:38 AM PDT 24
Peak memory 204744 kb
Host smart-c64e4ccf-fb82-44a9-a02d-73fb25a73aea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821445813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3821445813
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.324851099
Short name T354
Test name
Test status
Simulation time 161070770 ps
CPU time 0.85 seconds
Started Jul 01 10:40:31 AM PDT 24
Finished Jul 01 10:40:33 AM PDT 24
Peak memory 204536 kb
Host smart-2a2bd030-11c2-4291-8787-354ecfa559e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324851099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.324851099
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2904330095
Short name T426
Test name
Test status
Simulation time 585942189 ps
CPU time 6.97 seconds
Started Jul 01 10:40:20 AM PDT 24
Finished Jul 01 10:40:30 AM PDT 24
Peak memory 204956 kb
Host smart-0b5d7fb9-d937-44ce-b9c3-490a33a38a6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904330095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2904330095
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1338727574
Short name T106
Test name
Test status
Simulation time 177140086 ps
CPU time 3.28 seconds
Started Jul 01 10:40:40 AM PDT 24
Finished Jul 01 10:40:44 AM PDT 24
Peak memory 213164 kb
Host smart-ba940cec-6b5f-40c9-813a-d16fee551c07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338727574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1338727574
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.108422388
Short name T440
Test name
Test status
Simulation time 2114613130 ps
CPU time 3.09 seconds
Started Jul 01 10:40:50 AM PDT 24
Finished Jul 01 10:40:55 AM PDT 24
Peak memory 215556 kb
Host smart-52274fba-0221-46ed-a908-fc3c0b7ee622
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108422388 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.108422388
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.53207153
Short name T119
Test name
Test status
Simulation time 382199192 ps
CPU time 2.31 seconds
Started Jul 01 10:40:42 AM PDT 24
Finished Jul 01 10:40:46 AM PDT 24
Peak memory 213048 kb
Host smart-6b817980-d60a-4c3d-ae85-cf198a562411
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53207153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.53207153
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2186578688
Short name T434
Test name
Test status
Simulation time 26674194462 ps
CPU time 73.14 seconds
Started Jul 01 10:40:45 AM PDT 24
Finished Jul 01 10:42:00 AM PDT 24
Peak memory 204848 kb
Host smart-d509ec52-f9e1-4b0b-ade7-e3d89d498ac4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186578688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.2186578688
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1122953943
Short name T357
Test name
Test status
Simulation time 2978308441 ps
CPU time 4.51 seconds
Started Jul 01 10:40:26 AM PDT 24
Finished Jul 01 10:40:32 AM PDT 24
Peak memory 204772 kb
Host smart-d7a3df5e-b9aa-40f2-bd97-84cb8720bd74
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122953943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1122953943
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2903475171
Short name T349
Test name
Test status
Simulation time 158636965 ps
CPU time 0.82 seconds
Started Jul 01 10:40:32 AM PDT 24
Finished Jul 01 10:40:35 AM PDT 24
Peak memory 204588 kb
Host smart-e6b229b5-b6e2-4c30-b87f-63d57904f065
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903475171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2903475171
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.142625544
Short name T127
Test name
Test status
Simulation time 637348496 ps
CPU time 6.4 seconds
Started Jul 01 10:41:03 AM PDT 24
Finished Jul 01 10:41:09 AM PDT 24
Peak memory 205008 kb
Host smart-112f5440-cedd-4df8-8543-c4d2ab24c1f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142625544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_
csr_outstanding.142625544
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4279843998
Short name T323
Test name
Test status
Simulation time 83210748 ps
CPU time 1.86 seconds
Started Jul 01 10:40:42 AM PDT 24
Finished Jul 01 10:40:45 AM PDT 24
Peak memory 213108 kb
Host smart-bd723437-e9eb-4d9d-bb60-82d3dda37c62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279843998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.4279843998
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3370867537
Short name T73
Test name
Test status
Simulation time 4508068649 ps
CPU time 24.81 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:41:17 AM PDT 24
Peak memory 213396 kb
Host smart-a96437ff-3397-4fda-bb01-ac287a625692
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370867537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
370867537
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4100765202
Short name T327
Test name
Test status
Simulation time 133597388 ps
CPU time 2.28 seconds
Started Jul 01 10:40:45 AM PDT 24
Finished Jul 01 10:40:48 AM PDT 24
Peak memory 217304 kb
Host smart-596ec52a-4683-4493-b82f-1cad4fce80db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100765202 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.4100765202
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3753828609
Short name T120
Test name
Test status
Simulation time 258674998 ps
CPU time 2.42 seconds
Started Jul 01 10:40:38 AM PDT 24
Finished Jul 01 10:40:41 AM PDT 24
Peak memory 213076 kb
Host smart-aa54d25a-bad2-4977-95cd-5b3d1ef3794b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753828609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3753828609
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4122089715
Short name T415
Test name
Test status
Simulation time 9536928140 ps
CPU time 3.95 seconds
Started Jul 01 10:40:39 AM PDT 24
Finished Jul 01 10:40:44 AM PDT 24
Peak memory 204828 kb
Host smart-02965807-324a-4004-a117-447cbf8b4a65
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122089715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.4122089715
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.725855306
Short name T370
Test name
Test status
Simulation time 2366645607 ps
CPU time 7.05 seconds
Started Jul 01 10:40:30 AM PDT 24
Finished Jul 01 10:40:39 AM PDT 24
Peak memory 204800 kb
Host smart-0b6e1e43-4a0f-4b9e-8367-cd0518e00ee9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725855306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.725855306
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1142474869
Short name T342
Test name
Test status
Simulation time 821443547 ps
CPU time 1.31 seconds
Started Jul 01 10:41:05 AM PDT 24
Finished Jul 01 10:41:07 AM PDT 24
Peak memory 204600 kb
Host smart-d60163e9-4192-4d7a-8304-c2f47274c65a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142474869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1142474869
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.4064382863
Short name T100
Test name
Test status
Simulation time 235527425 ps
CPU time 6.35 seconds
Started Jul 01 10:40:36 AM PDT 24
Finished Jul 01 10:40:43 AM PDT 24
Peak memory 204988 kb
Host smart-ca8316b8-ece6-4406-8612-ebfacf310cf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064382863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.4064382863
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.84060150
Short name T328
Test name
Test status
Simulation time 367734720 ps
CPU time 2.09 seconds
Started Jul 01 10:41:07 AM PDT 24
Finished Jul 01 10:41:09 AM PDT 24
Peak memory 213172 kb
Host smart-7e52638d-30eb-43d3-a68c-80900907cc18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84060150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.84060150
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.963085704
Short name T84
Test name
Test status
Simulation time 1340561214 ps
CPU time 10.35 seconds
Started Jul 01 10:40:34 AM PDT 24
Finished Jul 01 10:40:46 AM PDT 24
Peak memory 213156 kb
Host smart-c78d1153-584b-4d44-b037-e810100ac4c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963085704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.963085704
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.505989424
Short name T360
Test name
Test status
Simulation time 738789255 ps
CPU time 3.88 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:41:18 AM PDT 24
Peak memory 221200 kb
Host smart-13bdc63a-cbe0-4a08-9f1b-c78d421e3302
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505989424 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.505989424
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3746013340
Short name T117
Test name
Test status
Simulation time 319499079 ps
CPU time 2.13 seconds
Started Jul 01 10:40:33 AM PDT 24
Finished Jul 01 10:40:37 AM PDT 24
Peak memory 213120 kb
Host smart-d359812f-15e6-4e9e-99ef-3e663c904559
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746013340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3746013340
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.847996682
Short name T396
Test name
Test status
Simulation time 21155938133 ps
CPU time 47.41 seconds
Started Jul 01 10:40:22 AM PDT 24
Finished Jul 01 10:41:13 AM PDT 24
Peak memory 204844 kb
Host smart-2ec2b88a-4325-4d1d-a31b-a68aa901427e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847996682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.847996682
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3671872078
Short name T427
Test name
Test status
Simulation time 1051146350 ps
CPU time 1.65 seconds
Started Jul 01 10:40:52 AM PDT 24
Finished Jul 01 10:40:55 AM PDT 24
Peak memory 204776 kb
Host smart-847a112c-7848-4b1d-9b80-eccc4615508c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671872078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3671872078
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3458288900
Short name T364
Test name
Test status
Simulation time 402804350 ps
CPU time 1.65 seconds
Started Jul 01 10:41:07 AM PDT 24
Finished Jul 01 10:41:10 AM PDT 24
Peak memory 204596 kb
Host smart-5e454006-f7dd-4857-a632-a4b6a25194d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458288900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3458288900
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3412679302
Short name T115
Test name
Test status
Simulation time 292589393 ps
CPU time 4.18 seconds
Started Jul 01 10:40:21 AM PDT 24
Finished Jul 01 10:40:29 AM PDT 24
Peak memory 204904 kb
Host smart-92243d73-4773-4958-8a41-d50f40013efc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412679302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3412679302
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1118513890
Short name T335
Test name
Test status
Simulation time 1168955854 ps
CPU time 4.8 seconds
Started Jul 01 10:41:11 AM PDT 24
Finished Jul 01 10:41:16 AM PDT 24
Peak memory 213184 kb
Host smart-0e600faa-9ff1-4765-a772-2acd1683a8bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118513890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1118513890
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3989259996
Short name T338
Test name
Test status
Simulation time 809035339 ps
CPU time 4.15 seconds
Started Jul 01 10:40:31 AM PDT 24
Finished Jul 01 10:40:36 AM PDT 24
Peak memory 219768 kb
Host smart-d8558e25-b723-430d-a758-930bf14b3695
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989259996 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3989259996
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2428619966
Short name T98
Test name
Test status
Simulation time 165623427 ps
CPU time 1.9 seconds
Started Jul 01 10:40:33 AM PDT 24
Finished Jul 01 10:40:37 AM PDT 24
Peak memory 212984 kb
Host smart-da8a20ef-4db0-49bf-b67d-32f5e6259a55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428619966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2428619966
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1508234159
Short name T303
Test name
Test status
Simulation time 14081376309 ps
CPU time 9.5 seconds
Started Jul 01 10:40:37 AM PDT 24
Finished Jul 01 10:40:47 AM PDT 24
Peak memory 204820 kb
Host smart-aee8fbe6-a36d-4673-b778-74a300d63652
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508234159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.1508234159
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1643277245
Short name T428
Test name
Test status
Simulation time 11249913369 ps
CPU time 15 seconds
Started Jul 01 10:40:36 AM PDT 24
Finished Jul 01 10:40:52 AM PDT 24
Peak memory 204840 kb
Host smart-a4a80d71-ae47-4456-9c6a-0ced65f65fe9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643277245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1643277245
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2927642634
Short name T304
Test name
Test status
Simulation time 414127546 ps
CPU time 0.86 seconds
Started Jul 01 10:40:24 AM PDT 24
Finished Jul 01 10:40:27 AM PDT 24
Peak memory 204596 kb
Host smart-5aba743a-55ad-4faf-a330-59f925cf3696
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927642634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2927642634
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2467752626
Short name T116
Test name
Test status
Simulation time 923764237 ps
CPU time 4.22 seconds
Started Jul 01 10:41:11 AM PDT 24
Finished Jul 01 10:41:16 AM PDT 24
Peak memory 205028 kb
Host smart-161fbfa8-b817-4a2f-b2e7-3f93b2bfcd2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467752626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2467752626
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3738944522
Short name T162
Test name
Test status
Simulation time 3294633248 ps
CPU time 12.26 seconds
Started Jul 01 10:41:04 AM PDT 24
Finished Jul 01 10:41:16 AM PDT 24
Peak memory 213260 kb
Host smart-a7d59517-ad8e-4e6d-985d-c7763e5d92d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738944522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
738944522
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2941560368
Short name T85
Test name
Test status
Simulation time 1106769592 ps
CPU time 3.21 seconds
Started Jul 01 10:40:32 AM PDT 24
Finished Jul 01 10:40:37 AM PDT 24
Peak memory 219448 kb
Host smart-e155e250-1658-41af-9491-35456c553c98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941560368 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2941560368
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2772311807
Short name T101
Test name
Test status
Simulation time 90950929 ps
CPU time 1.61 seconds
Started Jul 01 10:40:41 AM PDT 24
Finished Jul 01 10:40:43 AM PDT 24
Peak memory 213096 kb
Host smart-98bcf8be-b246-4d0d-b3dd-c1c160992b7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772311807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2772311807
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3170632492
Short name T339
Test name
Test status
Simulation time 31968145306 ps
CPU time 46.48 seconds
Started Jul 01 10:40:43 AM PDT 24
Finished Jul 01 10:41:31 AM PDT 24
Peak memory 204824 kb
Host smart-d8504cea-351f-48c3-9089-243b8d1a5d71
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170632492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.3170632492
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4114673348
Short name T414
Test name
Test status
Simulation time 14342151398 ps
CPU time 19.77 seconds
Started Jul 01 10:40:46 AM PDT 24
Finished Jul 01 10:41:07 AM PDT 24
Peak memory 204832 kb
Host smart-5239b1f2-61a7-465f-9a92-0dec7f65e20e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114673348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
4114673348
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.874584079
Short name T411
Test name
Test status
Simulation time 373349268 ps
CPU time 1.44 seconds
Started Jul 01 10:40:51 AM PDT 24
Finished Jul 01 10:40:54 AM PDT 24
Peak memory 204596 kb
Host smart-949fe942-ac69-4c67-836b-717479fb4a3d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874584079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.874584079
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.363926001
Short name T413
Test name
Test status
Simulation time 337598786 ps
CPU time 3.94 seconds
Started Jul 01 10:40:34 AM PDT 24
Finished Jul 01 10:40:44 AM PDT 24
Peak memory 204904 kb
Host smart-6b4565cc-7619-4bd7-9f9b-3b1d4ed0f71a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363926001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.363926001
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3499607175
Short name T418
Test name
Test status
Simulation time 116157535 ps
CPU time 2.91 seconds
Started Jul 01 10:40:38 AM PDT 24
Finished Jul 01 10:40:41 AM PDT 24
Peak memory 213136 kb
Host smart-99374668-a2e2-4ddd-93de-12cfd4ce43d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499607175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3499607175
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.618136258
Short name T368
Test name
Test status
Simulation time 2277410776 ps
CPU time 8.93 seconds
Started Jul 01 10:40:42 AM PDT 24
Finished Jul 01 10:40:57 AM PDT 24
Peak memory 213252 kb
Host smart-f2ad70a6-6da9-4f95-ae2a-c8ad241ec8e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618136258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.618136258
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1400177521
Short name T121
Test name
Test status
Simulation time 10185702984 ps
CPU time 72.94 seconds
Started Jul 01 10:40:00 AM PDT 24
Finished Jul 01 10:41:14 AM PDT 24
Peak memory 213180 kb
Host smart-d86baaae-4e02-4995-bef6-f4bf9a5baa82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400177521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1400177521
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3418072942
Short name T123
Test name
Test status
Simulation time 592409514 ps
CPU time 1.71 seconds
Started Jul 01 10:40:10 AM PDT 24
Finished Jul 01 10:40:13 AM PDT 24
Peak memory 213028 kb
Host smart-4ddf21ec-395e-4171-87a6-aabe3cd1fe27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418072942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3418072942
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2876791398
Short name T92
Test name
Test status
Simulation time 3815666776 ps
CPU time 5.67 seconds
Started Jul 01 10:40:24 AM PDT 24
Finished Jul 01 10:40:34 AM PDT 24
Peak memory 220472 kb
Host smart-4b7759d2-4d12-464c-859e-fd47b975c935
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876791398 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2876791398
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.4238282511
Short name T369
Test name
Test status
Simulation time 151492267 ps
CPU time 1.56 seconds
Started Jul 01 10:40:10 AM PDT 24
Finished Jul 01 10:40:13 AM PDT 24
Peak memory 213000 kb
Host smart-8d17a3e8-523b-4dd1-834b-44c31736ce19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238282511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.4238282511
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4106642486
Short name T395
Test name
Test status
Simulation time 197726701761 ps
CPU time 62.1 seconds
Started Jul 01 10:40:13 AM PDT 24
Finished Jul 01 10:41:18 AM PDT 24
Peak memory 209260 kb
Host smart-ddc0ef48-b8f4-42d9-9bcc-85657bc491aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106642486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.4106642486
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1380426968
Short name T291
Test name
Test status
Simulation time 16473866704 ps
CPU time 13.44 seconds
Started Jul 01 10:40:14 AM PDT 24
Finished Jul 01 10:40:34 AM PDT 24
Peak memory 204808 kb
Host smart-c94ac387-44cf-4682-b7d2-838b548b24f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380426968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1380426968
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1437333810
Short name T438
Test name
Test status
Simulation time 2630776656 ps
CPU time 7.81 seconds
Started Jul 01 10:40:22 AM PDT 24
Finished Jul 01 10:40:33 AM PDT 24
Peak memory 204836 kb
Host smart-599e2ee8-838f-453e-8b33-a112bad8be6c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437333810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
437333810
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.4172828088
Short name T317
Test name
Test status
Simulation time 832487120 ps
CPU time 1.74 seconds
Started Jul 01 10:40:23 AM PDT 24
Finished Jul 01 10:40:28 AM PDT 24
Peak memory 204596 kb
Host smart-4ae62238-b8da-4ea5-a8ec-66c9bd273f4f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172828088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.4172828088
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1941136195
Short name T394
Test name
Test status
Simulation time 30466333938 ps
CPU time 78.36 seconds
Started Jul 01 10:40:20 AM PDT 24
Finished Jul 01 10:41:42 AM PDT 24
Peak memory 204896 kb
Host smart-2668d6f2-1925-4eb4-b160-923515ca9ede
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941136195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1941136195
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1159255567
Short name T363
Test name
Test status
Simulation time 160042142 ps
CPU time 0.74 seconds
Started Jul 01 10:40:03 AM PDT 24
Finished Jul 01 10:40:05 AM PDT 24
Peak memory 204596 kb
Host smart-c977632a-bd0c-49b8-92ee-9dda6e37fca5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159255567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1159255567
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.209399579
Short name T80
Test name
Test status
Simulation time 1310815017 ps
CPU time 1.6 seconds
Started Jul 01 10:40:26 AM PDT 24
Finished Jul 01 10:40:29 AM PDT 24
Peak memory 204592 kb
Host smart-5581d343-c64e-40f8-867c-2feeb668cfe9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209399579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.209399579
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1739076708
Short name T398
Test name
Test status
Simulation time 76198942 ps
CPU time 0.79 seconds
Started Jul 01 10:40:00 AM PDT 24
Finished Jul 01 10:40:02 AM PDT 24
Peak memory 204588 kb
Host smart-0e0722c7-311e-4032-900f-4d24eaa130b2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739076708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1739076708
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.657908160
Short name T302
Test name
Test status
Simulation time 171513827 ps
CPU time 0.89 seconds
Started Jul 01 10:40:20 AM PDT 24
Finished Jul 01 10:40:24 AM PDT 24
Peak memory 204600 kb
Host smart-59b96059-c540-4e56-8609-d29995e1edb8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657908160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.657908160
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2458622684
Short name T75
Test name
Test status
Simulation time 173221441 ps
CPU time 4 seconds
Started Jul 01 10:40:13 AM PDT 24
Finished Jul 01 10:40:19 AM PDT 24
Peak memory 205000 kb
Host smart-1901674e-ab07-4107-9b0e-be85fc46e757
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458622684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2458622684
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2458666614
Short name T333
Test name
Test status
Simulation time 105607979 ps
CPU time 2.95 seconds
Started Jul 01 10:40:19 AM PDT 24
Finished Jul 01 10:40:26 AM PDT 24
Peak memory 213176 kb
Host smart-f721c431-bb11-42a9-8cdd-236829a65af0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458666614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2458666614
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2992739797
Short name T326
Test name
Test status
Simulation time 767664764 ps
CPU time 8.24 seconds
Started Jul 01 10:40:15 AM PDT 24
Finished Jul 01 10:40:25 AM PDT 24
Peak memory 213136 kb
Host smart-66e6a8c1-adf7-4336-af3e-d9b1a6fd6a1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992739797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2992739797
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1363403960
Short name T113
Test name
Test status
Simulation time 2218538914 ps
CPU time 28.2 seconds
Started Jul 01 10:40:20 AM PDT 24
Finished Jul 01 10:40:52 AM PDT 24
Peak memory 204872 kb
Host smart-37a5e323-0b49-4a97-a5f4-58923eb141f8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363403960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1363403960
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1651382915
Short name T110
Test name
Test status
Simulation time 3200677055 ps
CPU time 36.15 seconds
Started Jul 01 10:40:19 AM PDT 24
Finished Jul 01 10:40:59 AM PDT 24
Peak memory 213216 kb
Host smart-f8fce8a2-191e-4474-b5c0-2a88accfc453
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651382915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1651382915
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3522947098
Short name T114
Test name
Test status
Simulation time 134021317 ps
CPU time 2.37 seconds
Started Jul 01 10:40:25 AM PDT 24
Finished Jul 01 10:40:30 AM PDT 24
Peak memory 214108 kb
Host smart-24062eaf-1c4c-4269-8473-5acd822f2926
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522947098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3522947098
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.625868955
Short name T433
Test name
Test status
Simulation time 1263902211 ps
CPU time 3.87 seconds
Started Jul 01 10:40:03 AM PDT 24
Finished Jul 01 10:40:08 AM PDT 24
Peak memory 221200 kb
Host smart-cf180122-d088-47ff-831c-d5f1d9d9750a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625868955 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.625868955
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2795355009
Short name T381
Test name
Test status
Simulation time 210699498 ps
CPU time 2.65 seconds
Started Jul 01 10:40:11 AM PDT 24
Finished Jul 01 10:40:15 AM PDT 24
Peak memory 213148 kb
Host smart-29205293-b07f-41da-a35d-856d31d31f6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795355009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2795355009
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2787143420
Short name T348
Test name
Test status
Simulation time 20835737475 ps
CPU time 16.97 seconds
Started Jul 01 10:40:21 AM PDT 24
Finished Jul 01 10:40:41 AM PDT 24
Peak memory 204904 kb
Host smart-3825778a-a821-47f2-9f92-3af0c3933b8a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787143420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2787143420
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2899747808
Short name T344
Test name
Test status
Simulation time 4962669376 ps
CPU time 8.89 seconds
Started Jul 01 10:40:11 AM PDT 24
Finished Jul 01 10:40:22 AM PDT 24
Peak memory 204824 kb
Host smart-bac084d7-67df-4761-8641-3681c755715a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899747808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.2899747808
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.739444502
Short name T320
Test name
Test status
Simulation time 2952664924 ps
CPU time 6.2 seconds
Started Jul 01 10:40:00 AM PDT 24
Finished Jul 01 10:40:07 AM PDT 24
Peak memory 204844 kb
Host smart-074b74de-7e87-4202-9f93-cd7928ff83f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739444502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.739444502
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3510013835
Short name T306
Test name
Test status
Simulation time 3803556239 ps
CPU time 3.42 seconds
Started Jul 01 10:40:09 AM PDT 24
Finished Jul 01 10:40:15 AM PDT 24
Peak memory 204840 kb
Host smart-048d7ee1-06b6-44fa-b0bf-89c57b11919d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510013835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
510013835
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2223244379
Short name T296
Test name
Test status
Simulation time 768945680 ps
CPU time 1.59 seconds
Started Jul 01 10:40:11 AM PDT 24
Finished Jul 01 10:40:15 AM PDT 24
Peak memory 204572 kb
Host smart-bebc2244-0ea2-4a2a-8f9b-0cc63caed6e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223244379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2223244379
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3054279000
Short name T378
Test name
Test status
Simulation time 12764417760 ps
CPU time 12.32 seconds
Started Jul 01 10:40:14 AM PDT 24
Finished Jul 01 10:40:28 AM PDT 24
Peak memory 204844 kb
Host smart-6a2ce789-a016-4b64-9b60-afdb00bb0bf6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054279000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3054279000
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.259595163
Short name T299
Test name
Test status
Simulation time 109948365 ps
CPU time 1 seconds
Started Jul 01 10:40:05 AM PDT 24
Finished Jul 01 10:40:07 AM PDT 24
Peak memory 204592 kb
Host smart-3e646714-c498-4b62-ab7c-c05631452da7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259595163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.259595163
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2182778849
Short name T346
Test name
Test status
Simulation time 290386854 ps
CPU time 1.37 seconds
Started Jul 01 10:40:18 AM PDT 24
Finished Jul 01 10:40:23 AM PDT 24
Peak memory 204596 kb
Host smart-08c04509-ec30-4061-8ac0-1885a9b9d4c4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182778849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
182778849
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3295898386
Short name T324
Test name
Test status
Simulation time 48327271 ps
CPU time 0.78 seconds
Started Jul 01 10:40:29 AM PDT 24
Finished Jul 01 10:40:32 AM PDT 24
Peak memory 204588 kb
Host smart-706ce79e-9188-4a22-adc7-e0631fd9ec2f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295898386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3295898386
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2686626126
Short name T386
Test name
Test status
Simulation time 79473835 ps
CPU time 0.72 seconds
Started Jul 01 10:40:31 AM PDT 24
Finished Jul 01 10:40:33 AM PDT 24
Peak memory 204600 kb
Host smart-a70856fc-a8ec-4957-b1e5-dd7eb39bf606
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686626126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2686626126
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.402003439
Short name T423
Test name
Test status
Simulation time 93568320 ps
CPU time 3.59 seconds
Started Jul 01 10:40:20 AM PDT 24
Finished Jul 01 10:40:28 AM PDT 24
Peak memory 204936 kb
Host smart-fef7dc65-076f-4047-b71a-c45c1cb04a90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402003439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.402003439
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3334744819
Short name T340
Test name
Test status
Simulation time 286334419 ps
CPU time 2.62 seconds
Started Jul 01 10:40:30 AM PDT 24
Finished Jul 01 10:40:34 AM PDT 24
Peak memory 213168 kb
Host smart-d66c50dd-40f7-464e-8a41-6d25403c8604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334744819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3334744819
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1429346215
Short name T160
Test name
Test status
Simulation time 2457093298 ps
CPU time 18.87 seconds
Started Jul 01 10:40:04 AM PDT 24
Finished Jul 01 10:40:24 AM PDT 24
Peak memory 213232 kb
Host smart-6c83ea4f-3b8d-4d2a-adbf-07812f423d9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429346215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1429346215
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4071060186
Short name T102
Test name
Test status
Simulation time 2357998743 ps
CPU time 65.47 seconds
Started Jul 01 10:40:26 AM PDT 24
Finished Jul 01 10:41:34 AM PDT 24
Peak memory 204968 kb
Host smart-787500c9-8256-4c94-b654-e0701fe2c596
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071060186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.4071060186
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.778744701
Short name T390
Test name
Test status
Simulation time 5824087837 ps
CPU time 66.42 seconds
Started Jul 01 10:40:15 AM PDT 24
Finished Jul 01 10:41:24 AM PDT 24
Peak memory 213212 kb
Host smart-322d353f-3ae6-4fee-a7e8-ddcd53fea910
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778744701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.778744701
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3794897560
Short name T129
Test name
Test status
Simulation time 363401294 ps
CPU time 2.57 seconds
Started Jul 01 10:40:19 AM PDT 24
Finished Jul 01 10:40:25 AM PDT 24
Peak memory 213120 kb
Host smart-eb240a30-17d5-4ff3-881f-4829a12a6d71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794897560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3794897560
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.378797350
Short name T435
Test name
Test status
Simulation time 311925310 ps
CPU time 3.79 seconds
Started Jul 01 10:40:39 AM PDT 24
Finished Jul 01 10:40:43 AM PDT 24
Peak memory 221368 kb
Host smart-b69fdbbf-e7b1-4890-b627-5f1cc21ee6c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378797350 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.378797350
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3720233549
Short name T109
Test name
Test status
Simulation time 130929615 ps
CPU time 2.36 seconds
Started Jul 01 10:40:30 AM PDT 24
Finished Jul 01 10:40:34 AM PDT 24
Peak memory 213072 kb
Host smart-269ae762-d2f4-42e2-a2ba-78a87550ef64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720233549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3720233549
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.766044467
Short name T358
Test name
Test status
Simulation time 47627194336 ps
CPU time 117.95 seconds
Started Jul 01 10:40:25 AM PDT 24
Finished Jul 01 10:42:25 AM PDT 24
Peak memory 204832 kb
Host smart-370932fe-0298-448a-8058-bed37a737f41
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766044467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.766044467
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3333911365
Short name T425
Test name
Test status
Simulation time 35586979191 ps
CPU time 28 seconds
Started Jul 01 10:40:04 AM PDT 24
Finished Jul 01 10:40:34 AM PDT 24
Peak memory 204844 kb
Host smart-8bbee925-063c-45e0-863f-c954da12305e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333911365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.3333911365
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3979331827
Short name T108
Test name
Test status
Simulation time 8807507746 ps
CPU time 17.73 seconds
Started Jul 01 10:40:33 AM PDT 24
Finished Jul 01 10:40:53 AM PDT 24
Peak memory 204900 kb
Host smart-81bcde17-15a2-4712-850d-526a61d92a28
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979331827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3979331827
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2945622401
Short name T422
Test name
Test status
Simulation time 2037372238 ps
CPU time 6.29 seconds
Started Jul 01 10:40:19 AM PDT 24
Finished Jul 01 10:40:29 AM PDT 24
Peak memory 204772 kb
Host smart-b76f725c-7bcb-46ca-be33-d57033c8da48
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945622401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2
945622401
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2018974705
Short name T309
Test name
Test status
Simulation time 542330601 ps
CPU time 2.16 seconds
Started Jul 01 10:40:19 AM PDT 24
Finished Jul 01 10:40:25 AM PDT 24
Peak memory 204568 kb
Host smart-6da59741-872d-4895-9fd7-6c1c5d8516f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018974705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2018974705
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1828587720
Short name T376
Test name
Test status
Simulation time 11760913790 ps
CPU time 8.32 seconds
Started Jul 01 10:40:20 AM PDT 24
Finished Jul 01 10:40:32 AM PDT 24
Peak memory 204824 kb
Host smart-4ccabb36-c9df-48dd-bc04-458deafb47b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828587720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1828587720
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4066638824
Short name T314
Test name
Test status
Simulation time 427694795 ps
CPU time 1.06 seconds
Started Jul 01 10:40:32 AM PDT 24
Finished Jul 01 10:40:34 AM PDT 24
Peak memory 204592 kb
Host smart-a9d23ce3-8890-4672-b643-482dec9e1a38
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066638824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.4066638824
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2661405119
Short name T316
Test name
Test status
Simulation time 430125719 ps
CPU time 1.33 seconds
Started Jul 01 10:40:16 AM PDT 24
Finished Jul 01 10:40:20 AM PDT 24
Peak memory 204604 kb
Host smart-9b527eb9-cf4c-4f5e-ac21-71560ebe79e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661405119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
661405119
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3879498031
Short name T321
Test name
Test status
Simulation time 44637608 ps
CPU time 0.81 seconds
Started Jul 01 10:40:20 AM PDT 24
Finished Jul 01 10:40:25 AM PDT 24
Peak memory 204568 kb
Host smart-4a60e987-27cb-430a-a8c3-61a1dd7b23fb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879498031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3879498031
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1582376119
Short name T315
Test name
Test status
Simulation time 131589155 ps
CPU time 0.82 seconds
Started Jul 01 10:40:22 AM PDT 24
Finished Jul 01 10:40:28 AM PDT 24
Peak memory 204584 kb
Host smart-7d4fca22-0d1d-4813-ad62-ec7434b3cf57
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582376119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1582376119
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.168184472
Short name T125
Test name
Test status
Simulation time 1128750948 ps
CPU time 4.48 seconds
Started Jul 01 10:40:10 AM PDT 24
Finished Jul 01 10:40:21 AM PDT 24
Peak memory 204960 kb
Host smart-11b2f61b-991f-479a-b640-5700a2774581
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168184472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.168184472
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1267564931
Short name T69
Test name
Test status
Simulation time 48885522638 ps
CPU time 97.38 seconds
Started Jul 01 10:40:27 AM PDT 24
Finished Jul 01 10:42:06 AM PDT 24
Peak memory 221400 kb
Host smart-0e4a66c6-ef0e-4d1f-b619-82c39393bcfc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267564931 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1267564931
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3277346161
Short name T94
Test name
Test status
Simulation time 216924466 ps
CPU time 3.21 seconds
Started Jul 01 10:40:27 AM PDT 24
Finished Jul 01 10:40:37 AM PDT 24
Peak memory 213156 kb
Host smart-5419ad0e-c947-46f0-b849-507a830b4095
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277346161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3277346161
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.570942017
Short name T345
Test name
Test status
Simulation time 2425083462 ps
CPU time 10.03 seconds
Started Jul 01 10:40:24 AM PDT 24
Finished Jul 01 10:40:37 AM PDT 24
Peak memory 213228 kb
Host smart-f766b496-081a-4fa6-a401-9e330db8ef94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570942017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.570942017
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3314199282
Short name T421
Test name
Test status
Simulation time 106545579 ps
CPU time 2.01 seconds
Started Jul 01 10:40:18 AM PDT 24
Finished Jul 01 10:40:23 AM PDT 24
Peak memory 215232 kb
Host smart-706734d2-86e6-4c97-92eb-473bd9987777
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314199282 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3314199282
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4108216211
Short name T130
Test name
Test status
Simulation time 114974395 ps
CPU time 2.37 seconds
Started Jul 01 10:40:50 AM PDT 24
Finished Jul 01 10:40:53 AM PDT 24
Peak memory 213100 kb
Host smart-a54a754e-0637-4f90-9e66-2a51ef02301a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108216211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.4108216211
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3247964177
Short name T322
Test name
Test status
Simulation time 4501910756 ps
CPU time 8.92 seconds
Started Jul 01 10:40:24 AM PDT 24
Finished Jul 01 10:40:35 AM PDT 24
Peak memory 204828 kb
Host smart-c37a51da-cbcb-4e3a-a5c5-2ffac80b8432
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247964177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.3247964177
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4039235408
Short name T301
Test name
Test status
Simulation time 3007772409 ps
CPU time 2.72 seconds
Started Jul 01 10:40:23 AM PDT 24
Finished Jul 01 10:40:29 AM PDT 24
Peak memory 204828 kb
Host smart-3f521785-b3cb-4ada-8200-33a4e551d1f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039235408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.4
039235408
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.790865107
Short name T82
Test name
Test status
Simulation time 158366499 ps
CPU time 1.09 seconds
Started Jul 01 10:40:13 AM PDT 24
Finished Jul 01 10:40:16 AM PDT 24
Peak memory 204576 kb
Host smart-31271f5a-87be-4606-8152-1e7ef7f02137
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790865107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.790865107
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1168699232
Short name T402
Test name
Test status
Simulation time 306099724 ps
CPU time 3.59 seconds
Started Jul 01 10:40:23 AM PDT 24
Finished Jul 01 10:40:29 AM PDT 24
Peak memory 204964 kb
Host smart-7af893e4-84eb-4e73-afee-83b5abbd1753
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168699232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1168699232
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2905210099
Short name T166
Test name
Test status
Simulation time 29791039143 ps
CPU time 27.77 seconds
Started Jul 01 10:40:20 AM PDT 24
Finished Jul 01 10:40:52 AM PDT 24
Peak memory 221396 kb
Host smart-98ac75cf-a504-49cb-a3da-833691764b81
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905210099 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2905210099
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1393290498
Short name T158
Test name
Test status
Simulation time 105148361 ps
CPU time 4.8 seconds
Started Jul 01 10:40:27 AM PDT 24
Finished Jul 01 10:40:34 AM PDT 24
Peak memory 213192 kb
Host smart-724c00d9-ffbb-4bef-85ee-65abcfb1e072
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393290498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1393290498
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3565124640
Short name T352
Test name
Test status
Simulation time 4503482742 ps
CPU time 17.29 seconds
Started Jul 01 10:40:28 AM PDT 24
Finished Jul 01 10:40:47 AM PDT 24
Peak memory 213220 kb
Host smart-85afcd37-8a1e-4710-858a-73f7195c70ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565124640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3565124640
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2339600419
Short name T384
Test name
Test status
Simulation time 418019775 ps
CPU time 2.56 seconds
Started Jul 01 10:40:58 AM PDT 24
Finished Jul 01 10:41:01 AM PDT 24
Peak memory 221308 kb
Host smart-da2c57ad-84ce-48b3-972f-65c689b0992c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339600419 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2339600419
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.808053076
Short name T417
Test name
Test status
Simulation time 164886284 ps
CPU time 2.26 seconds
Started Jul 01 10:40:21 AM PDT 24
Finished Jul 01 10:40:27 AM PDT 24
Peak memory 213068 kb
Host smart-a5714398-abe1-43c6-a12b-11ce66fa3c03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808053076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.808053076
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2016693527
Short name T392
Test name
Test status
Simulation time 32524750582 ps
CPU time 90.14 seconds
Started Jul 01 10:40:26 AM PDT 24
Finished Jul 01 10:41:58 AM PDT 24
Peak memory 204848 kb
Host smart-f73af3ce-ffde-4712-bf79-c875d35dd3f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016693527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.2016693527
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2217546791
Short name T311
Test name
Test status
Simulation time 2060605737 ps
CPU time 2.54 seconds
Started Jul 01 10:40:22 AM PDT 24
Finished Jul 01 10:40:28 AM PDT 24
Peak memory 204796 kb
Host smart-5a44de82-820d-4ff7-ab46-a615902dea23
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217546791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
217546791
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.145954114
Short name T312
Test name
Test status
Simulation time 197872620 ps
CPU time 1.11 seconds
Started Jul 01 10:40:21 AM PDT 24
Finished Jul 01 10:40:25 AM PDT 24
Peak memory 204592 kb
Host smart-54a2a21a-f548-4d95-88b2-742c0407a148
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145954114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.145954114
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.274798507
Short name T97
Test name
Test status
Simulation time 451103712 ps
CPU time 4.22 seconds
Started Jul 01 10:40:54 AM PDT 24
Finished Jul 01 10:41:00 AM PDT 24
Peak memory 205012 kb
Host smart-423f26eb-3976-4116-b2f1-05cb4275b1c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274798507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c
sr_outstanding.274798507
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3122878199
Short name T393
Test name
Test status
Simulation time 27687818222 ps
CPU time 43.78 seconds
Started Jul 01 10:40:27 AM PDT 24
Finished Jul 01 10:41:13 AM PDT 24
Peak memory 221416 kb
Host smart-88b0b90b-6e29-4dc5-accd-44ede62a1ade
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122878199 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3122878199
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.42586511
Short name T375
Test name
Test status
Simulation time 289604672 ps
CPU time 5.24 seconds
Started Jul 01 10:41:13 AM PDT 24
Finished Jul 01 10:41:19 AM PDT 24
Peak memory 213148 kb
Host smart-53da0609-3ecd-45ce-82a2-a028e8cd5051
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42586511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.42586511
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2192520495
Short name T165
Test name
Test status
Simulation time 6131112736 ps
CPU time 21.45 seconds
Started Jul 01 10:40:30 AM PDT 24
Finished Jul 01 10:40:53 AM PDT 24
Peak memory 213116 kb
Host smart-98df9f6a-c9a7-478a-91c2-e9b7d68ce305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192520495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2192520495
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3575826072
Short name T420
Test name
Test status
Simulation time 3484772996 ps
CPU time 4.75 seconds
Started Jul 01 10:40:25 AM PDT 24
Finished Jul 01 10:40:32 AM PDT 24
Peak memory 221764 kb
Host smart-9ffa22c1-55c6-4aa8-880d-ee5b5192d917
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575826072 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3575826072
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.590676298
Short name T374
Test name
Test status
Simulation time 145033599 ps
CPU time 2.04 seconds
Started Jul 01 10:40:56 AM PDT 24
Finished Jul 01 10:40:59 AM PDT 24
Peak memory 213092 kb
Host smart-2c218050-2cc2-4965-beff-a825866fcc1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590676298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.590676298
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3895119597
Short name T293
Test name
Test status
Simulation time 22699661982 ps
CPU time 20.11 seconds
Started Jul 01 10:40:59 AM PDT 24
Finished Jul 01 10:41:19 AM PDT 24
Peak memory 204832 kb
Host smart-af8499dd-eb0c-4389-823e-eac55b2e7112
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895119597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.3895119597
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2329822466
Short name T429
Test name
Test status
Simulation time 7174464949 ps
CPU time 2.51 seconds
Started Jul 01 10:40:18 AM PDT 24
Finished Jul 01 10:40:24 AM PDT 24
Peak memory 204840 kb
Host smart-07d87573-39e9-431e-bceb-01087d7d83c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329822466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
329822466
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1102116988
Short name T81
Test name
Test status
Simulation time 457187622 ps
CPU time 1.85 seconds
Started Jul 01 10:40:31 AM PDT 24
Finished Jul 01 10:40:34 AM PDT 24
Peak memory 204592 kb
Host smart-0876386d-63a0-48ef-8884-6ca8b0de7e74
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102116988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
102116988
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3769544707
Short name T359
Test name
Test status
Simulation time 182119812 ps
CPU time 3.62 seconds
Started Jul 01 10:40:24 AM PDT 24
Finished Jul 01 10:40:30 AM PDT 24
Peak memory 204896 kb
Host smart-741d0213-3b08-46c6-b77a-329a90239e66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769544707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3769544707
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.261032880
Short name T68
Test name
Test status
Simulation time 24332233627 ps
CPU time 19.06 seconds
Started Jul 01 10:40:29 AM PDT 24
Finished Jul 01 10:40:50 AM PDT 24
Peak memory 220564 kb
Host smart-b1a5b5b4-6038-4945-aa40-0ec53f4edee4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261032880 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.261032880
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.225839586
Short name T383
Test name
Test status
Simulation time 323040553 ps
CPU time 5.17 seconds
Started Jul 01 10:40:23 AM PDT 24
Finished Jul 01 10:40:31 AM PDT 24
Peak memory 213144 kb
Host smart-be8d2dd1-044d-4a04-95a8-18c908d61fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225839586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.225839586
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3775632740
Short name T163
Test name
Test status
Simulation time 4085672336 ps
CPU time 10.62 seconds
Started Jul 01 10:40:18 AM PDT 24
Finished Jul 01 10:40:32 AM PDT 24
Peak memory 213224 kb
Host smart-96e6f968-8b7c-4f55-9f1e-91d771bb9089
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775632740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3775632740
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.842801024
Short name T341
Test name
Test status
Simulation time 309025556 ps
CPU time 4.68 seconds
Started Jul 01 10:40:07 AM PDT 24
Finished Jul 01 10:40:13 AM PDT 24
Peak memory 221424 kb
Host smart-023fcce1-b693-4b7b-930c-7db38889e122
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842801024 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.842801024
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2982122019
Short name T96
Test name
Test status
Simulation time 155123413 ps
CPU time 2.49 seconds
Started Jul 01 10:40:28 AM PDT 24
Finished Jul 01 10:40:32 AM PDT 24
Peak memory 213104 kb
Host smart-6ad527b1-b47c-456e-b4ed-f78c0c3f39e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982122019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2982122019
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3785410681
Short name T305
Test name
Test status
Simulation time 5243581398 ps
CPU time 13.74 seconds
Started Jul 01 10:40:15 AM PDT 24
Finished Jul 01 10:40:31 AM PDT 24
Peak memory 204840 kb
Host smart-324e4ec8-f9e1-4329-8abf-e1a95debfe46
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785410681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
785410681
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.623358692
Short name T300
Test name
Test status
Simulation time 229334266 ps
CPU time 1.18 seconds
Started Jul 01 10:40:57 AM PDT 24
Finished Jul 01 10:40:59 AM PDT 24
Peak memory 204584 kb
Host smart-71bc9cda-51d0-4dbe-ad78-b627fce8c618
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623358692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.623358692
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.124437860
Short name T371
Test name
Test status
Simulation time 1276627107 ps
CPU time 8.11 seconds
Started Jul 01 10:40:54 AM PDT 24
Finished Jul 01 10:41:03 AM PDT 24
Peak memory 205036 kb
Host smart-1c8bf0ea-ba4d-4a0e-8bb4-6d57a5b439be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124437860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.124437860
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1338579255
Short name T400
Test name
Test status
Simulation time 17436400989 ps
CPU time 55.98 seconds
Started Jul 01 10:40:28 AM PDT 24
Finished Jul 01 10:41:26 AM PDT 24
Peak memory 221312 kb
Host smart-89b7bc91-2c2e-4a18-8f67-0c5cbbb8e401
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338579255 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1338579255
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3922008271
Short name T361
Test name
Test status
Simulation time 275733651 ps
CPU time 3.23 seconds
Started Jul 01 10:40:28 AM PDT 24
Finished Jul 01 10:40:33 AM PDT 24
Peak memory 215652 kb
Host smart-c378bcce-5087-4dcd-9dc2-835e7f75a02d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922008271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3922008271
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3146958357
Short name T95
Test name
Test status
Simulation time 562336034 ps
CPU time 4.3 seconds
Started Jul 01 10:40:52 AM PDT 24
Finished Jul 01 10:40:57 AM PDT 24
Peak memory 219448 kb
Host smart-4eaf9d47-8d7b-416f-976b-865c542cdb81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146958357 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3146958357
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1716492951
Short name T397
Test name
Test status
Simulation time 102097156 ps
CPU time 1.48 seconds
Started Jul 01 10:41:05 AM PDT 24
Finished Jul 01 10:41:07 AM PDT 24
Peak memory 213048 kb
Host smart-fb31b555-bd43-40c1-a9a6-5e7e556872d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716492951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1716492951
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3373816184
Short name T330
Test name
Test status
Simulation time 1905848644 ps
CPU time 5.97 seconds
Started Jul 01 10:40:25 AM PDT 24
Finished Jul 01 10:40:33 AM PDT 24
Peak memory 204776 kb
Host smart-9b7b67a5-d43f-4614-bdaf-8b8ef1453707
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373816184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.3373816184
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1595992477
Short name T310
Test name
Test status
Simulation time 13208103831 ps
CPU time 9.6 seconds
Started Jul 01 10:41:06 AM PDT 24
Finished Jul 01 10:41:16 AM PDT 24
Peak memory 204836 kb
Host smart-013717c5-9e54-4925-8ad2-4cae9e52d9c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595992477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
595992477
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3712490879
Short name T343
Test name
Test status
Simulation time 119452432 ps
CPU time 0.98 seconds
Started Jul 01 10:40:20 AM PDT 24
Finished Jul 01 10:40:25 AM PDT 24
Peak memory 204684 kb
Host smart-f5c185ec-b9e1-4ed9-abdc-04d3f578f3b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712490879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
712490879
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3162819052
Short name T126
Test name
Test status
Simulation time 538062040 ps
CPU time 3.6 seconds
Started Jul 01 10:40:28 AM PDT 24
Finished Jul 01 10:40:33 AM PDT 24
Peak memory 204888 kb
Host smart-e218a9b5-0c66-4c78-8217-7cddb326f9ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162819052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3162819052
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1860949834
Short name T356
Test name
Test status
Simulation time 20274712913 ps
CPU time 59.65 seconds
Started Jul 01 10:40:50 AM PDT 24
Finished Jul 01 10:41:51 AM PDT 24
Peak memory 221364 kb
Host smart-90e4d9e7-6aa6-412c-b9ee-610826bd3d2d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860949834 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.1860949834
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1234103394
Short name T389
Test name
Test status
Simulation time 263588876 ps
CPU time 4.86 seconds
Started Jul 01 10:40:15 AM PDT 24
Finished Jul 01 10:40:21 AM PDT 24
Peak memory 213176 kb
Host smart-b0a87ecc-eabe-4e83-bbb4-44dd6e1e965c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234103394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1234103394
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3709341715
Short name T366
Test name
Test status
Simulation time 3654468080 ps
CPU time 18.36 seconds
Started Jul 01 10:40:06 AM PDT 24
Finished Jul 01 10:40:26 AM PDT 24
Peak memory 213228 kb
Host smart-746afd7c-94bd-49bb-8804-fc67191e7e13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709341715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3709341715
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2222351448
Short name T182
Test name
Test status
Simulation time 57884636 ps
CPU time 0.76 seconds
Started Jul 01 10:52:03 AM PDT 24
Finished Jul 01 10:52:07 AM PDT 24
Peak memory 204872 kb
Host smart-23a85044-964e-49e5-9001-bdd2982d6588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222351448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2222351448
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2100310653
Short name T205
Test name
Test status
Simulation time 4706760508 ps
CPU time 5.05 seconds
Started Jul 01 10:51:52 AM PDT 24
Finished Jul 01 10:51:59 AM PDT 24
Peak memory 205332 kb
Host smart-eefc0313-20ed-4fa2-984f-c3b5f24ce4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100310653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2100310653
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.828455425
Short name T199
Test name
Test status
Simulation time 8641172244 ps
CPU time 4.04 seconds
Started Jul 01 10:51:53 AM PDT 24
Finished Jul 01 10:51:59 AM PDT 24
Peak memory 213336 kb
Host smart-9523a552-4b9c-40cd-b0b9-c69ceeaa4c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828455425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.828455425
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2796165289
Short name T290
Test name
Test status
Simulation time 1259633014 ps
CPU time 1.96 seconds
Started Jul 01 10:51:54 AM PDT 24
Finished Jul 01 10:51:58 AM PDT 24
Peak memory 204772 kb
Host smart-aa720d92-d81c-4699-8977-2f513ee31f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796165289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2796165289
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3302493979
Short name T31
Test name
Test status
Simulation time 391798442 ps
CPU time 1.23 seconds
Started Jul 01 10:51:57 AM PDT 24
Finished Jul 01 10:51:59 AM PDT 24
Peak memory 204744 kb
Host smart-a848bc50-3d39-4cb3-9d4e-f646a211f23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302493979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3302493979
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2914154708
Short name T174
Test name
Test status
Simulation time 781996653 ps
CPU time 2.65 seconds
Started Jul 01 10:51:58 AM PDT 24
Finished Jul 01 10:52:01 AM PDT 24
Peak memory 204856 kb
Host smart-0bffb8b7-ff77-4b3f-b730-6ede18647dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914154708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2914154708
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.3604805713
Short name T44
Test name
Test status
Simulation time 149204564 ps
CPU time 0.82 seconds
Started Jul 01 10:52:02 AM PDT 24
Finished Jul 01 10:52:06 AM PDT 24
Peak memory 215640 kb
Host smart-3715a2c7-a6d4-45c4-b146-4a6fae4208a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604805713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3604805713
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.798808334
Short name T188
Test name
Test status
Simulation time 9877015568 ps
CPU time 10.43 seconds
Started Jul 01 10:51:52 AM PDT 24
Finished Jul 01 10:52:04 AM PDT 24
Peak memory 213476 kb
Host smart-a384b6f7-2ee8-414e-910c-5ada9cde654c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798808334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.798808334
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1602982900
Short name T178
Test name
Test status
Simulation time 1816258287 ps
CPU time 2.42 seconds
Started Jul 01 10:52:02 AM PDT 24
Finished Jul 01 10:52:08 AM PDT 24
Peak memory 204736 kb
Host smart-1a899471-2026-4381-8a65-c24e25b6a3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602982900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1602982900
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2276232480
Short name T286
Test name
Test status
Simulation time 230302835 ps
CPU time 0.86 seconds
Started Jul 01 10:51:58 AM PDT 24
Finished Jul 01 10:51:59 AM PDT 24
Peak memory 204884 kb
Host smart-48a88d66-f7b0-4da7-9650-7c7471f61e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276232480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2276232480
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1527566161
Short name T30
Test name
Test status
Simulation time 4540848829 ps
CPU time 12.95 seconds
Started Jul 01 10:52:02 AM PDT 24
Finished Jul 01 10:52:18 AM PDT 24
Peak memory 204804 kb
Host smart-51bc202f-9316-4963-a420-fe4068a1fa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527566161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1527566161
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2661767361
Short name T245
Test name
Test status
Simulation time 412797137 ps
CPU time 1.03 seconds
Started Jul 01 10:52:01 AM PDT 24
Finished Jul 01 10:52:05 AM PDT 24
Peak memory 204796 kb
Host smart-3775018b-a21b-421c-a7a7-8cfe84cf7349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661767361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2661767361
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2666498504
Short name T7
Test name
Test status
Simulation time 189676820 ps
CPU time 1.3 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:04 AM PDT 24
Peak memory 204868 kb
Host smart-ac21109f-2191-4f44-a93d-35f80cf48182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666498504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2666498504
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1416281288
Short name T170
Test name
Test status
Simulation time 543603616 ps
CPU time 1.47 seconds
Started Jul 01 10:51:52 AM PDT 24
Finished Jul 01 10:51:55 AM PDT 24
Peak memory 204868 kb
Host smart-b6ceac82-3fd7-451a-b045-25ac5e3617a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416281288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1416281288
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1027989352
Short name T276
Test name
Test status
Simulation time 548378414 ps
CPU time 2.09 seconds
Started Jul 01 10:51:54 AM PDT 24
Finished Jul 01 10:51:57 AM PDT 24
Peak memory 204864 kb
Host smart-e5b57c09-c820-432d-a777-aa7d59d8fe8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027989352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1027989352
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3708363600
Short name T138
Test name
Test status
Simulation time 137420908 ps
CPU time 1.02 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:03 AM PDT 24
Peak memory 204884 kb
Host smart-d076547e-3976-4ecd-b048-84b89df99735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708363600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3708363600
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.84566627
Short name T56
Test name
Test status
Simulation time 202703668 ps
CPU time 0.93 seconds
Started Jul 01 10:52:08 AM PDT 24
Finished Jul 01 10:52:11 AM PDT 24
Peak memory 213272 kb
Host smart-d3c16eff-9154-47bd-82cc-4a3a13651e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84566627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.84566627
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1387797843
Short name T261
Test name
Test status
Simulation time 1842331133 ps
CPU time 2.42 seconds
Started Jul 01 10:51:59 AM PDT 24
Finished Jul 01 10:52:02 AM PDT 24
Peak memory 204864 kb
Host smart-f13fe42c-6e13-49f0-a11e-69cfc8fbded7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387797843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1387797843
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3384471453
Short name T186
Test name
Test status
Simulation time 5145011932 ps
CPU time 13.31 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:16 AM PDT 24
Peak memory 205276 kb
Host smart-e0528137-4424-4383-96cc-fbfe8cc313a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384471453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3384471453
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.969543396
Short name T278
Test name
Test status
Simulation time 3581452101 ps
CPU time 3 seconds
Started Jul 01 10:51:52 AM PDT 24
Finished Jul 01 10:51:57 AM PDT 24
Peak memory 205144 kb
Host smart-7e24c943-685a-499a-a7b1-c2e422de6b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969543396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.969543396
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.637820415
Short name T218
Test name
Test status
Simulation time 10617273884 ps
CPU time 10.85 seconds
Started Jul 01 10:51:58 AM PDT 24
Finished Jul 01 10:52:10 AM PDT 24
Peak memory 205096 kb
Host smart-b8b76713-7338-4929-a1ed-06b10a7f0b7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637820415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.637820415
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.2592143691
Short name T35
Test name
Test status
Simulation time 248513460 ps
CPU time 1.3 seconds
Started Jul 01 10:52:03 AM PDT 24
Finished Jul 01 10:52:07 AM PDT 24
Peak memory 204864 kb
Host smart-6c33833c-f32a-40f5-bcac-9e7ba1c397bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592143691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2592143691
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2310070551
Short name T40
Test name
Test status
Simulation time 169297133 ps
CPU time 0.77 seconds
Started Jul 01 10:52:03 AM PDT 24
Finished Jul 01 10:52:07 AM PDT 24
Peak memory 204788 kb
Host smart-1c63bac6-d83d-4c64-8399-40d229276e9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310070551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2310070551
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1438773664
Short name T230
Test name
Test status
Simulation time 5394205066 ps
CPU time 8.87 seconds
Started Jul 01 10:52:03 AM PDT 24
Finished Jul 01 10:52:15 AM PDT 24
Peak memory 213512 kb
Host smart-545369ef-9f20-44e1-9715-2fa5ea481eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438773664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1438773664
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2258244521
Short name T240
Test name
Test status
Simulation time 4382056775 ps
CPU time 5.84 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:07 AM PDT 24
Peak memory 205236 kb
Host smart-998b9e50-0a84-4dff-8bbe-964a5b57a74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258244521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2258244521
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1761812113
Short name T25
Test name
Test status
Simulation time 173983438 ps
CPU time 0.85 seconds
Started Jul 01 10:52:02 AM PDT 24
Finished Jul 01 10:52:06 AM PDT 24
Peak memory 204880 kb
Host smart-e3285d4f-c801-4258-83a2-d9c67161100f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761812113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1761812113
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2950871725
Short name T58
Test name
Test status
Simulation time 937561381 ps
CPU time 2.92 seconds
Started Jul 01 10:52:01 AM PDT 24
Finished Jul 01 10:52:07 AM PDT 24
Peak memory 204904 kb
Host smart-3034f9b3-d00a-4e5c-ba06-57863982122c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950871725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2950871725
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1469626755
Short name T202
Test name
Test status
Simulation time 118624531 ps
CPU time 0.96 seconds
Started Jul 01 10:52:04 AM PDT 24
Finished Jul 01 10:52:08 AM PDT 24
Peak memory 204880 kb
Host smart-6e845ed2-29c2-475b-8326-f4e869f30540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469626755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1469626755
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.4092629973
Short name T34
Test name
Test status
Simulation time 137000599 ps
CPU time 0.74 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:03 AM PDT 24
Peak memory 204892 kb
Host smart-d9a54360-a9ae-47d5-86fd-4f527de9a260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092629973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.4092629973
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.843714687
Short name T236
Test name
Test status
Simulation time 1005560309 ps
CPU time 2.29 seconds
Started Jul 01 10:51:59 AM PDT 24
Finished Jul 01 10:52:02 AM PDT 24
Peak memory 205208 kb
Host smart-e734265b-4997-4251-b79f-0c65e34f3f58
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=843714687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl
_access.843714687
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3251919096
Short name T173
Test name
Test status
Simulation time 1824853709 ps
CPU time 2.77 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:06 AM PDT 24
Peak memory 204868 kb
Host smart-7b3ea067-81c5-4a43-9fd7-ec58e348c740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251919096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3251919096
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3236433975
Short name T146
Test name
Test status
Simulation time 319294963 ps
CPU time 0.95 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:03 AM PDT 24
Peak memory 204864 kb
Host smart-28ba9810-21fe-4af1-b0d8-51675be6884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236433975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3236433975
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2961456821
Short name T150
Test name
Test status
Simulation time 152662172 ps
CPU time 0.94 seconds
Started Jul 01 10:52:02 AM PDT 24
Finished Jul 01 10:52:06 AM PDT 24
Peak memory 204864 kb
Host smart-d95642a2-7aae-4c46-b958-780e55fe66ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961456821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2961456821
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1280856569
Short name T254
Test name
Test status
Simulation time 1161161711 ps
CPU time 1.16 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:04 AM PDT 24
Peak memory 204912 kb
Host smart-ec789d3e-cccf-4f74-ae94-21c1fbfba584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280856569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1280856569
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.931978764
Short name T66
Test name
Test status
Simulation time 3843683682 ps
CPU time 3.93 seconds
Started Jul 01 10:52:01 AM PDT 24
Finished Jul 01 10:52:08 AM PDT 24
Peak memory 204960 kb
Host smart-8637cce7-4d8b-47b9-a840-117266109db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931978764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.931978764
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2713092097
Short name T233
Test name
Test status
Simulation time 104810611 ps
CPU time 0.99 seconds
Started Jul 01 10:52:05 AM PDT 24
Finished Jul 01 10:52:09 AM PDT 24
Peak memory 204876 kb
Host smart-cd43f286-2509-4724-b37b-feade7522db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713092097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2713092097
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2844900005
Short name T140
Test name
Test status
Simulation time 207517959 ps
CPU time 0.74 seconds
Started Jul 01 10:52:09 AM PDT 24
Finished Jul 01 10:52:13 AM PDT 24
Peak memory 204856 kb
Host smart-1eb1b077-be43-4c6c-9e3f-7384767bdfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844900005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2844900005
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3200694833
Short name T169
Test name
Test status
Simulation time 721653548 ps
CPU time 1.56 seconds
Started Jul 01 10:52:06 AM PDT 24
Finished Jul 01 10:52:10 AM PDT 24
Peak memory 204892 kb
Host smart-e98f3942-8219-4bc3-8c0a-2c32b81481d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200694833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3200694833
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.56107019
Short name T238
Test name
Test status
Simulation time 787516743 ps
CPU time 1.07 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:03 AM PDT 24
Peak memory 204880 kb
Host smart-47f046ed-a795-402b-b386-f41c6a2951f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56107019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.56107019
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1350587859
Short name T20
Test name
Test status
Simulation time 392746258 ps
CPU time 1.35 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:03 AM PDT 24
Peak memory 204868 kb
Host smart-cc55e5ca-8386-4299-94d6-ee4182ac569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350587859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1350587859
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3770583652
Short name T62
Test name
Test status
Simulation time 264351849 ps
CPU time 1.36 seconds
Started Jul 01 10:52:15 AM PDT 24
Finished Jul 01 10:52:19 AM PDT 24
Peak memory 204740 kb
Host smart-3cb0ffc0-48be-40c6-ad83-a641d03a2f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770583652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3770583652
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.109495674
Short name T225
Test name
Test status
Simulation time 3842796201 ps
CPU time 3.56 seconds
Started Jul 01 10:52:01 AM PDT 24
Finished Jul 01 10:52:08 AM PDT 24
Peak memory 204924 kb
Host smart-2386e853-3304-48f6-8734-144ebfb0a2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109495674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.109495674
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1104997468
Short name T239
Test name
Test status
Simulation time 5722470310 ps
CPU time 4.97 seconds
Started Jul 01 10:52:18 AM PDT 24
Finished Jul 01 10:52:24 AM PDT 24
Peak memory 213488 kb
Host smart-314913a4-f5ea-498f-abb6-e992fbca697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104997468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1104997468
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3318539944
Short name T64
Test name
Test status
Simulation time 516182737 ps
CPU time 1.62 seconds
Started Jul 01 10:52:04 AM PDT 24
Finished Jul 01 10:52:08 AM PDT 24
Peak memory 237316 kb
Host smart-814b1b48-2e62-4aec-939d-bb9dd255ac06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318539944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3318539944
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3276332690
Short name T269
Test name
Test status
Simulation time 2167133545 ps
CPU time 6.68 seconds
Started Jul 01 10:52:02 AM PDT 24
Finished Jul 01 10:52:11 AM PDT 24
Peak memory 204932 kb
Host smart-266b4928-3835-41fc-9933-a4d04acced7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276332690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3276332690
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.3833494275
Short name T148
Test name
Test status
Simulation time 4550691680 ps
CPU time 13.26 seconds
Started Jul 01 10:52:11 AM PDT 24
Finished Jul 01 10:52:27 AM PDT 24
Peak memory 214976 kb
Host smart-13813412-7635-4c2b-991a-3d77f6bbf742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833494275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3833494275
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2422477444
Short name T235
Test name
Test status
Simulation time 39910309 ps
CPU time 0.77 seconds
Started Jul 01 10:52:14 AM PDT 24
Finished Jul 01 10:52:18 AM PDT 24
Peak memory 204892 kb
Host smart-c7d74fce-9847-4308-8cbf-7139e855ca7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422477444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2422477444
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1285660269
Short name T259
Test name
Test status
Simulation time 4984340653 ps
CPU time 13.58 seconds
Started Jul 01 10:52:14 AM PDT 24
Finished Jul 01 10:52:31 AM PDT 24
Peak memory 213696 kb
Host smart-c83f8ce4-d557-42a4-b4ac-04a4e13bf15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285660269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1285660269
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3489692723
Short name T51
Test name
Test status
Simulation time 7171780242 ps
CPU time 21.98 seconds
Started Jul 01 10:52:14 AM PDT 24
Finished Jul 01 10:52:39 AM PDT 24
Peak memory 213476 kb
Host smart-945c5bd6-33d6-45fe-a67d-73b09e583ef5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3489692723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3489692723
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3870231079
Short name T246
Test name
Test status
Simulation time 2581272106 ps
CPU time 4.27 seconds
Started Jul 01 10:52:15 AM PDT 24
Finished Jul 01 10:52:22 AM PDT 24
Peak memory 205268 kb
Host smart-951b4d81-3353-40bd-ae28-af8e0fdebbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870231079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3870231079
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2732056909
Short name T223
Test name
Test status
Simulation time 92639789 ps
CPU time 0.9 seconds
Started Jul 01 10:52:19 AM PDT 24
Finished Jul 01 10:52:22 AM PDT 24
Peak memory 204876 kb
Host smart-b4a6b87d-b8ba-4cc9-bd09-9d1c50a1117e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732056909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2732056909
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2069700388
Short name T249
Test name
Test status
Simulation time 7177907829 ps
CPU time 18.02 seconds
Started Jul 01 10:52:42 AM PDT 24
Finished Jul 01 10:53:04 AM PDT 24
Peak memory 213688 kb
Host smart-8c85b3b6-93b1-4773-b419-ff298ec7beb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069700388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2069700388
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1320431523
Short name T29
Test name
Test status
Simulation time 2196235387 ps
CPU time 2.5 seconds
Started Jul 01 10:52:40 AM PDT 24
Finished Jul 01 10:52:46 AM PDT 24
Peak memory 205312 kb
Host smart-f9a25e9a-ffff-46ad-bc1a-524e3ee79fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320431523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1320431523
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.220482752
Short name T156
Test name
Test status
Simulation time 2848107604 ps
CPU time 3.65 seconds
Started Jul 01 10:52:46 AM PDT 24
Finished Jul 01 10:52:53 AM PDT 24
Peak memory 205428 kb
Host smart-3dab488a-6eb3-4123-a328-2ade8706dcbf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=220482752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.220482752
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1667648770
Short name T267
Test name
Test status
Simulation time 7501730801 ps
CPU time 12.36 seconds
Started Jul 01 10:52:27 AM PDT 24
Finished Jul 01 10:52:40 AM PDT 24
Peak memory 213432 kb
Host smart-ff35f7fa-f3cf-41a5-81b4-30c30bc63183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667648770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1667648770
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1070647096
Short name T39
Test name
Test status
Simulation time 142700753 ps
CPU time 0.88 seconds
Started Jul 01 10:52:19 AM PDT 24
Finished Jul 01 10:52:22 AM PDT 24
Peak memory 204864 kb
Host smart-a46c6136-eeb7-48a0-8e4f-b154ccc421da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070647096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1070647096
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2892647592
Short name T145
Test name
Test status
Simulation time 5444459686 ps
CPU time 9.04 seconds
Started Jul 01 10:52:20 AM PDT 24
Finished Jul 01 10:52:32 AM PDT 24
Peak memory 205280 kb
Host smart-38d4fcc0-5e44-46dc-b1bd-f2ab40093e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892647592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2892647592
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3560604272
Short name T209
Test name
Test status
Simulation time 2203431042 ps
CPU time 3.68 seconds
Started Jul 01 10:52:19 AM PDT 24
Finished Jul 01 10:52:26 AM PDT 24
Peak memory 213488 kb
Host smart-5a834d27-9ab8-4b30-b67b-0300deebd4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560604272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3560604272
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1614965673
Short name T273
Test name
Test status
Simulation time 12887913812 ps
CPU time 33.98 seconds
Started Jul 01 10:52:40 AM PDT 24
Finished Jul 01 10:53:27 AM PDT 24
Peak memory 213508 kb
Host smart-8951bc6e-8b17-43e1-bc62-2f5594457df3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1614965673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1614965673
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.1363069218
Short name T289
Test name
Test status
Simulation time 1547753598 ps
CPU time 4.53 seconds
Started Jul 01 10:52:38 AM PDT 24
Finished Jul 01 10:52:44 AM PDT 24
Peak memory 205228 kb
Host smart-6a4fbfe9-fba7-42c9-864d-8c233e97b152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363069218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1363069218
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3768827939
Short name T137
Test name
Test status
Simulation time 6268930632 ps
CPU time 15.71 seconds
Started Jul 01 10:52:43 AM PDT 24
Finished Jul 01 10:53:02 AM PDT 24
Peak memory 213320 kb
Host smart-1d254c8d-c02e-46a7-ae9c-e5fd51c3e501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768827939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3768827939
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1564295641
Short name T132
Test name
Test status
Simulation time 211428216 ps
CPU time 0.74 seconds
Started Jul 01 10:52:30 AM PDT 24
Finished Jul 01 10:52:32 AM PDT 24
Peak memory 204868 kb
Host smart-4a45b246-1410-498b-a9f0-ea62de2eb79d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564295641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1564295641
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1081088883
Short name T222
Test name
Test status
Simulation time 8257609122 ps
CPU time 8.7 seconds
Started Jul 01 10:52:19 AM PDT 24
Finished Jul 01 10:52:30 AM PDT 24
Peak memory 213472 kb
Host smart-33028006-5b90-40d3-bed9-666b1f06be47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081088883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1081088883
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3296780333
Short name T263
Test name
Test status
Simulation time 2512912696 ps
CPU time 1.83 seconds
Started Jul 01 10:52:17 AM PDT 24
Finished Jul 01 10:52:20 AM PDT 24
Peak memory 213476 kb
Host smart-1c9a12d2-ac68-4e80-b16d-2607ad7f9bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296780333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3296780333
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3637706349
Short name T50
Test name
Test status
Simulation time 5034071622 ps
CPU time 6 seconds
Started Jul 01 10:52:34 AM PDT 24
Finished Jul 01 10:52:41 AM PDT 24
Peak memory 213472 kb
Host smart-975e54e8-4e74-43f3-acf3-a7970ef969fc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3637706349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3637706349
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.802086820
Short name T258
Test name
Test status
Simulation time 1694162339 ps
CPU time 2.28 seconds
Started Jul 01 10:52:38 AM PDT 24
Finished Jul 01 10:52:41 AM PDT 24
Peak memory 205252 kb
Host smart-58c1ac85-3b56-4ab1-8729-64af7c6ffce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802086820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.802086820
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2831443617
Short name T208
Test name
Test status
Simulation time 82909988 ps
CPU time 0.74 seconds
Started Jul 01 10:52:22 AM PDT 24
Finished Jul 01 10:52:24 AM PDT 24
Peak memory 204960 kb
Host smart-6d4123c7-7b6d-4bab-bf44-94e7c8df2f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831443617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2831443617
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1085077608
Short name T185
Test name
Test status
Simulation time 4527932696 ps
CPU time 3.67 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:52:46 AM PDT 24
Peak memory 213528 kb
Host smart-6b8c8c60-89dd-480f-bc9a-4054efca9905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085077608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1085077608
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3185640221
Short name T53
Test name
Test status
Simulation time 2523497689 ps
CPU time 2.82 seconds
Started Jul 01 10:52:38 AM PDT 24
Finished Jul 01 10:52:43 AM PDT 24
Peak memory 214472 kb
Host smart-11db96ef-2bac-4f32-b6c9-9cbc9b33c4ed
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3185640221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3185640221
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.635480090
Short name T248
Test name
Test status
Simulation time 3657182295 ps
CPU time 2.56 seconds
Started Jul 01 10:52:33 AM PDT 24
Finished Jul 01 10:52:37 AM PDT 24
Peak memory 205268 kb
Host smart-d517699a-af4f-42fc-938f-06363ea286f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635480090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.635480090
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3208100960
Short name T152
Test name
Test status
Simulation time 15356948489 ps
CPU time 39.99 seconds
Started Jul 01 10:52:24 AM PDT 24
Finished Jul 01 10:53:06 AM PDT 24
Peak memory 205164 kb
Host smart-ec192f6d-fb3e-4275-ab59-79c5a9363f39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208100960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3208100960
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3494155936
Short name T214
Test name
Test status
Simulation time 59403062 ps
CPU time 0.81 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:52:43 AM PDT 24
Peak memory 204896 kb
Host smart-36e17cd3-d460-4a7e-b6b3-06ecdf0b884d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494155936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3494155936
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3212166951
Short name T203
Test name
Test status
Simulation time 2900700564 ps
CPU time 4.92 seconds
Started Jul 01 10:52:25 AM PDT 24
Finished Jul 01 10:52:32 AM PDT 24
Peak memory 205292 kb
Host smart-53d2de6e-817b-4a3e-825c-2ffec62d2470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212166951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3212166951
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.294585375
Short name T216
Test name
Test status
Simulation time 811297423 ps
CPU time 1.54 seconds
Started Jul 01 10:52:25 AM PDT 24
Finished Jul 01 10:52:28 AM PDT 24
Peak memory 205204 kb
Host smart-81fccddf-8f7c-4981-b57d-88c847e45410
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=294585375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.294585375
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.262641499
Short name T280
Test name
Test status
Simulation time 15606954044 ps
CPU time 40.28 seconds
Started Jul 01 10:52:24 AM PDT 24
Finished Jul 01 10:53:06 AM PDT 24
Peak memory 213504 kb
Host smart-0368a900-f927-4e7e-9281-d1efa9526273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262641499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.262641499
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.3146389104
Short name T288
Test name
Test status
Simulation time 18805740031 ps
CPU time 14.21 seconds
Started Jul 01 10:52:25 AM PDT 24
Finished Jul 01 10:52:41 AM PDT 24
Peak memory 213376 kb
Host smart-b79027c6-5a41-474f-afc0-21a73e424fe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146389104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3146389104
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3924596387
Short name T271
Test name
Test status
Simulation time 19960825592 ps
CPU time 28.14 seconds
Started Jul 01 10:52:23 AM PDT 24
Finished Jul 01 10:52:52 AM PDT 24
Peak memory 213460 kb
Host smart-be7254e4-af75-407b-9b19-f5bace945920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924596387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3924596387
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3252097288
Short name T251
Test name
Test status
Simulation time 2031211791 ps
CPU time 5.78 seconds
Started Jul 01 10:52:45 AM PDT 24
Finished Jul 01 10:52:54 AM PDT 24
Peak memory 213388 kb
Host smart-496223ef-4b5a-4314-bcc3-33bf566a4430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252097288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3252097288
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1953017276
Short name T255
Test name
Test status
Simulation time 3802357584 ps
CPU time 3.21 seconds
Started Jul 01 10:52:43 AM PDT 24
Finished Jul 01 10:52:49 AM PDT 24
Peak memory 213324 kb
Host smart-96c25821-cd8c-4c6b-8fed-3514dd0ba66f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1953017276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1953017276
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.3176478748
Short name T253
Test name
Test status
Simulation time 10625987270 ps
CPU time 28.08 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:53:10 AM PDT 24
Peak memory 213340 kb
Host smart-df9a9f66-a37b-4c73-beb2-c159a91ecdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176478748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3176478748
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.1255749221
Short name T9
Test name
Test status
Simulation time 4820279987 ps
CPU time 12.38 seconds
Started Jul 01 10:52:25 AM PDT 24
Finished Jul 01 10:52:39 AM PDT 24
Peak memory 215168 kb
Host smart-0c502bcf-2fe2-4a9a-a02b-50de1a29db60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255749221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1255749221
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2533779146
Short name T48
Test name
Test status
Simulation time 38705367 ps
CPU time 0.77 seconds
Started Jul 01 10:52:29 AM PDT 24
Finished Jul 01 10:52:31 AM PDT 24
Peak memory 204896 kb
Host smart-0d223755-76b4-4e03-8906-0eccf2162166
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533779146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2533779146
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1492029688
Short name T2
Test name
Test status
Simulation time 5803009595 ps
CPU time 15.26 seconds
Started Jul 01 10:52:27 AM PDT 24
Finished Jul 01 10:52:43 AM PDT 24
Peak memory 205256 kb
Host smart-428ba646-c19a-417b-a464-e2aa6aad7ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492029688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1492029688
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1480170222
Short name T282
Test name
Test status
Simulation time 1544958053 ps
CPU time 1.95 seconds
Started Jul 01 10:52:40 AM PDT 24
Finished Jul 01 10:52:45 AM PDT 24
Peak memory 205164 kb
Host smart-6aff370f-3d18-4ca2-ae71-12372e39523a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480170222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1480170222
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2835837069
Short name T237
Test name
Test status
Simulation time 2222583116 ps
CPU time 5.24 seconds
Started Jul 01 10:52:33 AM PDT 24
Finished Jul 01 10:52:39 AM PDT 24
Peak memory 213460 kb
Host smart-19808de9-426b-4597-99a8-6f7387f8efe3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2835837069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.2835837069
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.248414150
Short name T279
Test name
Test status
Simulation time 1889899811 ps
CPU time 3.23 seconds
Started Jul 01 10:52:24 AM PDT 24
Finished Jul 01 10:52:29 AM PDT 24
Peak memory 213404 kb
Host smart-0a924299-7251-476d-b04a-23d6f96c57b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248414150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.248414150
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.1186379889
Short name T33
Test name
Test status
Simulation time 2367065868 ps
CPU time 4.1 seconds
Started Jul 01 10:52:30 AM PDT 24
Finished Jul 01 10:52:35 AM PDT 24
Peak memory 213332 kb
Host smart-49ade765-4adf-46f4-867f-acc630d47b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186379889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1186379889
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.865517277
Short name T266
Test name
Test status
Simulation time 52228184 ps
CPU time 0.77 seconds
Started Jul 01 10:52:41 AM PDT 24
Finished Jul 01 10:52:44 AM PDT 24
Peak memory 204888 kb
Host smart-c476f584-53b4-479c-a601-da841a95561e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865517277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.865517277
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2913846137
Short name T183
Test name
Test status
Simulation time 55678065669 ps
CPU time 143.5 seconds
Started Jul 01 10:52:42 AM PDT 24
Finished Jul 01 10:55:09 AM PDT 24
Peak memory 214856 kb
Host smart-99591118-21aa-4d0b-b473-663cf95bdbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913846137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2913846137
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3872767292
Short name T184
Test name
Test status
Simulation time 14229546064 ps
CPU time 11.54 seconds
Started Jul 01 10:52:34 AM PDT 24
Finished Jul 01 10:52:46 AM PDT 24
Peak memory 213408 kb
Host smart-1d7157be-6512-450a-be8e-0ec680397a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872767292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3872767292
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.190052613
Short name T281
Test name
Test status
Simulation time 2371519638 ps
CPU time 7.47 seconds
Started Jul 01 10:52:38 AM PDT 24
Finished Jul 01 10:52:48 AM PDT 24
Peak memory 205272 kb
Host smart-45225a43-84ff-4bbc-9a2f-7d0ece62f055
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=190052613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.190052613
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3931297292
Short name T242
Test name
Test status
Simulation time 5794309332 ps
CPU time 16.27 seconds
Started Jul 01 10:52:42 AM PDT 24
Finished Jul 01 10:53:02 AM PDT 24
Peak memory 221596 kb
Host smart-b339fe26-0308-48f2-a5dd-6d22935e815a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931297292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3931297292
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.929799734
Short name T176
Test name
Test status
Simulation time 1675032795 ps
CPU time 5.95 seconds
Started Jul 01 10:52:37 AM PDT 24
Finished Jul 01 10:52:44 AM PDT 24
Peak memory 205032 kb
Host smart-be716e63-23f6-4a08-a023-6e5a1192ba79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929799734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.929799734
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.556626502
Short name T192
Test name
Test status
Simulation time 81390012 ps
CPU time 0.75 seconds
Started Jul 01 10:52:36 AM PDT 24
Finished Jul 01 10:52:38 AM PDT 24
Peak memory 204904 kb
Host smart-94e4a40e-cee0-4c2d-98f4-556c62cb2f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556626502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.556626502
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.344910398
Short name T219
Test name
Test status
Simulation time 72763743867 ps
CPU time 81.57 seconds
Started Jul 01 10:52:29 AM PDT 24
Finished Jul 01 10:53:51 AM PDT 24
Peak memory 213524 kb
Host smart-c5d7fea4-6cb8-4b4f-8917-3e6091592e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344910398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.344910398
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3616339709
Short name T87
Test name
Test status
Simulation time 2994363648 ps
CPU time 3.53 seconds
Started Jul 01 10:52:32 AM PDT 24
Finished Jul 01 10:52:37 AM PDT 24
Peak memory 213412 kb
Host smart-29b54387-072c-4b59-8ff8-ef10b330c086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616339709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3616339709
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1811064508
Short name T139
Test name
Test status
Simulation time 2846146831 ps
CPU time 8.58 seconds
Started Jul 01 10:52:27 AM PDT 24
Finished Jul 01 10:52:37 AM PDT 24
Peak memory 213444 kb
Host smart-53a79e2e-e0a2-4225-a5a4-a943f62cb240
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1811064508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1811064508
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.114447795
Short name T14
Test name
Test status
Simulation time 696134209 ps
CPU time 1.78 seconds
Started Jul 01 10:52:27 AM PDT 24
Finished Jul 01 10:52:30 AM PDT 24
Peak memory 205204 kb
Host smart-a2213ead-8d62-4f42-948a-c52bd809647f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114447795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.114447795
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.948268406
Short name T256
Test name
Test status
Simulation time 79566645 ps
CPU time 0.72 seconds
Started Jul 01 10:52:07 AM PDT 24
Finished Jul 01 10:52:10 AM PDT 24
Peak memory 204896 kb
Host smart-b1471f06-6d7a-456d-8e7d-4f8fbeeeeb1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948268406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.948268406
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1440609017
Short name T224
Test name
Test status
Simulation time 18876054070 ps
CPU time 39.97 seconds
Started Jul 01 10:52:05 AM PDT 24
Finished Jul 01 10:52:48 AM PDT 24
Peak memory 213444 kb
Host smart-c9286ecf-5812-40f7-af94-c5cfc24379ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440609017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1440609017
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1052528079
Short name T141
Test name
Test status
Simulation time 2795484952 ps
CPU time 5.39 seconds
Started Jul 01 10:52:07 AM PDT 24
Finished Jul 01 10:52:14 AM PDT 24
Peak memory 213476 kb
Host smart-f7ebb9c6-a891-44db-b661-c88d569274dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052528079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1052528079
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3063885795
Short name T243
Test name
Test status
Simulation time 9783866784 ps
CPU time 7.9 seconds
Started Jul 01 10:52:03 AM PDT 24
Finished Jul 01 10:52:14 AM PDT 24
Peak memory 213496 kb
Host smart-f440c149-cc18-4c60-8f54-4fda12ec3458
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063885795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3063885795
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2673326370
Short name T252
Test name
Test status
Simulation time 332552740 ps
CPU time 1.59 seconds
Started Jul 01 10:52:11 AM PDT 24
Finished Jul 01 10:52:15 AM PDT 24
Peak memory 204868 kb
Host smart-96e48990-eb78-465a-889c-7c5eded1515e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673326370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2673326370
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.4003546264
Short name T228
Test name
Test status
Simulation time 2682329816 ps
CPU time 2.55 seconds
Started Jul 01 10:52:05 AM PDT 24
Finished Jul 01 10:52:10 AM PDT 24
Peak memory 205336 kb
Host smart-c94b5e78-5516-4fc6-933c-77286c4f2c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003546264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.4003546264
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1047043423
Short name T79
Test name
Test status
Simulation time 848942023 ps
CPU time 2.97 seconds
Started Jul 01 10:52:05 AM PDT 24
Finished Jul 01 10:52:11 AM PDT 24
Peak memory 237012 kb
Host smart-10077914-5dd3-40f6-bc5d-f42d976eb214
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047043423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1047043423
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1266219947
Short name T190
Test name
Test status
Simulation time 84080388 ps
CPU time 0.76 seconds
Started Jul 01 10:52:31 AM PDT 24
Finished Jul 01 10:52:33 AM PDT 24
Peak memory 204876 kb
Host smart-a9c76436-263f-4542-b33c-52a1d07e08a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266219947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1266219947
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.1174678737
Short name T187
Test name
Test status
Simulation time 4564591215 ps
CPU time 11.67 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:52:54 AM PDT 24
Peak memory 213272 kb
Host smart-6af9396d-fd23-4854-88df-39183d32bd2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174678737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.1174678737
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2125491827
Short name T227
Test name
Test status
Simulation time 56713622 ps
CPU time 0.72 seconds
Started Jul 01 10:52:32 AM PDT 24
Finished Jul 01 10:52:34 AM PDT 24
Peak memory 204872 kb
Host smart-6941428e-da1a-485f-8dac-c4e3030859d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125491827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2125491827
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.2264086941
Short name T22
Test name
Test status
Simulation time 11505749037 ps
CPU time 8.94 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:52:51 AM PDT 24
Peak memory 213316 kb
Host smart-c6e5c746-0c29-4713-9dea-7a0b067ef70b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264086941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2264086941
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.1013511782
Short name T201
Test name
Test status
Simulation time 105538032 ps
CPU time 0.76 seconds
Started Jul 01 10:52:31 AM PDT 24
Finished Jul 01 10:52:33 AM PDT 24
Peak memory 204876 kb
Host smart-5d4b2522-ce20-4170-9a69-86c45307c435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013511782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1013511782
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2202296505
Short name T250
Test name
Test status
Simulation time 191088436 ps
CPU time 0.75 seconds
Started Jul 01 10:52:26 AM PDT 24
Finished Jul 01 10:52:28 AM PDT 24
Peak memory 204884 kb
Host smart-b40f2453-8158-44f8-af1c-7dcb58c51130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202296505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2202296505
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.3948242666
Short name T179
Test name
Test status
Simulation time 5577591150 ps
CPU time 3.61 seconds
Started Jul 01 10:52:31 AM PDT 24
Finished Jul 01 10:52:36 AM PDT 24
Peak memory 205088 kb
Host smart-97ea7323-338e-4910-bfcd-f36310c96420
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948242666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3948242666
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2356558163
Short name T275
Test name
Test status
Simulation time 127526118 ps
CPU time 0.7 seconds
Started Jul 01 10:52:38 AM PDT 24
Finished Jul 01 10:52:41 AM PDT 24
Peak memory 204872 kb
Host smart-1d579036-d79b-41cb-9c08-a858508b9c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356558163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2356558163
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2045304596
Short name T221
Test name
Test status
Simulation time 183079871 ps
CPU time 0.78 seconds
Started Jul 01 10:52:27 AM PDT 24
Finished Jul 01 10:52:29 AM PDT 24
Peak memory 204888 kb
Host smart-2adb1bcf-e9e4-437c-b83c-f1423ff74ff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045304596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2045304596
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.50350031
Short name T5
Test name
Test status
Simulation time 16495856759 ps
CPU time 22.78 seconds
Started Jul 01 10:52:27 AM PDT 24
Finished Jul 01 10:52:51 AM PDT 24
Peak memory 213292 kb
Host smart-7f7ac72e-bf43-4ee7-9348-d2fdc5c0d43c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50350031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.50350031
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.913794043
Short name T189
Test name
Test status
Simulation time 65280770 ps
CPU time 0.76 seconds
Started Jul 01 10:52:43 AM PDT 24
Finished Jul 01 10:52:47 AM PDT 24
Peak memory 204868 kb
Host smart-99b5091c-7037-4657-869c-55921be6004d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913794043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.913794043
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.348855568
Short name T244
Test name
Test status
Simulation time 45790364 ps
CPU time 0.81 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:52:42 AM PDT 24
Peak memory 204640 kb
Host smart-47b1ca19-37df-4d36-bd3a-bf06538a60d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348855568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.348855568
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.4036028827
Short name T168
Test name
Test status
Simulation time 2663696496 ps
CPU time 4.28 seconds
Started Jul 01 10:52:32 AM PDT 24
Finished Jul 01 10:52:38 AM PDT 24
Peak memory 205184 kb
Host smart-1930dccf-4725-47c1-8511-cdea7cfc6c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036028827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.4036028827
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1741139544
Short name T200
Test name
Test status
Simulation time 110613583 ps
CPU time 0.8 seconds
Started Jul 01 10:52:31 AM PDT 24
Finished Jul 01 10:52:33 AM PDT 24
Peak memory 204856 kb
Host smart-0e956e1d-a6cd-4a13-9634-897c85964dec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741139544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1741139544
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1547732164
Short name T232
Test name
Test status
Simulation time 101735635 ps
CPU time 0.78 seconds
Started Jul 01 10:52:34 AM PDT 24
Finished Jul 01 10:52:36 AM PDT 24
Peak memory 204880 kb
Host smart-32824448-8189-4633-9a59-2c2e77225a23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547732164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1547732164
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.2671776493
Short name T23
Test name
Test status
Simulation time 4679630882 ps
CPU time 7.47 seconds
Started Jul 01 10:52:41 AM PDT 24
Finished Jul 01 10:52:51 AM PDT 24
Peak memory 205172 kb
Host smart-33dd0a6a-16cc-49f3-aeb7-c52dd13da3b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671776493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.2671776493
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.93571157
Short name T206
Test name
Test status
Simulation time 62244599 ps
CPU time 0.86 seconds
Started Jul 01 10:52:36 AM PDT 24
Finished Jul 01 10:52:37 AM PDT 24
Peak memory 204772 kb
Host smart-96288686-ecbd-48ef-a633-08a60a04cf2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93571157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.93571157
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.994344129
Short name T207
Test name
Test status
Simulation time 2728508321 ps
CPU time 6.28 seconds
Started Jul 01 10:52:06 AM PDT 24
Finished Jul 01 10:52:15 AM PDT 24
Peak memory 213504 kb
Host smart-3be5aff8-13da-456a-80db-cda0890b256e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994344129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.994344129
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3732617035
Short name T287
Test name
Test status
Simulation time 872025933 ps
CPU time 2.07 seconds
Started Jul 01 10:52:04 AM PDT 24
Finished Jul 01 10:52:09 AM PDT 24
Peak memory 213312 kb
Host smart-177745f0-af6a-42ba-a1d1-2f259a1c7d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732617035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3732617035
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3708014591
Short name T204
Test name
Test status
Simulation time 1511832010 ps
CPU time 3.05 seconds
Started Jul 01 10:52:04 AM PDT 24
Finished Jul 01 10:52:10 AM PDT 24
Peak memory 205140 kb
Host smart-65dc8cb5-d446-42fe-8df0-e203186274e2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3708014591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.3708014591
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2509838551
Short name T47
Test name
Test status
Simulation time 575633917 ps
CPU time 1.3 seconds
Started Jul 01 10:52:08 AM PDT 24
Finished Jul 01 10:52:10 AM PDT 24
Peak memory 204908 kb
Host smart-f8a04744-5a11-4cd0-b0d8-bbd46589417e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509838551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2509838551
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1773722892
Short name T77
Test name
Test status
Simulation time 1035850007 ps
CPU time 3.73 seconds
Started Jul 01 10:52:05 AM PDT 24
Finished Jul 01 10:52:11 AM PDT 24
Peak memory 205148 kb
Host smart-8b0adcab-18e9-49ab-aac6-8e4f4b4f7f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773722892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1773722892
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2062936609
Short name T65
Test name
Test status
Simulation time 579063243 ps
CPU time 2.4 seconds
Started Jul 01 10:52:21 AM PDT 24
Finished Jul 01 10:52:25 AM PDT 24
Peak memory 237072 kb
Host smart-18782c86-5e51-4c7e-a1d3-f2161dac9b17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062936609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2062936609
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.2909654819
Short name T27
Test name
Test status
Simulation time 16180560829 ps
CPU time 22.66 seconds
Started Jul 01 10:52:06 AM PDT 24
Finished Jul 01 10:52:31 AM PDT 24
Peak memory 216872 kb
Host smart-bdb7265d-9bef-46b3-9629-e799b01014f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909654819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2909654819
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.4094225906
Short name T213
Test name
Test status
Simulation time 137957237 ps
CPU time 1.1 seconds
Started Jul 01 10:52:33 AM PDT 24
Finished Jul 01 10:52:35 AM PDT 24
Peak memory 204832 kb
Host smart-82185eaa-4505-486a-a098-079116cc875a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094225906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.4094225906
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.60033699
Short name T142
Test name
Test status
Simulation time 6934411818 ps
CPU time 3.87 seconds
Started Jul 01 10:52:43 AM PDT 24
Finished Jul 01 10:52:51 AM PDT 24
Peak memory 213372 kb
Host smart-3b7a4de5-916b-47fd-bb67-68cb99fba2f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60033699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.60033699
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.622274273
Short name T195
Test name
Test status
Simulation time 140591950 ps
CPU time 0.88 seconds
Started Jul 01 10:52:46 AM PDT 24
Finished Jul 01 10:52:50 AM PDT 24
Peak memory 204768 kb
Host smart-944174a6-bde0-4c0d-a0d1-3e574ec6369f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622274273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.622274273
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.1242820754
Short name T11
Test name
Test status
Simulation time 7567985754 ps
CPU time 2.11 seconds
Started Jul 01 10:52:49 AM PDT 24
Finished Jul 01 10:52:55 AM PDT 24
Peak memory 213296 kb
Host smart-c53d247f-7487-41e0-a37d-488d28930b89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242820754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1242820754
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2530066395
Short name T197
Test name
Test status
Simulation time 34829088 ps
CPU time 0.78 seconds
Started Jul 01 10:52:33 AM PDT 24
Finished Jul 01 10:52:35 AM PDT 24
Peak memory 204828 kb
Host smart-687083f3-3d13-4dbd-a9e3-b935bb856d73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530066395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2530066395
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.3892540933
Short name T171
Test name
Test status
Simulation time 14999021998 ps
CPU time 8.84 seconds
Started Jul 01 10:52:38 AM PDT 24
Finished Jul 01 10:52:49 AM PDT 24
Peak memory 213388 kb
Host smart-b8087b62-d13c-4a79-aae0-c4b7950c6b93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892540933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3892540933
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3558833412
Short name T131
Test name
Test status
Simulation time 107142387 ps
CPU time 0.78 seconds
Started Jul 01 10:52:41 AM PDT 24
Finished Jul 01 10:52:45 AM PDT 24
Peak memory 204872 kb
Host smart-cf40347f-50f2-4ed4-9ce5-b63426d567eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558833412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3558833412
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2044358826
Short name T181
Test name
Test status
Simulation time 50543436 ps
CPU time 0.87 seconds
Started Jul 01 10:52:43 AM PDT 24
Finished Jul 01 10:52:48 AM PDT 24
Peak memory 204876 kb
Host smart-1e4316cf-32a0-4186-a3a5-627f93e02e6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044358826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2044358826
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.561642247
Short name T59
Test name
Test status
Simulation time 9287978721 ps
CPU time 12.09 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:52:54 AM PDT 24
Peak memory 205192 kb
Host smart-8d39c13f-2422-411d-be3e-0820e92bcee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561642247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.561642247
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1598828421
Short name T42
Test name
Test status
Simulation time 113985668 ps
CPU time 0.95 seconds
Started Jul 01 10:52:40 AM PDT 24
Finished Jul 01 10:52:44 AM PDT 24
Peak memory 204876 kb
Host smart-9bab9b45-781b-4c6d-99f0-4648cf34f936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598828421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1598828421
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.3726022589
Short name T167
Test name
Test status
Simulation time 3929910094 ps
CPU time 12.28 seconds
Started Jul 01 10:52:32 AM PDT 24
Finished Jul 01 10:52:46 AM PDT 24
Peak memory 205160 kb
Host smart-e6ae5c8f-7c03-4451-bbfb-809bc9fd6b5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726022589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3726022589
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1973309480
Short name T49
Test name
Test status
Simulation time 41650307 ps
CPU time 0.77 seconds
Started Jul 01 10:52:31 AM PDT 24
Finished Jul 01 10:52:33 AM PDT 24
Peak memory 204896 kb
Host smart-d6004783-9b02-46d9-8113-9c96d04ead62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973309480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1973309480
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3941670934
Short name T211
Test name
Test status
Simulation time 185570691 ps
CPU time 0.73 seconds
Started Jul 01 10:52:43 AM PDT 24
Finished Jul 01 10:52:47 AM PDT 24
Peak memory 204884 kb
Host smart-9d1b56b4-afed-478d-8b49-e4fdbd85f3fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941670934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3941670934
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.1268446844
Short name T36
Test name
Test status
Simulation time 1943598006 ps
CPU time 5.4 seconds
Started Jul 01 10:52:34 AM PDT 24
Finished Jul 01 10:52:40 AM PDT 24
Peak memory 213280 kb
Host smart-b3951152-5d28-4128-9449-8bcee01b3839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268446844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1268446844
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.4262056036
Short name T54
Test name
Test status
Simulation time 87307742 ps
CPU time 0.73 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:52:42 AM PDT 24
Peak memory 204768 kb
Host smart-98bf86ad-fe09-45ea-8f3c-0e23e40fe47a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262056036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.4262056036
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.3829666959
Short name T153
Test name
Test status
Simulation time 4598705106 ps
CPU time 14.51 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:52:56 AM PDT 24
Peak memory 213260 kb
Host smart-e4787b92-7797-49e1-b51a-5b5177919cdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829666959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3829666959
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2093241733
Short name T220
Test name
Test status
Simulation time 84251898 ps
CPU time 0.7 seconds
Started Jul 01 10:52:34 AM PDT 24
Finished Jul 01 10:52:35 AM PDT 24
Peak memory 204872 kb
Host smart-b474bd24-f7c1-40fe-b2e1-06311c689207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093241733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2093241733
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3387341120
Short name T21
Test name
Test status
Simulation time 4372388428 ps
CPU time 4.09 seconds
Started Jul 01 10:52:35 AM PDT 24
Finished Jul 01 10:52:40 AM PDT 24
Peak memory 205196 kb
Host smart-f216a4a9-4526-476d-9ed2-cf7278bba9be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387341120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3387341120
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1302251686
Short name T191
Test name
Test status
Simulation time 164288029 ps
CPU time 0.8 seconds
Started Jul 01 10:52:21 AM PDT 24
Finished Jul 01 10:52:24 AM PDT 24
Peak memory 204864 kb
Host smart-189eb18a-9146-4c80-9937-0a285e6e292b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302251686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1302251686
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2008579604
Short name T196
Test name
Test status
Simulation time 26416903067 ps
CPU time 56.99 seconds
Started Jul 01 10:52:07 AM PDT 24
Finished Jul 01 10:53:06 AM PDT 24
Peak memory 213484 kb
Host smart-48c57290-2542-4426-9ee9-29aa66dd9823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008579604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2008579604
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1565651251
Short name T272
Test name
Test status
Simulation time 895774203 ps
CPU time 2.25 seconds
Started Jul 01 10:52:23 AM PDT 24
Finished Jul 01 10:52:26 AM PDT 24
Peak memory 205224 kb
Host smart-7fdd9202-a436-424c-b843-6717d88c5e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565651251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1565651251
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2091168469
Short name T241
Test name
Test status
Simulation time 2305062010 ps
CPU time 3.04 seconds
Started Jul 01 10:52:15 AM PDT 24
Finished Jul 01 10:52:21 AM PDT 24
Peak memory 205224 kb
Host smart-99110535-a386-49ea-983d-25b16a7ba233
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2091168469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2091168469
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3959107397
Short name T1
Test name
Test status
Simulation time 413638416 ps
CPU time 1.61 seconds
Started Jul 01 10:52:14 AM PDT 24
Finished Jul 01 10:52:19 AM PDT 24
Peak memory 204872 kb
Host smart-6985aec3-0009-4e39-b31d-442287e02be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959107397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3959107397
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.314400273
Short name T264
Test name
Test status
Simulation time 15632370663 ps
CPU time 6.88 seconds
Started Jul 01 10:52:08 AM PDT 24
Finished Jul 01 10:52:17 AM PDT 24
Peak memory 213356 kb
Host smart-ff8dbafc-2515-4d9c-bfb3-84080ec48d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314400273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.314400273
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3165016203
Short name T3
Test name
Test status
Simulation time 279991855 ps
CPU time 1.16 seconds
Started Jul 01 10:52:09 AM PDT 24
Finished Jul 01 10:52:13 AM PDT 24
Peak memory 236428 kb
Host smart-c927be93-6b01-4225-b7ec-4668ed4fbd2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165016203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3165016203
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.178081710
Short name T6
Test name
Test status
Simulation time 5558176966 ps
CPU time 8.74 seconds
Started Jul 01 10:52:18 AM PDT 24
Finished Jul 01 10:52:29 AM PDT 24
Peak memory 205196 kb
Host smart-fc4eb22d-ea75-407f-a77e-7bad3b147ded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178081710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.178081710
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.773647829
Short name T215
Test name
Test status
Simulation time 78858664 ps
CPU time 0.88 seconds
Started Jul 01 10:52:38 AM PDT 24
Finished Jul 01 10:52:40 AM PDT 24
Peak memory 204888 kb
Host smart-f713cd5c-43c4-4f33-b946-7f7e14369910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773647829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.773647829
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.2276059766
Short name T147
Test name
Test status
Simulation time 8336076611 ps
CPU time 13.14 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:52:54 AM PDT 24
Peak memory 213180 kb
Host smart-349ae635-7197-450e-9d13-962cd40a9abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276059766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2276059766
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3893417312
Short name T283
Test name
Test status
Simulation time 121389768 ps
CPU time 0.73 seconds
Started Jul 01 10:52:50 AM PDT 24
Finished Jul 01 10:52:56 AM PDT 24
Peak memory 204904 kb
Host smart-0323110a-057d-48e8-a796-37d0f6f8e523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893417312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3893417312
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3279560481
Short name T274
Test name
Test status
Simulation time 72795499 ps
CPU time 0.83 seconds
Started Jul 01 10:52:43 AM PDT 24
Finished Jul 01 10:52:47 AM PDT 24
Peak memory 204872 kb
Host smart-e6a35102-a8da-4861-9d55-9e55ce93d368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279560481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3279560481
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.990512771
Short name T260
Test name
Test status
Simulation time 62481926 ps
CPU time 0.84 seconds
Started Jul 01 10:52:40 AM PDT 24
Finished Jul 01 10:52:44 AM PDT 24
Peak memory 204852 kb
Host smart-a3832d5d-8d25-481d-b483-c83c715f2e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990512771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.990512771
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.322274665
Short name T217
Test name
Test status
Simulation time 213094144 ps
CPU time 0.95 seconds
Started Jul 01 10:52:41 AM PDT 24
Finished Jul 01 10:52:45 AM PDT 24
Peak memory 204900 kb
Host smart-6f0b5376-0511-48a9-a18a-341d5ec411f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322274665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.322274665
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.3297708106
Short name T136
Test name
Test status
Simulation time 14196960105 ps
CPU time 39.6 seconds
Started Jul 01 10:52:37 AM PDT 24
Finished Jul 01 10:53:17 AM PDT 24
Peak memory 213328 kb
Host smart-a227eb9d-0d0b-4e66-b86a-ad8e7b88fc94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297708106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3297708106
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1967210319
Short name T226
Test name
Test status
Simulation time 97343438 ps
CPU time 0.8 seconds
Started Jul 01 10:52:38 AM PDT 24
Finished Jul 01 10:52:41 AM PDT 24
Peak memory 204904 kb
Host smart-acc69cc5-6fc4-48f6-a828-5ad5f5f0f689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967210319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1967210319
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.787560840
Short name T143
Test name
Test status
Simulation time 2222112654 ps
CPU time 2.81 seconds
Started Jul 01 10:52:38 AM PDT 24
Finished Jul 01 10:52:42 AM PDT 24
Peak memory 213304 kb
Host smart-bc74e09a-4e4e-4d2c-8ffd-e08c6a39d130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787560840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.787560840
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.951686
Short name T46
Test name
Test status
Simulation time 66528741 ps
CPU time 0.74 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:52:42 AM PDT 24
Peak memory 204876 kb
Host smart-efc0843f-cfa3-4b73-a463-33c608c6cfd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.951686
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.2524406669
Short name T133
Test name
Test status
Simulation time 2813550691 ps
CPU time 5.64 seconds
Started Jul 01 10:52:48 AM PDT 24
Finished Jul 01 10:52:56 AM PDT 24
Peak memory 213380 kb
Host smart-8435aac9-cea7-4691-a94d-af52bcd6dc98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524406669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.2524406669
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2201936455
Short name T234
Test name
Test status
Simulation time 162401838 ps
CPU time 0.74 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:52:42 AM PDT 24
Peak memory 204864 kb
Host smart-f7d96c1d-b435-4727-a3a5-b125ba35dbbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201936455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2201936455
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.2794316013
Short name T60
Test name
Test status
Simulation time 10507937678 ps
CPU time 8.91 seconds
Started Jul 01 10:52:38 AM PDT 24
Finished Jul 01 10:52:48 AM PDT 24
Peak memory 213400 kb
Host smart-71b6a6f9-47f3-407f-988d-2bf639687c6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794316013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2794316013
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2714994603
Short name T193
Test name
Test status
Simulation time 73079734 ps
CPU time 0.77 seconds
Started Jul 01 10:52:41 AM PDT 24
Finished Jul 01 10:52:45 AM PDT 24
Peak memory 204908 kb
Host smart-479c652f-8aaa-432c-b632-cba186cdc95f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714994603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2714994603
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.1692597785
Short name T12
Test name
Test status
Simulation time 7712607431 ps
CPU time 10.81 seconds
Started Jul 01 10:52:40 AM PDT 24
Finished Jul 01 10:52:54 AM PDT 24
Peak memory 213348 kb
Host smart-95885d82-d97d-4ace-a64c-22aa949a728f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692597785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1692597785
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1028660823
Short name T229
Test name
Test status
Simulation time 140460290 ps
CPU time 0.86 seconds
Started Jul 01 10:52:44 AM PDT 24
Finished Jul 01 10:52:48 AM PDT 24
Peak memory 204708 kb
Host smart-9679400b-b88a-4f5e-94b5-7952de8fce6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028660823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1028660823
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.1285038779
Short name T175
Test name
Test status
Simulation time 5726473596 ps
CPU time 16.11 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:52:58 AM PDT 24
Peak memory 213364 kb
Host smart-c079705a-2225-4a20-8644-9ea89c6ce864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285038779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.1285038779
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1157064366
Short name T284
Test name
Test status
Simulation time 96093150 ps
CPU time 0.77 seconds
Started Jul 01 10:52:14 AM PDT 24
Finished Jul 01 10:52:22 AM PDT 24
Peak memory 204884 kb
Host smart-c237fcdc-6479-4139-a044-2c778223d643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157064366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1157064366
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.508857476
Short name T277
Test name
Test status
Simulation time 27924396569 ps
CPU time 82.43 seconds
Started Jul 01 10:52:12 AM PDT 24
Finished Jul 01 10:53:37 AM PDT 24
Peak memory 213516 kb
Host smart-ab94b349-b6e6-4d8e-bc1a-e6751fcfaef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508857476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.508857476
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3286031601
Short name T262
Test name
Test status
Simulation time 4202704953 ps
CPU time 11.27 seconds
Started Jul 01 10:52:38 AM PDT 24
Finished Jul 01 10:52:52 AM PDT 24
Peak memory 213436 kb
Host smart-75eac3fd-5de4-4bbd-baf7-2e44de121587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286031601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3286031601
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.564767294
Short name T41
Test name
Test status
Simulation time 15020895277 ps
CPU time 12.6 seconds
Started Jul 01 10:52:36 AM PDT 24
Finished Jul 01 10:52:49 AM PDT 24
Peak memory 213384 kb
Host smart-8567abad-4850-41e4-a2e7-63338a906603
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564767294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.564767294
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1470592289
Short name T155
Test name
Test status
Simulation time 1225256773 ps
CPU time 1.27 seconds
Started Jul 01 10:52:08 AM PDT 24
Finished Jul 01 10:52:11 AM PDT 24
Peak memory 213388 kb
Host smart-cef6f5a0-130d-4cac-b04a-8a1bb385f4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470592289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1470592289
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.1880987931
Short name T61
Test name
Test status
Simulation time 2141875089 ps
CPU time 2.63 seconds
Started Jul 01 10:52:20 AM PDT 24
Finished Jul 01 10:52:25 AM PDT 24
Peak memory 213220 kb
Host smart-8c33646d-f3b5-454d-b709-5667a9254504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880987931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1880987931
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.782699764
Short name T37
Test name
Test status
Simulation time 57908650 ps
CPU time 0.8 seconds
Started Jul 01 10:52:10 AM PDT 24
Finished Jul 01 10:52:13 AM PDT 24
Peak memory 204888 kb
Host smart-97db2fce-1995-44e5-be45-e0d6d52b1967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782699764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.782699764
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1612080649
Short name T268
Test name
Test status
Simulation time 1648626701 ps
CPU time 1.45 seconds
Started Jul 01 10:52:10 AM PDT 24
Finished Jul 01 10:52:14 AM PDT 24
Peak memory 205304 kb
Host smart-ca583315-9da5-4077-a9ce-f0f19c5f981d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612080649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1612080649
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2684399955
Short name T89
Test name
Test status
Simulation time 1352672334 ps
CPU time 3.77 seconds
Started Jul 01 10:52:14 AM PDT 24
Finished Jul 01 10:52:21 AM PDT 24
Peak memory 213368 kb
Host smart-f5aa6af3-a029-4a82-aeab-2d4b013b2628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684399955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2684399955
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3651129355
Short name T247
Test name
Test status
Simulation time 1433872870 ps
CPU time 3.11 seconds
Started Jul 01 10:52:19 AM PDT 24
Finished Jul 01 10:52:25 AM PDT 24
Peak memory 213444 kb
Host smart-64ebcc7d-a1e8-4226-8b5d-5e950861b0fb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651129355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3651129355
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2250456968
Short name T198
Test name
Test status
Simulation time 1745475129 ps
CPU time 1.34 seconds
Started Jul 01 10:52:15 AM PDT 24
Finished Jul 01 10:52:19 AM PDT 24
Peak memory 213424 kb
Host smart-70e4cec5-0e00-4929-933e-aca02da96757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250456968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2250456968
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.4215369308
Short name T151
Test name
Test status
Simulation time 7115289093 ps
CPU time 11.78 seconds
Started Jul 01 10:52:12 AM PDT 24
Finished Jul 01 10:52:26 AM PDT 24
Peak memory 213352 kb
Host smart-df9a56d0-98f2-4420-8030-cc1b7a63a761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215369308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.4215369308
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.282633402
Short name T90
Test name
Test status
Simulation time 99922355 ps
CPU time 0.94 seconds
Started Jul 01 10:52:15 AM PDT 24
Finished Jul 01 10:52:18 AM PDT 24
Peak memory 204904 kb
Host smart-f3595d44-d4fc-4dba-bcd3-901392af3ae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282633402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.282633402
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3252456356
Short name T88
Test name
Test status
Simulation time 15845622214 ps
CPU time 22.65 seconds
Started Jul 01 10:52:16 AM PDT 24
Finished Jul 01 10:52:40 AM PDT 24
Peak memory 213556 kb
Host smart-22bbee7c-8720-40f4-93f3-fd9f155db230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252456356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3252456356
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2962650271
Short name T71
Test name
Test status
Simulation time 7869931097 ps
CPU time 24.54 seconds
Started Jul 01 10:52:15 AM PDT 24
Finished Jul 01 10:52:42 AM PDT 24
Peak memory 213520 kb
Host smart-18bfccf0-4c21-4a42-a888-4116a5f0e859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962650271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2962650271
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3499258494
Short name T212
Test name
Test status
Simulation time 2960827860 ps
CPU time 3.08 seconds
Started Jul 01 10:52:09 AM PDT 24
Finished Jul 01 10:52:14 AM PDT 24
Peak memory 213412 kb
Host smart-0dfad641-534f-4cfd-8bbd-78a33470d460
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3499258494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3499258494
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.952262042
Short name T231
Test name
Test status
Simulation time 1125431988 ps
CPU time 1.46 seconds
Started Jul 01 10:52:10 AM PDT 24
Finished Jul 01 10:52:13 AM PDT 24
Peak memory 205268 kb
Host smart-c4d8da4b-6f0e-4e60-a6fc-7ea26f4354d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952262042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.952262042
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1384703358
Short name T180
Test name
Test status
Simulation time 72829134 ps
CPU time 0.77 seconds
Started Jul 01 10:52:15 AM PDT 24
Finished Jul 01 10:52:18 AM PDT 24
Peak memory 205100 kb
Host smart-edd932c4-407b-4818-9a0f-db36a9fd3a04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384703358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1384703358
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.1056262115
Short name T270
Test name
Test status
Simulation time 14452464698 ps
CPU time 37.76 seconds
Started Jul 01 10:52:18 AM PDT 24
Finished Jul 01 10:52:57 AM PDT 24
Peak memory 213508 kb
Host smart-ee60af58-099c-4cda-8f4e-7449c2fa7992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056262115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1056262115
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3129569894
Short name T257
Test name
Test status
Simulation time 1195502402 ps
CPU time 2.75 seconds
Started Jul 01 10:52:15 AM PDT 24
Finished Jul 01 10:52:20 AM PDT 24
Peak memory 213444 kb
Host smart-741fa845-0cf0-4efc-9bcc-d2f5fdc61051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129569894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3129569894
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.187164710
Short name T52
Test name
Test status
Simulation time 7130178038 ps
CPU time 15.72 seconds
Started Jul 01 10:52:23 AM PDT 24
Finished Jul 01 10:52:40 AM PDT 24
Peak memory 213420 kb
Host smart-638b512b-fc2f-47bb-ae11-4cde40781190
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=187164710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.187164710
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.541337393
Short name T265
Test name
Test status
Simulation time 5811938164 ps
CPU time 4.84 seconds
Started Jul 01 10:52:26 AM PDT 24
Finished Jul 01 10:52:32 AM PDT 24
Peak memory 213444 kb
Host smart-e8de683f-4b52-442b-8d81-f1c53cc54a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541337393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.541337393
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.2610637125
Short name T177
Test name
Test status
Simulation time 6042128490 ps
CPU time 17.81 seconds
Started Jul 01 10:52:20 AM PDT 24
Finished Jul 01 10:52:40 AM PDT 24
Peak memory 213472 kb
Host smart-0bbcafa9-9c81-4afd-8003-c968dee475a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610637125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2610637125
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3788947888
Short name T210
Test name
Test status
Simulation time 114557020 ps
CPU time 0.75 seconds
Started Jul 01 10:52:14 AM PDT 24
Finished Jul 01 10:52:17 AM PDT 24
Peak memory 204892 kb
Host smart-6d976ced-3120-4a4d-bfad-365c2b62d0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788947888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3788947888
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.410398604
Short name T194
Test name
Test status
Simulation time 6940725709 ps
CPU time 17.53 seconds
Started Jul 01 10:52:14 AM PDT 24
Finished Jul 01 10:52:34 AM PDT 24
Peak memory 205304 kb
Host smart-00d108a2-6101-4431-9b30-c74b2bc98835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410398604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.410398604
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2549257883
Short name T135
Test name
Test status
Simulation time 3837225806 ps
CPU time 11.97 seconds
Started Jul 01 10:52:19 AM PDT 24
Finished Jul 01 10:52:34 AM PDT 24
Peak memory 205296 kb
Host smart-9f6409bd-8e81-4084-a2a8-bfdd921d357c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549257883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2549257883
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1451474672
Short name T45
Test name
Test status
Simulation time 1123652615 ps
CPU time 4.03 seconds
Started Jul 01 10:52:31 AM PDT 24
Finished Jul 01 10:52:36 AM PDT 24
Peak memory 205280 kb
Host smart-a0ec2a36-9d1c-49c6-b83d-cd9b8c13ae95
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1451474672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1451474672
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3344334624
Short name T13
Test name
Test status
Simulation time 3545587200 ps
CPU time 6.56 seconds
Started Jul 01 10:52:16 AM PDT 24
Finished Jul 01 10:52:24 AM PDT 24
Peak memory 205240 kb
Host smart-4ad9be45-1e9a-4dac-a132-90670f48eae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344334624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3344334624
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.473611334
Short name T149
Test name
Test status
Simulation time 14608476732 ps
CPU time 24.28 seconds
Started Jul 01 10:52:15 AM PDT 24
Finished Jul 01 10:52:42 AM PDT 24
Peak memory 213308 kb
Host smart-0ea124bd-9b35-4347-a22b-e1a817e291de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473611334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.473611334
Directory /workspace/9.rv_dm_stress_all/latest
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