Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	237284	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	605882	1		T7	3		T4	6		T8	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	550505	1		T7	7		T4	12		T5	6
values[0x0]	143487	1		T7	3		T4	9		T8	14
values[0x1]	149174	1		T7	9		T4	10		T8	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	178260	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	664906	1		T7	5		T4	9		T8	10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3090	1		T69	4		T60	4		T85	7
valid_sources[0x01]	3424	1		T84	1		T68	4		T69	2
valid_sources[0x02]	3002	1		T68	5		T69	5		T60	5
valid_sources[0x03]	3844	1		T68	14		T69	1		T60	6
valid_sources[0x04]	3596	1		T34	2		T91	1		T54	2
valid_sources[0x05]	3421	1		T33	1		T15	1		T68	7
valid_sources[0x06]	3538	1		T33	1		T157	2		T68	10
valid_sources[0x07]	3209	1		T12	1		T49	2		T68	11
valid_sources[0x08]	4558	1		T6	1		T157	2		T178	2
valid_sources[0x09]	3910	1		T91	1		T68	7		T69	3
valid_sources[0x0a]	2933	1		T91	1		T54	4		T15	1
valid_sources[0x0b]	2814	1		T12	3		T68	3		T69	4
valid_sources[0x0c]	3240	1		T32	4		T68	25		T69	2
valid_sources[0x0d]	3156	1		T5	1		T92	1		T54	1
valid_sources[0x0e]	2974	1		T92	5		T179	52		T24	2
valid_sources[0x0f]	3120	1		T6	1		T91	1		T54	2
valid_sources[0x10]	3273	1		T18	1		T68	1		T69	1
valid_sources[0x11]	2847	1		T6	1		T91	1		T15	2
valid_sources[0x12]	3113	1		T91	1		T49	1		T150	1
valid_sources[0x13]	2907	1		T54	2		T68	11		T60	3
valid_sources[0x14]	3355	1		T157	1		T15	1		T68	18
valid_sources[0x15]	3032	1		T54	1		T68	2		T69	6
valid_sources[0x16]	3298	1		T180	1		T57	1		T24	1
valid_sources[0x17]	3398	1		T15	1		T68	8		T69	3
valid_sources[0x18]	3017	1		T5	1		T54	2		T157	2
valid_sources[0x19]	3173	1		T6	1		T150	1		T68	6
valid_sources[0x1a]	2785	1		T54	1		T154	1		T180	1
valid_sources[0x1b]	2942	1		T181	1		T15	2		T49	1
valid_sources[0x1c]	3482	1		T24	1		T68	8		T69	1
valid_sources[0x1d]	2931	1		T54	1		T182	2		T150	1
valid_sources[0x1e]	3131	1		T44	1		T18	1		T68	16
valid_sources[0x1f]	3542	1		T60	5		T85	2		T86	2
valid_sources[0x20]	2706	1		T91	1		T68	26		T69	7
valid_sources[0x21]	3006	1		T7	19		T68	17		T60	4
valid_sources[0x22]	3475	1		T69	5		T60	11		T85	3
valid_sources[0x23]	3352	1		T54	1		T12	1		T44	1
valid_sources[0x24]	2975	1		T34	1		T11	1		T18	2
valid_sources[0x25]	2988	1		T5	3		T54	1		T15	1
valid_sources[0x26]	3153	1		T12	1		T150	1		T68	1
valid_sources[0x27]	3041	1		T15	1		T146	40		T68	7
valid_sources[0x28]	3272	1		T22	2		T69	1		T85	3
valid_sources[0x29]	3277	1		T4	1		T68	7		T69	6
valid_sources[0x2a]	3709	1		T4	1		T6	1		T13	34
valid_sources[0x2b]	3657	1		T68	3		T69	1		T60	4
valid_sources[0x2c]	3087	1		T69	4		T60	18		T85	3
valid_sources[0x2d]	3152	1		T34	3		T69	2		T60	16
valid_sources[0x2e]	2823	1		T183	6		T68	3		T69	1
valid_sources[0x2f]	3367	1		T154	2		T68	10		T69	1
valid_sources[0x30]	3148	1		T19	5		T69	10		T60	1
valid_sources[0x31]	3487	1		T6	1		T68	10		T69	5
valid_sources[0x32]	3497	1		T15	1		T158	1		T68	6
valid_sources[0x33]	4116	1		T91	2		T154	4		T43	1
valid_sources[0x34]	3748	1		T4	1		T33	1		T34	1
valid_sources[0x35]	3387	1		T4	2		T54	1		T43	2
valid_sources[0x36]	2781	1		T4	2		T54	2		T157	2
valid_sources[0x37]	2771	1		T11	1		T181	2		T68	8
valid_sources[0x38]	3395	1		T68	5		T69	1		T60	3
valid_sources[0x39]	12017	1		T68	2		T69	9		T60	2
valid_sources[0x3a]	3236	1		T5	3		T11	1		T184	1
valid_sources[0x3b]	3189	1		T6	1		T49	1		T68	2
valid_sources[0x3c]	4050	1		T54	1		T32	1		T24	1
valid_sources[0x3d]	3486	1		T49	1		T68	6		T69	3
valid_sources[0x3e]	3857	1		T156	2		T44	1		T184	1
valid_sources[0x3f]	2862	1		T156	1		T180	1		T44	1
valid_sources[0x40]	3165	1		T54	1		T69	5		T60	2
valid_sources[0x41]	2760	1		T68	16		T69	8		T60	5
valid_sources[0x42]	5968	1		T34	1		T91	2		T54	1
valid_sources[0x43]	3369	1		T180	1		T68	7		T69	4
valid_sources[0x44]	3996	1		T91	1		T185	3		T68	1
valid_sources[0x45]	3294	1		T68	4		T69	1		T60	5
valid_sources[0x46]	3324	1		T68	20		T69	3		T60	3
valid_sources[0x47]	2928	1		T54	1		T180	1		T15	1
valid_sources[0x48]	3707	1		T6	1		T54	1		T11	2
valid_sources[0x49]	3122	1		T54	1		T49	1		T68	28
valid_sources[0x4a]	3447	1		T4	2		T91	1		T24	3
valid_sources[0x4b]	3298	1		T91	1		T156	1		T49	1
valid_sources[0x4c]	3940	1		T68	17		T69	4		T60	4
valid_sources[0x4d]	3318	1		T91	1		T186	26		T24	1
valid_sources[0x4e]	2693	1		T4	1		T11	1		T68	2
valid_sources[0x4f]	2846	1		T156	1		T187	2		T68	9
valid_sources[0x50]	2728	1		T68	1		T69	7		T60	3
valid_sources[0x51]	3312	1		T54	1		T58	1		T68	5
valid_sources[0x52]	3107	1		T14	3		T22	1		T68	4
valid_sources[0x53]	3420	1		T5	1		T44	1		T24	4
valid_sources[0x54]	3054	1		T6	2		T54	1		T12	1
valid_sources[0x55]	3257	1		T68	8		T69	5		T60	1
valid_sources[0x56]	3452	1		T149	1		T60	2		T85	4
valid_sources[0x57]	2940	1		T11	1		T43	2		T68	6
valid_sources[0x58]	2748	1		T8	6		T54	1		T11	1
valid_sources[0x59]	3193	1		T34	1		T54	1		T156	1
valid_sources[0x5a]	2935	1		T4	1		T15	1		T150	1
valid_sources[0x5b]	3474	1		T5	2		T156	1		T68	6
valid_sources[0x5c]	3003	1		T156	1		T15	3		T60	4
valid_sources[0x5d]	3255	1		T149	18		T24	3		T68	5
valid_sources[0x5e]	3537	1		T150	1		T188	1		T24	1
valid_sources[0x5f]	2782	1		T91	1		T189	2		T68	12
valid_sources[0x60]	2927	1		T34	1		T58	1		T68	16
valid_sources[0x61]	5457	1		T34	1		T69	9		T60	3
valid_sources[0x62]	2973	1		T54	1		T189	1		T68	5
valid_sources[0x63]	3626	1		T54	1		T68	4		T69	2
valid_sources[0x64]	2948	1		T56	2		T68	9		T69	1
valid_sources[0x65]	3302	1		T4	1		T15	1		T68	4
valid_sources[0x66]	3250	1		T150	1		T69	2		T60	19
valid_sources[0x67]	3368	1		T54	1		T68	5		T60	4
valid_sources[0x68]	2733	1		T34	1		T54	1		T68	16
valid_sources[0x69]	3322	1		T33	1		T24	1		T68	1
valid_sources[0x6a]	3266	1		T54	1		T68	5		T69	4
valid_sources[0x6b]	3102	1		T54	3		T32	1		T22	1
valid_sources[0x6c]	3075	1		T91	1		T154	1		T12	1
valid_sources[0x6d]	3869	1		T149	3		T68	5		T69	4
valid_sources[0x6e]	4119	1		T22	2		T68	2		T69	2
valid_sources[0x6f]	2893	1		T12	2		T189	2		T24	2
valid_sources[0x70]	3075	1		T157	1		T68	9		T69	3
valid_sources[0x71]	3728	1		T91	1		T68	3		T69	6
valid_sources[0x72]	3591	1		T44	1		T68	1		T69	5
valid_sources[0x73]	2973	1		T25	1		T68	11		T69	3
valid_sources[0x74]	3148	1		T190	4		T68	2		T69	5
valid_sources[0x75]	3120	1		T54	1		T68	1		T69	2
valid_sources[0x76]	3392	1		T156	2		T68	7		T69	5
valid_sources[0x77]	2844	1		T16	1		T154	2		T68	14
valid_sources[0x78]	3205	1		T5	1		T185	4		T68	1
valid_sources[0x79]	3070	1		T68	10		T69	9		T60	9
valid_sources[0x7a]	3958	1		T156	3		T68	12		T69	2
valid_sources[0x7b]	3012	1		T54	1		T68	9		T69	4
valid_sources[0x7c]	2673	1		T68	12		T69	6		T60	1
valid_sources[0x7d]	2934	1		T68	1		T69	5		T60	3
valid_sources[0x7e]	4047	1		T68	26		T69	7		T60	4
valid_sources[0x7f]	3205	1		T178	1		T68	29		T69	2
valid_sources[0x80]	3004	1		T54	1		T156	1		T17	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

324156

1

T7

1

T4

4

T5

5

values[0x0]

all_enables

biggest_size

141423

1

T7

1

T4

2

T8

5

values[0x1]

all_enables

biggest_size

140303

1

T7

1

T8

1

T5

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5415	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	24460	1		T1	1		T2	1		T3	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	11387	1		T68	109		T69	60		T60	455
values[0x0]	9080	1		T1	1		T2	1		T3	2
values[0x1]	9408	1		T3	3		T27	1		T7	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4015	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	25860	1		T1	1		T2	1		T3	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	104	1		T62	1		T191	1		T192	1
valid_sources[0x01]	169	1		T193	1		T68	2		T103	1
valid_sources[0x02]	117	1		T38	6		T68	2		T88	2
valid_sources[0x03]	104	1		T68	2		T90	1		T98	1
valid_sources[0x04]	80	1		T31	1		T69	1		T60	8
valid_sources[0x05]	86	1		T10	5		T194	1		T68	1
valid_sources[0x06]	206	1		T195	1		T68	3		T60	1
valid_sources[0x07]	98	1		T13	1		T196	5		T193	1
valid_sources[0x08]	59	1		T197	1		T42	1		T198	1
valid_sources[0x09]	113	1		T199	1		T69	1		T60	27
valid_sources[0x0a]	90	1		T62	1		T200	1		T201	1
valid_sources[0x0b]	110	1		T35	1		T202	1		T203	1
valid_sources[0x0c]	89	1		T39	1		T68	1		T69	3
valid_sources[0x0d]	101	1		T204	1		T205	6		T69	3
valid_sources[0x0e]	85	1		T47	3		T185	1		T200	1
valid_sources[0x0f]	87	1		T206	1		T68	2		T82	1
valid_sources[0x10]	102	1		T62	2		T156	1		T207	1
valid_sources[0x11]	194	1		T60	76		T82	2		T87	1
valid_sources[0x12]	108	1		T21	1		T184	1		T68	1
valid_sources[0x13]	92	1		T208	1		T22	1		T200	1
valid_sources[0x14]	67	1		T82	3		T90	2		T209	1
valid_sources[0x15]	113	1		T210	1		T68	3		T82	1
valid_sources[0x16]	99	1		T31	1		T30	1		T191	1
valid_sources[0x17]	116	1		T47	2		T151	12		T88	2
valid_sources[0x18]	72	1		T211	1		T42	1		T47	1
valid_sources[0x19]	145	1		T39	1		T130	1		T212	1
valid_sources[0x1a]	111	1		T143	3		T42	1		T68	2
valid_sources[0x1b]	105	1		T67	1		T185	1		T68	5
valid_sources[0x1c]	97	1		T213	1		T214	2		T68	9
valid_sources[0x1d]	125	1		T68	4		T88	1		T89	1
valid_sources[0x1e]	126	1		T5	9		T156	1		T68	6
valid_sources[0x1f]	210	1		T69	3		T82	1		T90	4
valid_sources[0x20]	115	1		T39	1		T194	1		T69	1
valid_sources[0x21]	99	1		T66	1		T215	2		T85	1
valid_sources[0x22]	43	1		T216	1		T90	1		T209	3
valid_sources[0x23]	119	1		T206	1		T68	1		T82	1
valid_sources[0x24]	109	1		T66	2		T68	2		T60	16
valid_sources[0x25]	105	1		T49	8		T159	1		T183	1
valid_sources[0x26]	88	1		T39	1		T22	1		T217	2
valid_sources[0x27]	192	1		T2	1		T39	1		T211	1
valid_sources[0x28]	102	1		T69	1		T60	5		T82	1
valid_sources[0x29]	82	1		T62	1		T218	1		T46	1
valid_sources[0x2a]	100	1		T54	1		T192	1		T68	1
valid_sources[0x2b]	155	1		T13	1		T217	1		T68	2
valid_sources[0x2c]	80	1		T26	1		T191	1		T69	1
valid_sources[0x2d]	127	1		T39	3		T219	1		T68	2
valid_sources[0x2e]	102	1		T6	1		T211	1		T156	1
valid_sources[0x2f]	71	1		T211	2		T46	1		T220	1
valid_sources[0x30]	78	1		T62	1		T221	1		T222	1
valid_sources[0x31]	71	1		T223	1		T192	2		T60	9
valid_sources[0x32]	128	1		T200	1		T68	1		T82	2
valid_sources[0x33]	104	1		T146	6		T185	1		T68	1
valid_sources[0x34]	231	1		T91	3		T76	1		T45	6
valid_sources[0x35]	99	1		T68	3		T69	3		T89	1
valid_sources[0x36]	125	1		T35	1		T69	6		T82	2
valid_sources[0x37]	94	1		T217	2		T183	1		T69	2
valid_sources[0x38]	106	1		T68	1		T60	23		T82	1
valid_sources[0x39]	126	1		T52	1		T73	7		T68	1
valid_sources[0x3a]	98	1		T27	1		T224	14		T225	1
valid_sources[0x3b]	80	1		T56	1		T88	1		T90	3
valid_sources[0x3c]	89	1		T68	1		T82	1		T88	2
valid_sources[0x3d]	97	1		T226	1		T203	2		T68	2
valid_sources[0x3e]	124	1		T149	4		T206	1		T150	6
valid_sources[0x3f]	105	1		T92	1		T137	1		T68	5
valid_sources[0x40]	86	1		T44	1		T227	1		T69	1
valid_sources[0x41]	81	1		T39	1		T228	1		T68	4
valid_sources[0x42]	186	1		T39	2		T154	2		T18	8
valid_sources[0x43]	137	1		T76	1		T13	1		T90	1
valid_sources[0x44]	109	1		T39	1		T229	1		T140	9
valid_sources[0x45]	105	1		T92	1		T230	1		T197	1
valid_sources[0x46]	101	1		T68	1		T89	3		T103	1
valid_sources[0x47]	92	1		T148	1		T231	6		T232	1
valid_sources[0x48]	90	1		T37	1		T62	1		T33	1
valid_sources[0x49]	179	1		T68	2		T60	67		T86	2
valid_sources[0x4a]	82	1		T67	1		T82	4		T85	2
valid_sources[0x4b]	111	1		T83	3		T137	2		T233	1
valid_sources[0x4c]	217	1		T39	1		T136	1		T234	4
valid_sources[0x4d]	99	1		T68	6		T69	3		T82	4
valid_sources[0x4e]	125	1		T62	1		T215	1		T22	1
valid_sources[0x4f]	90	1		T8	6		T11	2		T193	1
valid_sources[0x50]	105	1		T26	1		T12	1		T68	4
valid_sources[0x51]	88	1		T11	1		T235	1		T208	1
valid_sources[0x52]	76	1		T76	1		T42	1		T68	1
valid_sources[0x53]	96	1		T236	1		T68	1		T69	8
valid_sources[0x54]	115	1		T59	5		T237	1		T68	1
valid_sources[0x55]	432	1		T71	1		T143	1		T156	1
valid_sources[0x56]	143	1		T131	4		T76	1		T47	1
valid_sources[0x57]	90	1		T217	1		T68	1		T69	1
valid_sources[0x58]	139	1		T6	1		T194	1		T68	1
valid_sources[0x59]	88	1		T238	19		T239	1		T69	2
valid_sources[0x5a]	142	1		T82	1		T103	2		T99	1
valid_sources[0x5b]	104	1		T39	1		T240	1		T206	1
valid_sources[0x5c]	301	1		T35	6		T241	2		T180	1
valid_sources[0x5d]	98	1		T242	1		T243	8		T69	2
valid_sources[0x5e]	132	1		T136	3		T191	2		T68	2
valid_sources[0x5f]	230	1		T138	1		T47	1		T69	1
valid_sources[0x60]	99	1		T92	3		T212	3		T215	1
valid_sources[0x61]	76	1		T12	2		T47	1		T69	2
valid_sources[0x62]	112	1		T92	1		T212	1		T244	1
valid_sources[0x63]	84	1		T78	1		T22	2		T88	1
valid_sources[0x64]	161	1		T241	2		T245	2		T181	1
valid_sources[0x65]	82	1		T199	2		T68	2		T69	4
valid_sources[0x66]	94	1		T13	1		T57	1		T82	5
valid_sources[0x67]	82	1		T200	1		T194	1		T68	1
valid_sources[0x68]	67	1		T246	1		T68	1		T69	1
valid_sources[0x69]	112	1		T191	1		T12	3		T247	1
valid_sources[0x6a]	96	1		T62	1		T32	6		T44	1
valid_sources[0x6b]	96	1		T76	1		T187	1		T68	2
valid_sources[0x6c]	151	1		T75	1		T85	1		T90	4
valid_sources[0x6d]	106	1		T6	1		T92	1		T248	5
valid_sources[0x6e]	155	1		T188	1		T24	1		T249	3
valid_sources[0x6f]	108	1		T46	1		T68	2		T69	3
valid_sources[0x70]	95	1		T66	2		T12	1		T250	1
valid_sources[0x71]	105	1		T7	1		T67	1		T203	1
valid_sources[0x72]	58	1		T198	1		T68	2		T69	1
valid_sources[0x73]	82	1		T251	1		T47	1		T69	1
valid_sources[0x74]	187	1		T245	1		T68	2		T60	64
valid_sources[0x75]	154	1		T215	1		T237	1		T69	2
valid_sources[0x76]	203	1		T252	1		T185	1		T253	14
valid_sources[0x77]	91	1		T77	1		T68	10		T69	1
valid_sources[0x78]	72	1		T6	2		T254	1		T68	2
valid_sources[0x79]	115	1		T68	1		T82	1		T86	6
valid_sources[0x7a]	129	1		T1	1		T211	5		T255	1
valid_sources[0x7b]	133	1		T256	5		T148	2		T237	3
valid_sources[0x7c]	90	1		T46	1		T257	3		T69	1
valid_sources[0x7d]	199	1		T198	1		T68	4		T82	2
valid_sources[0x7e]	166	1		T185	1		T237	2		T68	1
valid_sources[0x7f]	77	1		T7	1		T258	1		T222	1
valid_sources[0x80]	86	1		T237	1		T68	6		T88	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8006

1

T68

101

T69

56

T60

435

values[0x0]

all_enables

biggest_size

8343

1

T1

1

T2

1

T3

2

values[0x1]

all_enables

biggest_size

8111

1

T3

3

T27

1

T7

3