Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	290610	1		T7	16		T4	25		T8	16
full_word	608078	1		T7	3		T4	6		T8	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	898378	1		T7	19		T4	31		T8	22
auto[TlIntgErrCmd]	107	1		T88	7		T89	8		T135	4
auto[TlIntgErrData]	104	1		T88	10		T89	7		T135	3
auto[TlIntgErrBoth]	99	1		T88	3		T89	5		T135	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	553069	1		T7	7		T4	12		T5	6
auto[1]	345619	1		T7	12		T4	19		T8	22

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	228501	1		T7	6		T4	8		T5	1
auto[TlIntgErrNone]	partial	auto[1]	61821	1		T7	10		T4	17		T8	16
auto[TlIntgErrNone]	full_word	auto[0]	324430	1		T7	1		T4	4		T5	5
auto[TlIntgErrNone]	full_word	auto[1]	283626	1		T7	2		T4	2		T8	6
auto[TlIntgErrCmd]	partial	auto[0]	52	1		T88	4		T89	5		T135	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T88	3		T89	2		T135	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T168	1		T169	1		T170	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T89	1		T171	1		T166	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T88	3		T89	3		T135	1
auto[TlIntgErrData]	partial	auto[1]	53	1		T88	6		T89	3		T135	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T163	1		T168	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1		T88	1		T89	1		T172	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T88	3		T89	3		T135	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1		T89	2		T163	3		T172	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T135	1		T173	1		T174	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T135	1		T168	1		T175	1