Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	125898200	18277	0	0
late_debug_enable_rd_A	125898200	4873	0	0
late_debug_enable_regwen_rd_A	125898200	3850	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125898200	18277	0	0
T60	173214	1081	0	0
T68	94329	197	0	0
T69	5713	56	0	0
T82	5061	629	0	0
T85	39089	19	0	0
T86	6864	489	0	0
T87	140564	30	0	0
T88	153477	4	0	0
T89	83244	3	0	0
T90	47802	184	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125898200	4873	0	0
T85	39089	4	0	0
T87	140564	27	0	0
T95	37890	9	0	0
T98	42366	55	0	0
T100	23376	20	0	0
T104	323549	49	0	0
T129	418582	1073	0	0
T132	24257	10	0	0
T133	19728	47	0	0
T134	31220	14	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125898200	3850	0	0
T85	39089	12	0	0
T87	140564	25	0	0
T95	37890	5	0	0
T98	42366	47	0	0
T100	23376	39	0	0
T104	323549	39	0	0
T129	418582	1002	0	0
T132	24257	16	0	0
T133	19728	61	0	0
T134	31220	5	0	0