Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	75.00						75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	57617902	5777902	0	0
MemTLResponseWithoutDebugIsError_A	57617902	9	0	0
NdmResetAckNeedsDebug_A	57617902	0	0	0
SbaTLRequestNeedsDebug_A	57617902	16354	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57617902	5777902	0	0
T4	374043	88159	0	0
T5	0	65879	0	0
T6	0	42878	0	0
T7	50857	6929	0	0
T8	190607	66674	0	0
T9	85747	49737	0	0
T25	0	3694	0	0
T28	171221	0	0	0
T29	7660	0	0	0
T33	0	45203	0	0
T34	0	3924	0	0
T35	0	58707	0	0
T36	12243	0	0	0
T37	153876	0	0	0
T38	4392	0	0	0
T39	5441	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57617902	9	0	0
T15	297707	0	0	0
T40	4833	7	0	0
T41	0	2	0	0
T42	395673	0	0	0
T43	59363	0	0	0
T44	433638	0	0	0
T45	110039	0	0	0
T46	10614	0	0	0
T47	3148	0	0	0
T48	24338	0	0	0
T49	421192	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57617902	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57617902	16354	0	0
T1	43055	60	0	0
T2	409463	14	0	0
T3	85854	19	0	0
T4	374043	0	0	0
T7	50857	0	0	0
T9	85747	0	0	0
T27	102116	377	0	0
T28	0	2507	0	0
T31	0	49	0	0
T36	12243	0	0	0
T37	153876	27	0	0
T38	4392	0	0	0
T50	0	73	0	0
T51	0	62	0	0
T52	0	53	0	0