Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9595473 9594151 0 0
selKnown1 64492228 64490902 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9595473 9594151 0 0
T1 14900 14898 0 0
T2 17375 17373 0 0
T3 38806 38802 0 0
T4 26258 26254 0 0
T5 0 20 0 0
T6 0 4 0 0
T7 28879 28875 0 0
T8 0 8 0 0
T9 12514 12510 0 0
T27 274897 274893 0 0
T28 2 0 0 0
T29 2 0 0 0
T30 0 9 0 0
T31 0 2 0 0
T34 0 12 0 0
T35 0 7 0 0
T36 264 260 0 0
T37 33765 33761 0 0
T38 461 457 0 0
T66 0 12 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 64492228 64490902 0 0
T1 50505 50503 0 0
T2 418150 418148 0 0
T3 105262 105258 0 0
T4 387167 387163 0 0
T5 0 6 0 0
T6 0 4 0 0
T7 65297 65293 0 0
T8 0 8 0 0
T9 92005 92001 0 0
T27 239565 239562 0 0
T28 2 0 0 0
T29 2 0 0 0
T31 0 2 0 0
T34 0 4 0 0
T35 0 14 0 0
T36 12376 12372 0 0
T37 170759 170756 0 0
T38 4623 4619 0 0
T66 0 12 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2720403 2720182 0 0
selKnown1 57617902 57617679 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2720403 2720182 0 0
T1 7450 7449 0 0
T2 8687 8686 0 0
T3 19398 19397 0 0
T4 13118 13117 0 0
T7 14434 14433 0 0
T9 6256 6255 0 0
T27 137447 137446 0 0
T36 131 130 0 0
T37 16881 16880 0 0
T38 229 228 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 57617902 57617679 0 0
T1 43055 43054 0 0
T2 409463 409462 0 0
T3 85854 85853 0 0
T4 374043 374042 0 0
T7 50857 50856 0 0
T9 85747 85746 0 0
T27 102116 102116 0 0
T36 12243 12242 0 0
T37 153876 153876 0 0
T38 4392 4391 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 724 503 0 0
selKnown1 581 358 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 724 503 0 0
T3 5 4 0 0
T4 8 7 0 0
T5 0 10 0 0
T6 0 2 0 0
T7 5 4 0 0
T8 0 4 0 0
T9 1 0 0 0
T27 1 0 0 0
T28 1 0 0 0
T29 1 0 0 0
T31 0 1 0 0
T34 0 2 0 0
T35 0 7 0 0
T36 1 0 0 0
T37 1 0 0 0
T38 1 0 0 0
T66 0 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 581 358 0 0
T3 5 4 0 0
T4 3 2 0 0
T5 0 3 0 0
T6 0 2 0 0
T7 3 2 0 0
T8 0 4 0 0
T9 1 0 0 0
T27 1 0 0 0
T28 1 0 0 0
T29 1 0 0 0
T31 0 1 0 0
T34 0 2 0 0
T35 0 7 0 0
T36 1 0 0 0
T37 1 0 0 0
T38 1 0 0 0
T66 0 6 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6872289 6871848 0 0
selKnown1 6872085 6871646 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6872289 6871848 0 0
T1 7450 7449 0 0
T2 8688 8687 0 0
T3 19398 19397 0 0
T4 13119 13118 0 0
T7 14435 14434 0 0
T9 6256 6255 0 0
T27 137448 137447 0 0
T36 131 130 0 0
T37 16882 16881 0 0
T38 230 229 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6872085 6871646 0 0
T1 7450 7449 0 0
T2 8687 8686 0 0
T3 19398 19397 0 0
T4 13118 13117 0 0
T7 14434 14433 0 0
T9 6256 6255 0 0
T27 137447 137446 0 0
T36 131 130 0 0
T37 16881 16880 0 0
T38 229 228 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2057 1618 0 0
selKnown1 1660 1219 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2057 1618 0 0
T3 5 4 0 0
T4 13 12 0 0
T5 0 10 0 0
T6 0 2 0 0
T7 5 4 0 0
T8 0 4 0 0
T9 1 0 0 0
T27 1 0 0 0
T28 1 0 0 0
T29 1 0 0 0
T30 0 9 0 0
T31 0 1 0 0
T34 0 10 0 0
T36 1 0 0 0
T37 1 0 0 0
T38 1 0 0 0
T66 0 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1660 1219 0 0
T3 5 4 0 0
T4 3 2 0 0
T5 0 3 0 0
T6 0 2 0 0
T7 3 2 0 0
T8 0 4 0 0
T9 1 0 0 0
T27 1 0 0 0
T28 1 0 0 0
T29 1 0 0 0
T31 0 1 0 0
T34 0 2 0 0
T35 0 7 0 0
T36 1 0 0 0
T37 1 0 0 0
T38 1 0 0 0
T66 0 6 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%