SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
82.66 | 98.04 | 77.78 | 100.00 | 87.50 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1338 | 1338 | 0 | 0 |
OutputsKnown_A | 345707412 | 345476052 | 0 | 0 |
gen_flops.OutputDelay_A | 172853706 | 172732797 | 0 | 2007 |
gen_no_flops.OutputDelay_A | 172853706 | 172738026 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1338 | 1338 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T9 | 6 | 6 | 0 | 0 |
T27 | 6 | 6 | 0 | 0 |
T36 | 6 | 6 | 0 | 0 |
T37 | 6 | 6 | 0 | 0 |
T38 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 345707412 | 345476052 | 0 | 0 |
T1 | 258330 | 257832 | 0 | 0 |
T2 | 2456778 | 2456406 | 0 | 0 |
T3 | 515124 | 513018 | 0 | 0 |
T4 | 2244258 | 2243310 | 0 | 0 |
T7 | 305142 | 303930 | 0 | 0 |
T9 | 514482 | 514164 | 0 | 0 |
T27 | 612696 | 612660 | 0 | 0 |
T36 | 73458 | 73032 | 0 | 0 |
T37 | 923256 | 923226 | 0 | 0 |
T38 | 26352 | 25782 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 172853706 | 172732797 | 0 | 2007 |
T1 | 129165 | 128907 | 0 | 9 |
T2 | 1228389 | 1228194 | 0 | 9 |
T3 | 257562 | 256464 | 0 | 9 |
T4 | 1122129 | 1121628 | 0 | 9 |
T7 | 152571 | 151938 | 0 | 9 |
T9 | 257241 | 257073 | 0 | 9 |
T27 | 306348 | 306327 | 0 | 9 |
T36 | 36729 | 36507 | 0 | 9 |
T37 | 461628 | 461610 | 0 | 9 |
T38 | 13176 | 12882 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 172853706 | 172738026 | 0 | 0 |
T1 | 129165 | 128916 | 0 | 0 |
T2 | 1228389 | 1228203 | 0 | 0 |
T3 | 257562 | 256509 | 0 | 0 |
T4 | 1122129 | 1121655 | 0 | 0 |
T7 | 152571 | 151965 | 0 | 0 |
T9 | 257241 | 257082 | 0 | 0 |
T27 | 306348 | 306330 | 0 | 0 |
T36 | 36729 | 36516 | 0 | 0 |
T37 | 461628 | 461613 | 0 | 0 |
T38 | 13176 | 12891 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 223 | 223 | 0 | 0 |
OutputsKnown_A | 57617902 | 57579342 | 0 | 0 |
gen_flops.OutputDelay_A | 57617902 | 57577599 | 0 | 669 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223 | 223 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57617902 | 57579342 | 0 | 0 |
T1 | 43055 | 42972 | 0 | 0 |
T2 | 409463 | 409401 | 0 | 0 |
T3 | 85854 | 85503 | 0 | 0 |
T4 | 374043 | 373885 | 0 | 0 |
T7 | 50857 | 50655 | 0 | 0 |
T9 | 85747 | 85694 | 0 | 0 |
T27 | 102116 | 102110 | 0 | 0 |
T36 | 12243 | 12172 | 0 | 0 |
T37 | 153876 | 153871 | 0 | 0 |
T38 | 4392 | 4297 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57617902 | 57577599 | 0 | 669 |
T1 | 43055 | 42969 | 0 | 3 |
T2 | 409463 | 409398 | 0 | 3 |
T3 | 85854 | 85488 | 0 | 3 |
T4 | 374043 | 373876 | 0 | 3 |
T7 | 50857 | 50646 | 0 | 3 |
T9 | 85747 | 85691 | 0 | 3 |
T27 | 102116 | 102109 | 0 | 3 |
T36 | 12243 | 12169 | 0 | 3 |
T37 | 153876 | 153870 | 0 | 3 |
T38 | 4392 | 4294 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 223 | 223 | 0 | 0 |
OutputsKnown_A | 57617902 | 57579342 | 0 | 0 |
gen_flops.OutputDelay_A | 57617902 | 57577599 | 0 | 669 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223 | 223 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57617902 | 57579342 | 0 | 0 |
T1 | 43055 | 42972 | 0 | 0 |
T2 | 409463 | 409401 | 0 | 0 |
T3 | 85854 | 85503 | 0 | 0 |
T4 | 374043 | 373885 | 0 | 0 |
T7 | 50857 | 50655 | 0 | 0 |
T9 | 85747 | 85694 | 0 | 0 |
T27 | 102116 | 102110 | 0 | 0 |
T36 | 12243 | 12172 | 0 | 0 |
T37 | 153876 | 153871 | 0 | 0 |
T38 | 4392 | 4297 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57617902 | 57577599 | 0 | 669 |
T1 | 43055 | 42969 | 0 | 3 |
T2 | 409463 | 409398 | 0 | 3 |
T3 | 85854 | 85488 | 0 | 3 |
T4 | 374043 | 373876 | 0 | 3 |
T7 | 50857 | 50646 | 0 | 3 |
T9 | 85747 | 85691 | 0 | 3 |
T27 | 102116 | 102109 | 0 | 3 |
T36 | 12243 | 12169 | 0 | 3 |
T37 | 153876 | 153870 | 0 | 3 |
T38 | 4392 | 4294 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 223 | 223 | 0 | 0 |
OutputsKnown_A | 57617902 | 57579342 | 0 | 0 |
gen_no_flops.OutputDelay_A | 57617902 | 57579342 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223 | 223 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57617902 | 57579342 | 0 | 0 |
T1 | 43055 | 42972 | 0 | 0 |
T2 | 409463 | 409401 | 0 | 0 |
T3 | 85854 | 85503 | 0 | 0 |
T4 | 374043 | 373885 | 0 | 0 |
T7 | 50857 | 50655 | 0 | 0 |
T9 | 85747 | 85694 | 0 | 0 |
T27 | 102116 | 102110 | 0 | 0 |
T36 | 12243 | 12172 | 0 | 0 |
T37 | 153876 | 153871 | 0 | 0 |
T38 | 4392 | 4297 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57617902 | 57579342 | 0 | 0 |
T1 | 43055 | 42972 | 0 | 0 |
T2 | 409463 | 409401 | 0 | 0 |
T3 | 85854 | 85503 | 0 | 0 |
T4 | 374043 | 373885 | 0 | 0 |
T7 | 50857 | 50655 | 0 | 0 |
T9 | 85747 | 85694 | 0 | 0 |
T27 | 102116 | 102110 | 0 | 0 |
T36 | 12243 | 12172 | 0 | 0 |
T37 | 153876 | 153871 | 0 | 0 |
T38 | 4392 | 4297 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 223 | 223 | 0 | 0 |
OutputsKnown_A | 57617902 | 57579342 | 0 | 0 |
gen_flops.OutputDelay_A | 57617902 | 57577599 | 0 | 669 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223 | 223 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57617902 | 57579342 | 0 | 0 |
T1 | 43055 | 42972 | 0 | 0 |
T2 | 409463 | 409401 | 0 | 0 |
T3 | 85854 | 85503 | 0 | 0 |
T4 | 374043 | 373885 | 0 | 0 |
T7 | 50857 | 50655 | 0 | 0 |
T9 | 85747 | 85694 | 0 | 0 |
T27 | 102116 | 102110 | 0 | 0 |
T36 | 12243 | 12172 | 0 | 0 |
T37 | 153876 | 153871 | 0 | 0 |
T38 | 4392 | 4297 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57617902 | 57577599 | 0 | 669 |
T1 | 43055 | 42969 | 0 | 3 |
T2 | 409463 | 409398 | 0 | 3 |
T3 | 85854 | 85488 | 0 | 3 |
T4 | 374043 | 373876 | 0 | 3 |
T7 | 50857 | 50646 | 0 | 3 |
T9 | 85747 | 85691 | 0 | 3 |
T27 | 102116 | 102109 | 0 | 3 |
T36 | 12243 | 12169 | 0 | 3 |
T37 | 153876 | 153870 | 0 | 3 |
T38 | 4392 | 4294 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 223 | 223 | 0 | 0 |
OutputsKnown_A | 57617902 | 57579342 | 0 | 0 |
gen_no_flops.OutputDelay_A | 57617902 | 57579342 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223 | 223 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57617902 | 57579342 | 0 | 0 |
T1 | 43055 | 42972 | 0 | 0 |
T2 | 409463 | 409401 | 0 | 0 |
T3 | 85854 | 85503 | 0 | 0 |
T4 | 374043 | 373885 | 0 | 0 |
T7 | 50857 | 50655 | 0 | 0 |
T9 | 85747 | 85694 | 0 | 0 |
T27 | 102116 | 102110 | 0 | 0 |
T36 | 12243 | 12172 | 0 | 0 |
T37 | 153876 | 153871 | 0 | 0 |
T38 | 4392 | 4297 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57617902 | 57579342 | 0 | 0 |
T1 | 43055 | 42972 | 0 | 0 |
T2 | 409463 | 409401 | 0 | 0 |
T3 | 85854 | 85503 | 0 | 0 |
T4 | 374043 | 373885 | 0 | 0 |
T7 | 50857 | 50655 | 0 | 0 |
T9 | 85747 | 85694 | 0 | 0 |
T27 | 102116 | 102110 | 0 | 0 |
T36 | 12243 | 12172 | 0 | 0 |
T37 | 153876 | 153871 | 0 | 0 |
T38 | 4392 | 4297 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 223 | 223 | 0 | 0 |
OutputsKnown_A | 57617902 | 57579342 | 0 | 0 |
gen_no_flops.OutputDelay_A | 57617902 | 57579342 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223 | 223 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57617902 | 57579342 | 0 | 0 |
T1 | 43055 | 42972 | 0 | 0 |
T2 | 409463 | 409401 | 0 | 0 |
T3 | 85854 | 85503 | 0 | 0 |
T4 | 374043 | 373885 | 0 | 0 |
T7 | 50857 | 50655 | 0 | 0 |
T9 | 85747 | 85694 | 0 | 0 |
T27 | 102116 | 102110 | 0 | 0 |
T36 | 12243 | 12172 | 0 | 0 |
T37 | 153876 | 153871 | 0 | 0 |
T38 | 4392 | 4297 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57617902 | 57579342 | 0 | 0 |
T1 | 43055 | 42972 | 0 | 0 |
T2 | 409463 | 409401 | 0 | 0 |
T3 | 85854 | 85503 | 0 | 0 |
T4 | 374043 | 373885 | 0 | 0 |
T7 | 50857 | 50655 | 0 | 0 |
T9 | 85747 | 85694 | 0 | 0 |
T27 | 102116 | 102110 | 0 | 0 |
T36 | 12243 | 12172 | 0 | 0 |
T37 | 153876 | 153871 | 0 | 0 |
T38 | 4392 | 4297 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |