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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.43 95.12 79.31 89.42 74.36 85.33 98.32 55.18


Total test records in report: 431
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T88 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.130145769 Jul 02 09:45:13 AM PDT 24 Jul 02 09:45:15 AM PDT 24 222606497 ps
T290 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.418028840 Jul 02 09:44:52 AM PDT 24 Jul 02 09:45:04 AM PDT 24 40081603374 ps
T291 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2142624855 Jul 02 09:44:32 AM PDT 24 Jul 02 09:44:34 AM PDT 24 1033192677 ps
T84 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1275509488 Jul 02 09:44:21 AM PDT 24 Jul 02 09:44:33 AM PDT 24 1269367410 ps
T292 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1230420629 Jul 02 09:44:48 AM PDT 24 Jul 02 09:44:52 AM PDT 24 2773836041 ps
T293 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1792674417 Jul 02 09:45:06 AM PDT 24 Jul 02 09:45:11 AM PDT 24 2396862903 ps
T294 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2528865515 Jul 02 09:44:55 AM PDT 24 Jul 02 09:44:57 AM PDT 24 1546287588 ps
T295 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2288661842 Jul 02 09:44:29 AM PDT 24 Jul 02 09:44:31 AM PDT 24 62324962 ps
T60 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4130780321 Jul 02 09:44:52 AM PDT 24 Jul 02 09:46:49 AM PDT 24 41281698383 ps
T296 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4285357954 Jul 02 09:44:29 AM PDT 24 Jul 02 09:44:31 AM PDT 24 232602841 ps
T94 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1271789330 Jul 02 09:44:38 AM PDT 24 Jul 02 09:44:57 AM PDT 24 2056297283 ps
T297 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1978284976 Jul 02 09:44:29 AM PDT 24 Jul 02 09:44:31 AM PDT 24 392549569 ps
T298 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.88980901 Jul 02 09:45:00 AM PDT 24 Jul 02 09:45:06 AM PDT 24 1738679940 ps
T119 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4126048990 Jul 02 09:45:04 AM PDT 24 Jul 02 09:45:25 AM PDT 24 5743085267 ps
T157 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1474852394 Jul 02 09:44:51 AM PDT 24 Jul 02 09:45:02 AM PDT 24 874953843 ps
T156 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1660939961 Jul 02 09:44:55 AM PDT 24 Jul 02 09:45:05 AM PDT 24 789267551 ps
T89 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4024838203 Jul 02 09:44:37 AM PDT 24 Jul 02 09:44:46 AM PDT 24 7691264324 ps
T120 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2028087533 Jul 02 09:45:11 AM PDT 24 Jul 02 09:45:18 AM PDT 24 273905748 ps
T299 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3777872276 Jul 02 09:44:46 AM PDT 24 Jul 02 09:44:47 AM PDT 24 442756866 ps
T300 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.47088503 Jul 02 09:44:44 AM PDT 24 Jul 02 09:44:47 AM PDT 24 1016006499 ps
T301 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.958575274 Jul 02 09:44:32 AM PDT 24 Jul 02 09:44:38 AM PDT 24 2634982752 ps
T302 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4003196385 Jul 02 09:44:46 AM PDT 24 Jul 02 09:45:00 AM PDT 24 17082678152 ps
T303 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2602438944 Jul 02 09:44:48 AM PDT 24 Jul 02 09:44:49 AM PDT 24 137027118 ps
T159 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.4223595310 Jul 02 09:45:06 AM PDT 24 Jul 02 09:45:25 AM PDT 24 1673387970 ps
T304 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3739497827 Jul 02 09:45:08 AM PDT 24 Jul 02 09:45:53 AM PDT 24 31363221040 ps
T90 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.561818905 Jul 02 09:44:22 AM PDT 24 Jul 02 09:44:30 AM PDT 24 2792912976 ps
T305 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3795402296 Jul 02 09:44:20 AM PDT 24 Jul 02 09:44:24 AM PDT 24 1056428148 ps
T306 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2149767840 Jul 02 09:44:53 AM PDT 24 Jul 02 09:44:57 AM PDT 24 172813816 ps
T307 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4049909176 Jul 02 09:44:22 AM PDT 24 Jul 02 09:44:26 AM PDT 24 3051599377 ps
T91 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2401635212 Jul 02 09:45:01 AM PDT 24 Jul 02 09:45:06 AM PDT 24 277043363 ps
T308 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.260351651 Jul 02 09:44:27 AM PDT 24 Jul 02 09:44:29 AM PDT 24 100961498 ps
T309 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2206183520 Jul 02 09:45:13 AM PDT 24 Jul 02 09:45:16 AM PDT 24 584842824 ps
T310 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.879526964 Jul 02 09:44:55 AM PDT 24 Jul 02 09:45:01 AM PDT 24 221662149 ps
T311 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1064624661 Jul 02 09:44:29 AM PDT 24 Jul 02 09:44:39 AM PDT 24 3273602286 ps
T114 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1561691792 Jul 02 09:45:00 AM PDT 24 Jul 02 09:45:08 AM PDT 24 1758839335 ps
T312 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.219077873 Jul 02 09:44:55 AM PDT 24 Jul 02 09:45:30 AM PDT 24 13524964781 ps
T313 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1217059779 Jul 02 09:45:07 AM PDT 24 Jul 02 09:45:13 AM PDT 24 1573148435 ps
T106 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2604484697 Jul 02 09:44:21 AM PDT 24 Jul 02 09:45:18 AM PDT 24 5738377967 ps
T314 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1994265753 Jul 02 09:44:38 AM PDT 24 Jul 02 09:45:23 AM PDT 24 15960567357 ps
T315 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1985595650 Jul 02 09:45:01 AM PDT 24 Jul 02 09:45:13 AM PDT 24 6149863797 ps
T316 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.284138253 Jul 02 09:45:09 AM PDT 24 Jul 02 09:45:16 AM PDT 24 599548865 ps
T317 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2635768239 Jul 02 09:44:50 AM PDT 24 Jul 02 09:44:52 AM PDT 24 872917199 ps
T318 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3180439127 Jul 02 09:44:46 AM PDT 24 Jul 02 09:45:15 AM PDT 24 683864053 ps
T107 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1282441743 Jul 02 09:45:17 AM PDT 24 Jul 02 09:45:19 AM PDT 24 124254504 ps
T115 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3290778798 Jul 02 09:44:45 AM PDT 24 Jul 02 09:44:54 AM PDT 24 632506770 ps
T319 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2834113712 Jul 02 09:44:55 AM PDT 24 Jul 02 09:44:57 AM PDT 24 112523415 ps
T320 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3991171358 Jul 02 09:45:10 AM PDT 24 Jul 02 09:45:36 AM PDT 24 18582308057 ps
T100 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3689303726 Jul 02 09:44:53 AM PDT 24 Jul 02 09:44:58 AM PDT 24 306121125 ps
T108 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2188624948 Jul 02 09:44:41 AM PDT 24 Jul 02 09:45:18 AM PDT 24 7025417902 ps
T321 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1079806868 Jul 02 09:44:24 AM PDT 24 Jul 02 09:44:25 AM PDT 24 595643513 ps
T322 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2582623414 Jul 02 09:44:26 AM PDT 24 Jul 02 09:44:27 AM PDT 24 187585086 ps
T109 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.695805138 Jul 02 09:44:30 AM PDT 24 Jul 02 09:45:24 AM PDT 24 1464755885 ps
T323 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.412518075 Jul 02 09:44:53 AM PDT 24 Jul 02 09:45:01 AM PDT 24 3258815480 ps
T101 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2947189266 Jul 02 09:44:44 AM PDT 24 Jul 02 09:44:46 AM PDT 24 145083549 ps
T324 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.826546509 Jul 02 09:44:42 AM PDT 24 Jul 02 09:45:04 AM PDT 24 38542990244 ps
T325 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.882327427 Jul 02 09:44:58 AM PDT 24 Jul 02 09:45:07 AM PDT 24 2133916071 ps
T116 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3491106719 Jul 02 09:44:58 AM PDT 24 Jul 02 09:45:06 AM PDT 24 942399401 ps
T326 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3605764645 Jul 02 09:44:29 AM PDT 24 Jul 02 09:44:32 AM PDT 24 111160008 ps
T327 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3665486089 Jul 02 09:44:59 AM PDT 24 Jul 02 09:45:04 AM PDT 24 2517300595 ps
T328 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.665757152 Jul 02 09:44:59 AM PDT 24 Jul 02 09:45:05 AM PDT 24 3292367775 ps
T329 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3971692303 Jul 02 09:44:58 AM PDT 24 Jul 02 09:45:00 AM PDT 24 992577609 ps
T330 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.896607252 Jul 02 09:44:41 AM PDT 24 Jul 02 09:44:44 AM PDT 24 625626018 ps
T110 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1288279122 Jul 02 09:45:05 AM PDT 24 Jul 02 09:45:07 AM PDT 24 90389620 ps
T331 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3205110621 Jul 02 09:44:20 AM PDT 24 Jul 02 09:44:22 AM PDT 24 251019389 ps
T332 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4014303684 Jul 02 09:44:51 AM PDT 24 Jul 02 09:44:58 AM PDT 24 783833811 ps
T333 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2426007237 Jul 02 09:45:02 AM PDT 24 Jul 02 09:45:05 AM PDT 24 162969639 ps
T334 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3256654045 Jul 02 09:44:20 AM PDT 24 Jul 02 09:44:22 AM PDT 24 118996317 ps
T164 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2189857732 Jul 02 09:45:08 AM PDT 24 Jul 02 09:45:18 AM PDT 24 641655755 ps
T160 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2064513862 Jul 02 09:45:11 AM PDT 24 Jul 02 09:45:29 AM PDT 24 2073670020 ps
T163 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2552130602 Jul 02 09:44:52 AM PDT 24 Jul 02 09:45:10 AM PDT 24 1937392606 ps
T335 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4106917060 Jul 02 09:45:01 AM PDT 24 Jul 02 09:45:05 AM PDT 24 85313816 ps
T158 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1022207690 Jul 02 09:45:06 AM PDT 24 Jul 02 09:45:37 AM PDT 24 5725504701 ps
T336 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2554390233 Jul 02 09:45:14 AM PDT 24 Jul 02 09:45:17 AM PDT 24 889466362 ps
T337 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2206812816 Jul 02 09:44:24 AM PDT 24 Jul 02 09:44:54 AM PDT 24 43526538545 ps
T338 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3810883169 Jul 02 09:45:08 AM PDT 24 Jul 02 09:45:13 AM PDT 24 229230320 ps
T96 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4077524717 Jul 02 09:44:33 AM PDT 24 Jul 02 09:44:49 AM PDT 24 20686072762 ps
T339 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.742698983 Jul 02 09:44:42 AM PDT 24 Jul 02 09:44:43 AM PDT 24 130261371 ps
T340 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3807934329 Jul 02 09:45:02 AM PDT 24 Jul 02 09:45:11 AM PDT 24 10188999664 ps
T341 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.653446037 Jul 02 09:44:36 AM PDT 24 Jul 02 09:45:03 AM PDT 24 14293598769 ps
T342 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3225578728 Jul 02 09:45:00 AM PDT 24 Jul 02 09:47:36 AM PDT 24 53244848218 ps
T343 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.900476464 Jul 02 09:44:53 AM PDT 24 Jul 02 09:45:02 AM PDT 24 5489451492 ps
T344 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2533541288 Jul 02 09:44:24 AM PDT 24 Jul 02 09:46:29 AM PDT 24 45020880934 ps
T345 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4281443892 Jul 02 09:44:37 AM PDT 24 Jul 02 09:44:42 AM PDT 24 136600708 ps
T346 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.812065480 Jul 02 09:45:02 AM PDT 24 Jul 02 09:45:13 AM PDT 24 1203275960 ps
T117 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1065002920 Jul 02 09:45:02 AM PDT 24 Jul 02 09:45:11 AM PDT 24 1058081759 ps
T112 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3078168193 Jul 02 09:45:07 AM PDT 24 Jul 02 09:45:10 AM PDT 24 124742615 ps
T347 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3925631454 Jul 02 09:44:56 AM PDT 24 Jul 02 09:46:43 AM PDT 24 58155538041 ps
T97 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3830239677 Jul 02 09:44:46 AM PDT 24 Jul 02 09:44:55 AM PDT 24 4300234761 ps
T348 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2340441569 Jul 02 09:45:05 AM PDT 24 Jul 02 09:45:10 AM PDT 24 1083823671 ps
T349 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2425215026 Jul 02 09:44:41 AM PDT 24 Jul 02 09:44:42 AM PDT 24 29684943 ps
T350 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1146056907 Jul 02 09:44:55 AM PDT 24 Jul 02 09:45:01 AM PDT 24 2120671009 ps
T351 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3797973011 Jul 02 09:44:52 AM PDT 24 Jul 02 09:45:51 AM PDT 24 53791151678 ps
T352 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3474672228 Jul 02 09:45:07 AM PDT 24 Jul 02 09:45:08 AM PDT 24 467871252 ps
T353 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3984158986 Jul 02 09:45:01 AM PDT 24 Jul 02 09:45:04 AM PDT 24 256070891 ps
T102 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3902863375 Jul 02 09:44:51 AM PDT 24 Jul 02 09:44:59 AM PDT 24 574954350 ps
T354 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.111654803 Jul 02 09:44:43 AM PDT 24 Jul 02 09:44:50 AM PDT 24 1120404379 ps
T355 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2669663736 Jul 02 09:44:57 AM PDT 24 Jul 02 09:45:02 AM PDT 24 1051642386 ps
T356 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.740480714 Jul 02 09:45:08 AM PDT 24 Jul 02 09:45:14 AM PDT 24 361303232 ps
T357 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3568647145 Jul 02 09:44:32 AM PDT 24 Jul 02 09:44:34 AM PDT 24 1124012006 ps
T358 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3950231133 Jul 02 09:44:42 AM PDT 24 Jul 02 09:45:41 AM PDT 24 21173688910 ps
T359 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3525734704 Jul 02 09:44:53 AM PDT 24 Jul 02 09:44:55 AM PDT 24 253836562 ps
T360 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.159945305 Jul 02 09:44:53 AM PDT 24 Jul 02 09:44:59 AM PDT 24 2094859853 ps
T361 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2557779258 Jul 02 09:44:29 AM PDT 24 Jul 02 09:44:47 AM PDT 24 5925338430 ps
T161 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2700743056 Jul 02 09:44:54 AM PDT 24 Jul 02 09:45:05 AM PDT 24 1368491429 ps
T362 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2111138490 Jul 02 09:44:45 AM PDT 24 Jul 02 09:44:46 AM PDT 24 247900534 ps
T98 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.590834501 Jul 02 09:44:29 AM PDT 24 Jul 02 09:44:35 AM PDT 24 4056656069 ps
T103 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3338072867 Jul 02 09:45:07 AM PDT 24 Jul 02 09:45:12 AM PDT 24 122436884 ps
T363 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4100919820 Jul 02 09:44:40 AM PDT 24 Jul 02 09:45:19 AM PDT 24 3686098338 ps
T113 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.98576834 Jul 02 09:44:24 AM PDT 24 Jul 02 09:44:26 AM PDT 24 147902154 ps
T364 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3375314589 Jul 02 09:45:00 AM PDT 24 Jul 02 09:45:06 AM PDT 24 1937377218 ps
T365 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3521288705 Jul 02 09:44:57 AM PDT 24 Jul 02 09:45:00 AM PDT 24 148877222 ps
T366 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.709163797 Jul 02 09:44:41 AM PDT 24 Jul 02 09:45:36 AM PDT 24 20052646461 ps
T367 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.797595041 Jul 02 09:45:07 AM PDT 24 Jul 02 09:45:11 AM PDT 24 266267563 ps
T368 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4154028632 Jul 02 09:44:46 AM PDT 24 Jul 02 09:44:59 AM PDT 24 4578100235 ps
T369 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3040054128 Jul 02 09:44:21 AM PDT 24 Jul 02 09:44:24 AM PDT 24 327879673 ps
T370 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.645634778 Jul 02 09:45:08 AM PDT 24 Jul 02 09:45:13 AM PDT 24 925564435 ps
T104 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3107033038 Jul 02 09:44:54 AM PDT 24 Jul 02 09:44:57 AM PDT 24 1122227425 ps
T162 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1208949105 Jul 02 09:45:04 AM PDT 24 Jul 02 09:45:22 AM PDT 24 1148499842 ps
T371 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.112109503 Jul 02 09:45:00 AM PDT 24 Jul 02 09:45:06 AM PDT 24 562159141 ps
T372 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2307496030 Jul 02 09:44:26 AM PDT 24 Jul 02 09:44:28 AM PDT 24 278175368 ps
T105 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4130204695 Jul 02 09:44:53 AM PDT 24 Jul 02 09:44:56 AM PDT 24 911920749 ps
T373 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.82776431 Jul 02 09:44:53 AM PDT 24 Jul 02 09:45:01 AM PDT 24 552763328 ps
T374 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.676118742 Jul 02 09:45:09 AM PDT 24 Jul 02 09:45:17 AM PDT 24 838984232 ps
T375 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.51609748 Jul 02 09:44:38 AM PDT 24 Jul 02 09:44:39 AM PDT 24 120129309 ps
T376 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1812298999 Jul 02 09:44:23 AM PDT 24 Jul 02 09:44:30 AM PDT 24 1126030235 ps
T377 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.427563403 Jul 02 09:44:51 AM PDT 24 Jul 02 09:44:53 AM PDT 24 1109158734 ps
T378 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.594060859 Jul 02 09:44:53 AM PDT 24 Jul 02 09:44:57 AM PDT 24 481205454 ps
T379 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1228908640 Jul 02 09:45:00 AM PDT 24 Jul 02 09:45:03 AM PDT 24 89733066 ps
T380 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2495635923 Jul 02 09:44:56 AM PDT 24 Jul 02 09:45:20 AM PDT 24 29370384810 ps
T381 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3888230084 Jul 02 09:45:04 AM PDT 24 Jul 02 09:45:17 AM PDT 24 1508718553 ps
T382 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.476299937 Jul 02 09:44:40 AM PDT 24 Jul 02 09:44:49 AM PDT 24 3063112901 ps
T383 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2090550936 Jul 02 09:45:06 AM PDT 24 Jul 02 09:45:08 AM PDT 24 203188933 ps
T384 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3880637412 Jul 02 09:44:22 AM PDT 24 Jul 02 09:44:55 AM PDT 24 34344807125 ps
T385 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2083088628 Jul 02 09:44:29 AM PDT 24 Jul 02 09:45:03 AM PDT 24 20220878139 ps
T386 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2352417412 Jul 02 09:45:09 AM PDT 24 Jul 02 09:45:20 AM PDT 24 5017846400 ps
T387 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1913467272 Jul 02 09:44:37 AM PDT 24 Jul 02 09:44:39 AM PDT 24 87204816 ps
T388 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1724318288 Jul 02 09:45:13 AM PDT 24 Jul 02 09:45:21 AM PDT 24 468677330 ps
T389 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.713402186 Jul 02 09:44:45 AM PDT 24 Jul 02 09:45:38 AM PDT 24 21100488022 ps
T390 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.241155959 Jul 02 09:44:28 AM PDT 24 Jul 02 09:44:39 AM PDT 24 1974519063 ps
T391 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.296630987 Jul 02 09:44:48 AM PDT 24 Jul 02 09:44:51 AM PDT 24 470284149 ps
T392 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1172520420 Jul 02 09:44:39 AM PDT 24 Jul 02 09:49:48 AM PDT 24 104922549214 ps
T393 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2197791542 Jul 02 09:44:34 AM PDT 24 Jul 02 09:44:38 AM PDT 24 169169740 ps
T394 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2040659835 Jul 02 09:44:33 AM PDT 24 Jul 02 09:45:06 AM PDT 24 11200896558 ps
T395 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1800341632 Jul 02 09:44:45 AM PDT 24 Jul 02 09:44:47 AM PDT 24 107268887 ps
T396 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2102295851 Jul 02 09:44:21 AM PDT 24 Jul 02 09:44:26 AM PDT 24 1087546052 ps
T397 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1142975337 Jul 02 09:45:01 AM PDT 24 Jul 02 09:45:05 AM PDT 24 2058784337 ps
T111 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1684632227 Jul 02 09:45:00 AM PDT 24 Jul 02 09:45:03 AM PDT 24 118887925 ps
T398 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3783429600 Jul 02 09:45:12 AM PDT 24 Jul 02 09:45:19 AM PDT 24 5922942582 ps
T399 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1289686646 Jul 02 09:44:56 AM PDT 24 Jul 02 09:44:58 AM PDT 24 320808295 ps
T400 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1429726763 Jul 02 09:44:32 AM PDT 24 Jul 02 09:44:38 AM PDT 24 321659917 ps
T401 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1038722635 Jul 02 09:44:28 AM PDT 24 Jul 02 09:44:29 AM PDT 24 57714816 ps
T402 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2100415398 Jul 02 09:45:02 AM PDT 24 Jul 02 09:45:06 AM PDT 24 1055336711 ps
T403 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1201344034 Jul 02 09:44:32 AM PDT 24 Jul 02 09:44:35 AM PDT 24 161279672 ps
T404 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2432079053 Jul 02 09:45:06 AM PDT 24 Jul 02 09:45:12 AM PDT 24 1076951913 ps
T405 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4070313488 Jul 02 09:44:28 AM PDT 24 Jul 02 09:45:41 AM PDT 24 82695390527 ps
T406 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1106614993 Jul 02 09:45:07 AM PDT 24 Jul 02 09:45:09 AM PDT 24 255402614 ps
T407 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2780328973 Jul 02 09:44:55 AM PDT 24 Jul 02 09:44:58 AM PDT 24 498326489 ps
T408 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3240005984 Jul 02 09:44:53 AM PDT 24 Jul 02 09:44:57 AM PDT 24 59552115 ps
T409 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.718640233 Jul 02 09:44:18 AM PDT 24 Jul 02 09:45:00 AM PDT 24 15364930812 ps
T410 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.362281470 Jul 02 09:44:23 AM PDT 24 Jul 02 09:45:29 AM PDT 24 4589971580 ps
T411 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3270736266 Jul 02 09:44:25 AM PDT 24 Jul 02 09:44:29 AM PDT 24 324688579 ps
T412 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2415963692 Jul 02 09:45:12 AM PDT 24 Jul 02 09:45:17 AM PDT 24 2103305688 ps
T413 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3759166581 Jul 02 09:44:53 AM PDT 24 Jul 02 09:45:29 AM PDT 24 16870497769 ps
T414 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1960949824 Jul 02 09:44:53 AM PDT 24 Jul 02 09:44:55 AM PDT 24 1382113841 ps
T415 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1212122235 Jul 02 09:44:37 AM PDT 24 Jul 02 09:44:40 AM PDT 24 121529604 ps
T416 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2930556711 Jul 02 09:44:37 AM PDT 24 Jul 02 09:44:38 AM PDT 24 67353372 ps
T417 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1710043316 Jul 02 09:44:18 AM PDT 24 Jul 02 09:44:23 AM PDT 24 4897940544 ps
T418 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3092569538 Jul 02 09:45:04 AM PDT 24 Jul 02 09:45:06 AM PDT 24 434257794 ps
T419 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2523679522 Jul 02 09:45:06 AM PDT 24 Jul 02 09:45:22 AM PDT 24 10989067372 ps
T420 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3231232382 Jul 02 09:44:56 AM PDT 24 Jul 02 09:45:00 AM PDT 24 329433800 ps
T421 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2969348475 Jul 02 09:44:23 AM PDT 24 Jul 02 09:45:32 AM PDT 24 104341384818 ps
T422 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2671710702 Jul 02 09:44:43 AM PDT 24 Jul 02 09:44:53 AM PDT 24 3150470175 ps
T423 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3147776011 Jul 02 09:44:56 AM PDT 24 Jul 02 09:45:00 AM PDT 24 553400610 ps
T424 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.81465197 Jul 02 09:44:32 AM PDT 24 Jul 02 09:44:34 AM PDT 24 344610829 ps
T425 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1513140278 Jul 02 09:44:36 AM PDT 24 Jul 02 09:45:10 AM PDT 24 4735848451 ps
T426 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3881876894 Jul 02 09:44:23 AM PDT 24 Jul 02 09:45:29 AM PDT 24 24433022977 ps
T427 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3933021218 Jul 02 09:45:12 AM PDT 24 Jul 02 09:45:21 AM PDT 24 517729468 ps
T428 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2648231260 Jul 02 09:44:46 AM PDT 24 Jul 02 09:44:52 AM PDT 24 629003684 ps
T429 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1154543541 Jul 02 09:44:23 AM PDT 24 Jul 02 09:44:24 AM PDT 24 77264211 ps
T430 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4249522787 Jul 02 09:44:25 AM PDT 24 Jul 02 09:44:27 AM PDT 24 134432060 ps
T431 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2785225877 Jul 02 09:44:32 AM PDT 24 Jul 02 09:44:33 AM PDT 24 255103702 ps

Test location /workspace/coverage/default/12.rv_dm_stress_all.357597714
Short name T8
Test name
Test status
Simulation time 4522710454 ps
CPU time 11.04 seconds
Started Jul 02 09:45:40 AM PDT 24
Finished Jul 02 09:45:53 AM PDT 24
Peak memory 213444 kb
Host smart-0b1db3e7-d677-4ccf-b706-f49c88983148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357597714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.357597714
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1379676959
Short name T58
Test name
Test status
Simulation time 43967121727 ps
CPU time 106.31 seconds
Started Jul 02 09:44:37 AM PDT 24
Finished Jul 02 09:46:24 AM PDT 24
Peak memory 221452 kb
Host smart-1a0a4635-3020-4eaf-954d-8a4d5032f392
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379676959 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.1379676959
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2542881199
Short name T48
Test name
Test status
Simulation time 5073679163 ps
CPU time 14.73 seconds
Started Jul 02 09:45:36 AM PDT 24
Finished Jul 02 09:45:53 AM PDT 24
Peak memory 213516 kb
Host smart-2ae5251f-0bae-486f-84d6-74a056b52d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542881199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2542881199
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.639897753
Short name T9
Test name
Test status
Simulation time 2997655638 ps
CPU time 3.32 seconds
Started Jul 02 09:45:23 AM PDT 24
Finished Jul 02 09:45:26 AM PDT 24
Peak memory 205272 kb
Host smart-5575dd10-55ee-4865-bc0d-eebd4d89ca9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639897753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.639897753
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.2783033417
Short name T130
Test name
Test status
Simulation time 4620288037 ps
CPU time 5.75 seconds
Started Jul 02 09:45:32 AM PDT 24
Finished Jul 02 09:45:38 AM PDT 24
Peak memory 213552 kb
Host smart-7e50f148-776f-47f3-9d50-d946379956ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783033417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2783033417
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3454874460
Short name T92
Test name
Test status
Simulation time 1922126611 ps
CPU time 10.06 seconds
Started Jul 02 09:44:58 AM PDT 24
Finished Jul 02 09:45:09 AM PDT 24
Peak memory 213348 kb
Host smart-56cad0e3-6c8f-4061-bbc8-86cd98526704
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454874460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
454874460
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.539962921
Short name T35
Test name
Test status
Simulation time 6147356281 ps
CPU time 5.42 seconds
Started Jul 02 09:45:49 AM PDT 24
Finished Jul 02 09:45:56 AM PDT 24
Peak memory 213384 kb
Host smart-adf074bb-bb36-4616-a471-2494d83a27d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539962921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.539962921
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.911156491
Short name T118
Test name
Test status
Simulation time 55238691 ps
CPU time 0.78 seconds
Started Jul 02 09:45:29 AM PDT 24
Finished Jul 02 09:45:30 AM PDT 24
Peak memory 204992 kb
Host smart-1d21cdff-74ac-4dc6-94bb-621e1f1a225a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911156491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.911156491
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.686194488
Short name T39
Test name
Test status
Simulation time 86751841 ps
CPU time 1.05 seconds
Started Jul 02 09:45:27 AM PDT 24
Finished Jul 02 09:45:29 AM PDT 24
Peak memory 215644 kb
Host smart-f6359acd-8360-496c-922e-7c0f798e404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686194488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.686194488
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.372383580
Short name T20
Test name
Test status
Simulation time 294232461 ps
CPU time 1.28 seconds
Started Jul 02 09:45:21 AM PDT 24
Finished Jul 02 09:45:23 AM PDT 24
Peak memory 204992 kb
Host smart-512759f0-b3e1-4877-9d64-51d0f026c677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372383580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.372383580
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2773735518
Short name T64
Test name
Test status
Simulation time 436079008 ps
CPU time 1.58 seconds
Started Jul 02 09:45:28 AM PDT 24
Finished Jul 02 09:45:30 AM PDT 24
Peak memory 237160 kb
Host smart-a366980e-63ff-41dd-8c20-c987d34c8107
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773735518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2773735518
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.836593982
Short name T134
Test name
Test status
Simulation time 4124401953 ps
CPU time 5 seconds
Started Jul 02 09:45:41 AM PDT 24
Finished Jul 02 09:45:48 AM PDT 24
Peak memory 213692 kb
Host smart-618e416b-c853-49f7-807a-d66f81e8d941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836593982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.836593982
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.870740847
Short name T24
Test name
Test status
Simulation time 6874234525 ps
CPU time 10.79 seconds
Started Jul 02 09:45:36 AM PDT 24
Finished Jul 02 09:45:49 AM PDT 24
Peak memory 213464 kb
Host smart-a6f0874c-906d-463a-b913-5e5b8531cea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870740847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.870740847
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1861478581
Short name T86
Test name
Test status
Simulation time 171113484 ps
CPU time 1.53 seconds
Started Jul 02 09:44:30 AM PDT 24
Finished Jul 02 09:44:32 AM PDT 24
Peak memory 213236 kb
Host smart-224ee41a-2e70-436a-b1a1-4b49275680e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861478581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1861478581
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.1729459632
Short name T17
Test name
Test status
Simulation time 10678556813 ps
CPU time 29.82 seconds
Started Jul 02 09:45:45 AM PDT 24
Finished Jul 02 09:46:17 AM PDT 24
Peak memory 213452 kb
Host smart-c6fae623-75d3-4678-bbe1-ceb6fd824d07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729459632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1729459632
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4126048990
Short name T119
Test name
Test status
Simulation time 5743085267 ps
CPU time 20.42 seconds
Started Jul 02 09:45:04 AM PDT 24
Finished Jul 02 09:45:25 AM PDT 24
Peak memory 213276 kb
Host smart-3b1f2b0a-96ed-4784-b2a0-572a0eadba43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126048990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.4
126048990
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.4271371126
Short name T57
Test name
Test status
Simulation time 192002588 ps
CPU time 0.79 seconds
Started Jul 02 09:45:20 AM PDT 24
Finished Jul 02 09:45:21 AM PDT 24
Peak memory 204984 kb
Host smart-868c1ae2-6ad1-47ce-a8d8-a94dc52560be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271371126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.4271371126
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.191195361
Short name T53
Test name
Test status
Simulation time 212759313 ps
CPU time 0.9 seconds
Started Jul 02 09:45:25 AM PDT 24
Finished Jul 02 09:45:27 AM PDT 24
Peak memory 213276 kb
Host smart-b0e65954-3b3a-410b-acd6-6843dcc06042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191195361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.191195361
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.31441993
Short name T32
Test name
Test status
Simulation time 22067422028 ps
CPU time 19.14 seconds
Started Jul 02 09:45:45 AM PDT 24
Finished Jul 02 09:46:06 AM PDT 24
Peak memory 213600 kb
Host smart-dadbf78c-b358-4226-991b-8db0afe825ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31441993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.31441993
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.817274991
Short name T28
Test name
Test status
Simulation time 2997057132 ps
CPU time 4.6 seconds
Started Jul 02 09:45:42 AM PDT 24
Finished Jul 02 09:45:49 AM PDT 24
Peak memory 205416 kb
Host smart-55517fbe-ff55-4912-872c-0b336b4a6dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817274991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.817274991
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.2864307500
Short name T146
Test name
Test status
Simulation time 5805039706 ps
CPU time 5.23 seconds
Started Jul 02 09:45:44 AM PDT 24
Finished Jul 02 09:45:51 AM PDT 24
Peak memory 213456 kb
Host smart-9656aacc-7b92-4eb4-89b0-bc1837353f1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864307500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2864307500
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1413791063
Short name T129
Test name
Test status
Simulation time 4102293110 ps
CPU time 11.33 seconds
Started Jul 02 09:45:45 AM PDT 24
Finished Jul 02 09:45:58 AM PDT 24
Peak memory 205320 kb
Host smart-93887e76-797c-4a8e-b494-6ad1e888e5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413791063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1413791063
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.650244028
Short name T11
Test name
Test status
Simulation time 5295006703 ps
CPU time 13.24 seconds
Started Jul 02 09:45:51 AM PDT 24
Finished Jul 02 09:46:05 AM PDT 24
Peak memory 205212 kb
Host smart-61a84e3f-bbc7-4fbe-9f2b-92bd30711c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650244028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.650244028
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2606658407
Short name T121
Test name
Test status
Simulation time 10889538738 ps
CPU time 26.03 seconds
Started Jul 02 09:45:35 AM PDT 24
Finished Jul 02 09:46:03 AM PDT 24
Peak memory 213500 kb
Host smart-6e0cd377-757f-45ac-b143-0b318e1099fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606658407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2606658407
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1684632227
Short name T111
Test name
Test status
Simulation time 118887925 ps
CPU time 1.59 seconds
Started Jul 02 09:45:00 AM PDT 24
Finished Jul 02 09:45:03 AM PDT 24
Peak memory 213360 kb
Host smart-d9ed4e7b-1ecb-49e0-823b-79adc46703d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684632227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1684632227
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.4106736334
Short name T4
Test name
Test status
Simulation time 1224673158 ps
CPU time 1.99 seconds
Started Jul 02 09:45:23 AM PDT 24
Finished Jul 02 09:45:26 AM PDT 24
Peak memory 204980 kb
Host smart-aa82c85f-075e-4bc0-bfbc-9bf59d1e1b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106736334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.4106736334
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1271789330
Short name T94
Test name
Test status
Simulation time 2056297283 ps
CPU time 19.31 seconds
Started Jul 02 09:44:38 AM PDT 24
Finished Jul 02 09:44:57 AM PDT 24
Peak memory 213264 kb
Host smart-de5fc1eb-de30-45e8-a603-584369e51044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271789330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1271789330
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.723551907
Short name T21
Test name
Test status
Simulation time 252261424 ps
CPU time 1.31 seconds
Started Jul 02 09:45:22 AM PDT 24
Finished Jul 02 09:45:24 AM PDT 24
Peak memory 204984 kb
Host smart-5a9b4037-8ffb-4507-b1b7-b3c5303c47d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723551907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.723551907
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3937227153
Short name T18
Test name
Test status
Simulation time 6066183485 ps
CPU time 18.45 seconds
Started Jul 02 09:45:40 AM PDT 24
Finished Jul 02 09:46:01 AM PDT 24
Peak memory 213384 kb
Host smart-86795354-2513-46cc-812c-43ebe1b89908
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937227153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3937227153
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.981195152
Short name T149
Test name
Test status
Simulation time 6238856231 ps
CPU time 4.77 seconds
Started Jul 02 09:45:46 AM PDT 24
Finished Jul 02 09:45:53 AM PDT 24
Peak memory 213388 kb
Host smart-95fd2aef-ff5c-4c55-abcd-ffef6a5812c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981195152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.981195152
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.973026207
Short name T59
Test name
Test status
Simulation time 29477674923 ps
CPU time 19.26 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:45:13 AM PDT 24
Peak memory 221504 kb
Host smart-7f4491ef-f848-48a9-841f-48d6cdcb62ac
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973026207 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.973026207
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2383638134
Short name T51
Test name
Test status
Simulation time 1747437348 ps
CPU time 5.38 seconds
Started Jul 02 09:45:15 AM PDT 24
Finished Jul 02 09:45:21 AM PDT 24
Peak memory 204960 kb
Host smart-bdf51ac0-c0fa-44a7-a535-85e4bd164e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383638134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2383638134
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.679007318
Short name T200
Test name
Test status
Simulation time 23742842400 ps
CPU time 34.42 seconds
Started Jul 02 09:45:36 AM PDT 24
Finished Jul 02 09:46:12 AM PDT 24
Peak memory 213572 kb
Host smart-23c5ab70-506d-4641-aada-a8773b966571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679007318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.679007318
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.776574274
Short name T49
Test name
Test status
Simulation time 2968615979 ps
CPU time 2 seconds
Started Jul 02 09:45:40 AM PDT 24
Finished Jul 02 09:45:43 AM PDT 24
Peak memory 205400 kb
Host smart-666460ce-401f-46e6-962a-561481c0e7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776574274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.776574274
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.1500030349
Short name T6
Test name
Test status
Simulation time 4290231174 ps
CPU time 5.03 seconds
Started Jul 02 09:45:42 AM PDT 24
Finished Jul 02 09:45:49 AM PDT 24
Peak memory 213468 kb
Host smart-e3c8be86-ee18-4610-8adc-ba9ac9446059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500030349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1500030349
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1411316372
Short name T123
Test name
Test status
Simulation time 1858341937 ps
CPU time 3.29 seconds
Started Jul 02 09:45:42 AM PDT 24
Finished Jul 02 09:45:48 AM PDT 24
Peak memory 214376 kb
Host smart-b16bcbc1-3d53-4e7c-8f8a-a3063dc295bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411316372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1411316372
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.3712717757
Short name T148
Test name
Test status
Simulation time 885412015 ps
CPU time 1.55 seconds
Started Jul 02 09:45:45 AM PDT 24
Finished Jul 02 09:45:49 AM PDT 24
Peak memory 205144 kb
Host smart-f9302d69-19ca-4201-b39e-c8765b6f88a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712717757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.3712717757
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.1079629745
Short name T145
Test name
Test status
Simulation time 16133912940 ps
CPU time 25.17 seconds
Started Jul 02 09:45:48 AM PDT 24
Finished Jul 02 09:46:14 AM PDT 24
Peak memory 205248 kb
Host smart-1488c7a2-911f-4761-9ddc-5786e97bfe86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079629745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1079629745
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3916381782
Short name T285
Test name
Test status
Simulation time 214914750 ps
CPU time 0.8 seconds
Started Jul 02 09:44:23 AM PDT 24
Finished Jul 02 09:44:24 AM PDT 24
Peak memory 204796 kb
Host smart-aac36bb6-3407-4c0e-9fcc-bfcefe405b1f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916381782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3916381782
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.561818905
Short name T90
Test name
Test status
Simulation time 2792912976 ps
CPU time 7.63 seconds
Started Jul 02 09:44:22 AM PDT 24
Finished Jul 02 09:44:30 AM PDT 24
Peak memory 205172 kb
Host smart-d83a4aab-109f-4b0f-9d60-97fd8e33bb7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561818905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.561818905
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.590834501
Short name T98
Test name
Test status
Simulation time 4056656069 ps
CPU time 5.55 seconds
Started Jul 02 09:44:29 AM PDT 24
Finished Jul 02 09:44:35 AM PDT 24
Peak memory 205040 kb
Host smart-cd21f575-9808-4cc4-8858-ace0ee97afce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590834501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.590834501
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2700743056
Short name T161
Test name
Test status
Simulation time 1368491429 ps
CPU time 9.76 seconds
Started Jul 02 09:44:54 AM PDT 24
Finished Jul 02 09:45:05 AM PDT 24
Peak memory 213288 kb
Host smart-b8406f50-f12b-4038-a95e-ef0dd679942d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700743056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2700743056
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.247114635
Short name T19
Test name
Test status
Simulation time 1639994155 ps
CPU time 4.33 seconds
Started Jul 02 09:45:14 AM PDT 24
Finished Jul 02 09:45:18 AM PDT 24
Peak memory 204956 kb
Host smart-ab62e6bd-eb9b-4831-8bdf-85202658f8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247114635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.247114635
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.3623279870
Short name T54
Test name
Test status
Simulation time 155037014 ps
CPU time 0.83 seconds
Started Jul 02 09:45:25 AM PDT 24
Finished Jul 02 09:45:27 AM PDT 24
Peak memory 204968 kb
Host smart-8c6906b0-383a-4aea-953a-22ff5ff66fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623279870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3623279870
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1582660945
Short name T122
Test name
Test status
Simulation time 740318218 ps
CPU time 2.91 seconds
Started Jul 02 09:45:21 AM PDT 24
Finished Jul 02 09:45:24 AM PDT 24
Peak memory 205304 kb
Host smart-142d3f25-cdce-4d0a-a345-048dc3547fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582660945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1582660945
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.601189497
Short name T36
Test name
Test status
Simulation time 3208202751 ps
CPU time 2.93 seconds
Started Jul 02 09:45:21 AM PDT 24
Finished Jul 02 09:45:25 AM PDT 24
Peak memory 205268 kb
Host smart-153d7315-e814-4c51-b0bb-5873be0b1df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601189497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.601189497
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.2183022190
Short name T23
Test name
Test status
Simulation time 7287695894 ps
CPU time 20.33 seconds
Started Jul 02 09:45:41 AM PDT 24
Finished Jul 02 09:46:03 AM PDT 24
Peak memory 205184 kb
Host smart-8e8e7b6d-3a44-4b04-82a8-04eb348c255d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183022190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2183022190
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.1395283723
Short name T147
Test name
Test status
Simulation time 6866706748 ps
CPU time 17.87 seconds
Started Jul 02 09:45:39 AM PDT 24
Finished Jul 02 09:45:58 AM PDT 24
Peak memory 213392 kb
Host smart-465854a1-79ce-43cd-a0f7-67096a6949dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395283723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1395283723
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3900346748
Short name T138
Test name
Test status
Simulation time 2785910653 ps
CPU time 8.67 seconds
Started Jul 02 09:45:27 AM PDT 24
Finished Jul 02 09:45:37 AM PDT 24
Peak memory 205424 kb
Host smart-3bf6c846-0dc5-459a-874f-4f0e04a4a5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900346748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3900346748
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.154095984
Short name T143
Test name
Test status
Simulation time 6861442941 ps
CPU time 9.65 seconds
Started Jul 02 09:45:41 AM PDT 24
Finished Jul 02 09:45:52 AM PDT 24
Peak memory 213396 kb
Host smart-b5e0c07d-0b51-46f1-bb19-f1dc2d1b5892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154095984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.154095984
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1543724178
Short name T140
Test name
Test status
Simulation time 8014486479 ps
CPU time 22.83 seconds
Started Jul 02 09:45:52 AM PDT 24
Finished Jul 02 09:46:16 AM PDT 24
Peak memory 213384 kb
Host smart-fa3df2c9-7c4e-4b36-bb4f-0a3e666b8a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543724178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1543724178
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.253499067
Short name T136
Test name
Test status
Simulation time 15941773987 ps
CPU time 17.22 seconds
Started Jul 02 09:45:43 AM PDT 24
Finished Jul 02 09:46:03 AM PDT 24
Peak memory 213580 kb
Host smart-639301e7-a34e-45cf-b2e3-f885ac4212a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253499067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.253499067
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.2063917151
Short name T141
Test name
Test status
Simulation time 3964795126 ps
CPU time 12.05 seconds
Started Jul 02 09:45:33 AM PDT 24
Finished Jul 02 09:45:46 AM PDT 24
Peak memory 213384 kb
Host smart-b6fcedc6-121a-48f9-b9ab-eef6f9d82e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063917151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2063917151
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.653779462
Short name T99
Test name
Test status
Simulation time 3990948422 ps
CPU time 31.05 seconds
Started Jul 02 09:44:20 AM PDT 24
Finished Jul 02 09:44:51 AM PDT 24
Peak memory 205088 kb
Host smart-e50ac1f9-3785-488d-af54-bf9af7594f76
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653779462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.653779462
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2604484697
Short name T106
Test name
Test status
Simulation time 5738377967 ps
CPU time 56.15 seconds
Started Jul 02 09:44:21 AM PDT 24
Finished Jul 02 09:45:18 AM PDT 24
Peak memory 213368 kb
Host smart-4710209d-522d-4774-87d1-00b9db259984
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604484697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2604484697
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.98576834
Short name T113
Test name
Test status
Simulation time 147902154 ps
CPU time 1.72 seconds
Started Jul 02 09:44:24 AM PDT 24
Finished Jul 02 09:44:26 AM PDT 24
Peak memory 213212 kb
Host smart-08781b6f-6f1c-4c9e-958c-71ef344515ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98576834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.98576834
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3270736266
Short name T411
Test name
Test status
Simulation time 324688579 ps
CPU time 2.9 seconds
Started Jul 02 09:44:25 AM PDT 24
Finished Jul 02 09:44:29 AM PDT 24
Peak memory 213264 kb
Host smart-584c9798-1a21-4b67-bdc6-5f190dddd8f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270736266 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3270736266
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3256654045
Short name T334
Test name
Test status
Simulation time 118996317 ps
CPU time 1.5 seconds
Started Jul 02 09:44:20 AM PDT 24
Finished Jul 02 09:44:22 AM PDT 24
Peak memory 213248 kb
Host smart-f503b9ed-bd19-434f-bf5f-3f675a99069e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256654045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3256654045
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2969348475
Short name T421
Test name
Test status
Simulation time 104341384818 ps
CPU time 69.07 seconds
Started Jul 02 09:44:23 AM PDT 24
Finished Jul 02 09:45:32 AM PDT 24
Peak memory 205260 kb
Host smart-c42f0f6b-9370-445e-a7ab-019a96f273b9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969348475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2969348475
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.718640233
Short name T409
Test name
Test status
Simulation time 15364930812 ps
CPU time 41.39 seconds
Started Jul 02 09:44:18 AM PDT 24
Finished Jul 02 09:45:00 AM PDT 24
Peak memory 205036 kb
Host smart-cc3b1557-e2b2-4699-915f-48fb8dcddb7b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718640233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
v_dm_jtag_dmi_csr_bit_bash.718640233
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2102295851
Short name T396
Test name
Test status
Simulation time 1087546052 ps
CPU time 4.2 seconds
Started Jul 02 09:44:21 AM PDT 24
Finished Jul 02 09:44:26 AM PDT 24
Peak memory 204904 kb
Host smart-21d93ef0-de3f-4301-87cd-480b6e3921f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102295851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2102295851
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1865610498
Short name T282
Test name
Test status
Simulation time 2888728928 ps
CPU time 1.98 seconds
Started Jul 02 09:44:18 AM PDT 24
Finished Jul 02 09:44:21 AM PDT 24
Peak memory 205012 kb
Host smart-c35b371a-f2da-4e1f-98e0-3ccac13fdbf7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865610498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
865610498
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3795402296
Short name T305
Test name
Test status
Simulation time 1056428148 ps
CPU time 3.24 seconds
Started Jul 02 09:44:20 AM PDT 24
Finished Jul 02 09:44:24 AM PDT 24
Peak memory 204776 kb
Host smart-ce59edbc-d988-4f2c-aed7-34be195bb884
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795402296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3795402296
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1710043316
Short name T417
Test name
Test status
Simulation time 4897940544 ps
CPU time 4.67 seconds
Started Jul 02 09:44:18 AM PDT 24
Finished Jul 02 09:44:23 AM PDT 24
Peak memory 205008 kb
Host smart-e13f9131-0c09-4c55-9e2c-3cdaa46d3c59
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710043316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1710043316
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3205110621
Short name T331
Test name
Test status
Simulation time 251019389 ps
CPU time 1.34 seconds
Started Jul 02 09:44:20 AM PDT 24
Finished Jul 02 09:44:22 AM PDT 24
Peak memory 204748 kb
Host smart-bdf9796d-b3e7-4309-9629-230fc1e4a0cc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205110621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3205110621
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2307496030
Short name T372
Test name
Test status
Simulation time 278175368 ps
CPU time 0.89 seconds
Started Jul 02 09:44:26 AM PDT 24
Finished Jul 02 09:44:28 AM PDT 24
Peak memory 204756 kb
Host smart-2a293d2d-238a-413e-818e-26538f170edc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307496030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
307496030
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4249522787
Short name T430
Test name
Test status
Simulation time 134432060 ps
CPU time 0.83 seconds
Started Jul 02 09:44:25 AM PDT 24
Finished Jul 02 09:44:27 AM PDT 24
Peak memory 204684 kb
Host smart-6352233c-437b-4744-be5f-783a64bb696b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249522787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.4249522787
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2582623414
Short name T322
Test name
Test status
Simulation time 187585086 ps
CPU time 0.68 seconds
Started Jul 02 09:44:26 AM PDT 24
Finished Jul 02 09:44:27 AM PDT 24
Peak memory 204752 kb
Host smart-04948b00-5f09-4cd8-bef2-10927d8ca91b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582623414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2582623414
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3880637412
Short name T384
Test name
Test status
Simulation time 34344807125 ps
CPU time 32.44 seconds
Started Jul 02 09:44:22 AM PDT 24
Finished Jul 02 09:44:55 AM PDT 24
Peak memory 220716 kb
Host smart-52ad2c96-1c29-4509-b65d-6c99c8e2f374
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880637412 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3880637412
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3040054128
Short name T369
Test name
Test status
Simulation time 327879673 ps
CPU time 1.88 seconds
Started Jul 02 09:44:21 AM PDT 24
Finished Jul 02 09:44:24 AM PDT 24
Peak memory 213252 kb
Host smart-e338d91e-f525-43ae-aaf3-5a1a1ceaba05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040054128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3040054128
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1275509488
Short name T84
Test name
Test status
Simulation time 1269367410 ps
CPU time 10.94 seconds
Started Jul 02 09:44:21 AM PDT 24
Finished Jul 02 09:44:33 AM PDT 24
Peak memory 213348 kb
Host smart-5934071a-20fb-47ef-bf38-708778a9deab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275509488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1275509488
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.362281470
Short name T410
Test name
Test status
Simulation time 4589971580 ps
CPU time 65.34 seconds
Started Jul 02 09:44:23 AM PDT 24
Finished Jul 02 09:45:29 AM PDT 24
Peak memory 213404 kb
Host smart-981bbd03-d38a-48cb-bd4d-95d46618075e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362281470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.362281470
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.695805138
Short name T109
Test name
Test status
Simulation time 1464755885 ps
CPU time 53.92 seconds
Started Jul 02 09:44:30 AM PDT 24
Finished Jul 02 09:45:24 AM PDT 24
Peak memory 205024 kb
Host smart-a32b2dc3-1725-41d4-a63b-ae93b4411937
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695805138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.695805138
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1064624661
Short name T311
Test name
Test status
Simulation time 3273602286 ps
CPU time 8.84 seconds
Started Jul 02 09:44:29 AM PDT 24
Finished Jul 02 09:44:39 AM PDT 24
Peak memory 219756 kb
Host smart-0860ac63-9163-42bf-ab7b-56c93ea1d308
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064624661 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1064624661
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3605764645
Short name T326
Test name
Test status
Simulation time 111160008 ps
CPU time 2.36 seconds
Started Jul 02 09:44:29 AM PDT 24
Finished Jul 02 09:44:32 AM PDT 24
Peak memory 213248 kb
Host smart-9ee9f5f4-ac64-4c9e-912f-32bf55f73dd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605764645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3605764645
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2206812816
Short name T337
Test name
Test status
Simulation time 43526538545 ps
CPU time 29.43 seconds
Started Jul 02 09:44:24 AM PDT 24
Finished Jul 02 09:44:54 AM PDT 24
Peak memory 205080 kb
Host smart-a0ad927e-5cc0-4fa5-8bd0-c70dfaf5c433
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206812816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2206812816
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2758829342
Short name T286
Test name
Test status
Simulation time 5809863105 ps
CPU time 17.47 seconds
Started Jul 02 09:44:24 AM PDT 24
Finished Jul 02 09:44:42 AM PDT 24
Peak memory 204988 kb
Host smart-f2dd3c8e-b086-40d5-a04e-76474c25a212
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758829342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.2758829342
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4049909176
Short name T307
Test name
Test status
Simulation time 3051599377 ps
CPU time 3.45 seconds
Started Jul 02 09:44:22 AM PDT 24
Finished Jul 02 09:44:26 AM PDT 24
Peak memory 205016 kb
Host smart-a671ce93-bec2-4d38-87e0-a359784a692c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049909176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.4
049909176
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3881876894
Short name T426
Test name
Test status
Simulation time 24433022977 ps
CPU time 65.53 seconds
Started Jul 02 09:44:23 AM PDT 24
Finished Jul 02 09:45:29 AM PDT 24
Peak memory 204996 kb
Host smart-312da56d-1535-41c2-8896-a52f3b723194
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881876894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3881876894
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1079806868
Short name T321
Test name
Test status
Simulation time 595643513 ps
CPU time 0.89 seconds
Started Jul 02 09:44:24 AM PDT 24
Finished Jul 02 09:44:25 AM PDT 24
Peak memory 204776 kb
Host smart-e3e70d00-f5c5-4ddd-b233-fefd6b89a99c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079806868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1079806868
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4285357954
Short name T296
Test name
Test status
Simulation time 232602841 ps
CPU time 0.81 seconds
Started Jul 02 09:44:29 AM PDT 24
Finished Jul 02 09:44:31 AM PDT 24
Peak memory 204752 kb
Host smart-39568fc0-f7f7-4931-9b8f-2aed51de2cf3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285357954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.4
285357954
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1154543541
Short name T429
Test name
Test status
Simulation time 77264211 ps
CPU time 0.74 seconds
Started Jul 02 09:44:23 AM PDT 24
Finished Jul 02 09:44:24 AM PDT 24
Peak memory 204716 kb
Host smart-6f5ff967-a849-46b4-9c06-ea020016e106
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154543541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1154543541
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1038722635
Short name T401
Test name
Test status
Simulation time 57714816 ps
CPU time 0.68 seconds
Started Jul 02 09:44:28 AM PDT 24
Finished Jul 02 09:44:29 AM PDT 24
Peak memory 204744 kb
Host smart-002b09d5-f672-4876-8cab-1a4c70a43b7a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038722635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1038722635
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.626927267
Short name T71
Test name
Test status
Simulation time 181691390 ps
CPU time 3.5 seconds
Started Jul 02 09:44:29 AM PDT 24
Finished Jul 02 09:44:34 AM PDT 24
Peak memory 205068 kb
Host smart-4c81a2d5-d9b6-441f-9dfd-e5d50de26e05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626927267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.626927267
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2533541288
Short name T344
Test name
Test status
Simulation time 45020880934 ps
CPU time 124.56 seconds
Started Jul 02 09:44:24 AM PDT 24
Finished Jul 02 09:46:29 AM PDT 24
Peak memory 221568 kb
Host smart-b79a5ed8-f0f0-4070-9332-85cb053bf3a6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533541288 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2533541288
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1812298999
Short name T376
Test name
Test status
Simulation time 1126030235 ps
CPU time 6.29 seconds
Started Jul 02 09:44:23 AM PDT 24
Finished Jul 02 09:44:30 AM PDT 24
Peak memory 216040 kb
Host smart-5b507aaa-82f5-4954-ad88-b6b25b34a780
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812298999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1812298999
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3105870966
Short name T66
Test name
Test status
Simulation time 1174112418 ps
CPU time 12.29 seconds
Started Jul 02 09:44:23 AM PDT 24
Finished Jul 02 09:44:36 AM PDT 24
Peak memory 213268 kb
Host smart-f9200f3b-fcbe-49ef-b188-bc1f952c5325
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105870966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3105870966
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.112109503
Short name T371
Test name
Test status
Simulation time 562159141 ps
CPU time 5.01 seconds
Started Jul 02 09:45:00 AM PDT 24
Finished Jul 02 09:45:06 AM PDT 24
Peak memory 219308 kb
Host smart-6bceac8c-c1c5-4666-ac24-f23b15d05421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112109503 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.112109503
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1863541134
Short name T70
Test name
Test status
Simulation time 295599609 ps
CPU time 1.52 seconds
Started Jul 02 09:44:59 AM PDT 24
Finished Jul 02 09:45:01 AM PDT 24
Peak memory 213160 kb
Host smart-bbbc3b50-eaf1-4f0a-bee0-f97f273da614
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863541134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1863541134
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2495635923
Short name T380
Test name
Test status
Simulation time 29370384810 ps
CPU time 22.84 seconds
Started Jul 02 09:44:56 AM PDT 24
Finished Jul 02 09:45:20 AM PDT 24
Peak memory 205012 kb
Host smart-21b2e9e3-d547-41f1-a2de-cc956524519f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495635923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.2495635923
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1146056907
Short name T350
Test name
Test status
Simulation time 2120671009 ps
CPU time 4.95 seconds
Started Jul 02 09:44:55 AM PDT 24
Finished Jul 02 09:45:01 AM PDT 24
Peak memory 204928 kb
Host smart-857dc6c0-9071-4f46-9ffa-2e2145a2f52b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146056907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1146056907
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2834113712
Short name T319
Test name
Test status
Simulation time 112523415 ps
CPU time 0.81 seconds
Started Jul 02 09:44:55 AM PDT 24
Finished Jul 02 09:44:57 AM PDT 24
Peak memory 204788 kb
Host smart-add6bdb9-6d64-427d-a45c-f40b449c86ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834113712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2834113712
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2401635212
Short name T91
Test name
Test status
Simulation time 277043363 ps
CPU time 4.49 seconds
Started Jul 02 09:45:01 AM PDT 24
Finished Jul 02 09:45:06 AM PDT 24
Peak memory 205072 kb
Host smart-8413b41b-09e6-4dda-b937-7090cc1d23e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401635212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2401635212
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3147776011
Short name T423
Test name
Test status
Simulation time 553400610 ps
CPU time 3.07 seconds
Started Jul 02 09:44:56 AM PDT 24
Finished Jul 02 09:45:00 AM PDT 24
Peak memory 213236 kb
Host smart-6fcf6a37-d0c1-41ad-b109-dfdf62c0ef69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147776011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3147776011
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1345108978
Short name T93
Test name
Test status
Simulation time 7946640050 ps
CPU time 9.86 seconds
Started Jul 02 09:45:00 AM PDT 24
Finished Jul 02 09:45:11 AM PDT 24
Peak memory 213484 kb
Host smart-606bfd58-426f-4a54-a773-331230d83cbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345108978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
345108978
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3521288705
Short name T365
Test name
Test status
Simulation time 148877222 ps
CPU time 2.61 seconds
Started Jul 02 09:44:57 AM PDT 24
Finished Jul 02 09:45:00 AM PDT 24
Peak memory 218520 kb
Host smart-4c212625-62cd-4f5a-a3a6-6b6702ac2eb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521288705 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3521288705
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1228908640
Short name T379
Test name
Test status
Simulation time 89733066 ps
CPU time 2.08 seconds
Started Jul 02 09:45:00 AM PDT 24
Finished Jul 02 09:45:03 AM PDT 24
Peak memory 213184 kb
Host smart-85b74bd0-ffb0-452b-90f7-d52e77aa4f8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228908640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1228908640
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3665486089
Short name T327
Test name
Test status
Simulation time 2517300595 ps
CPU time 4.35 seconds
Started Jul 02 09:44:59 AM PDT 24
Finished Jul 02 09:45:04 AM PDT 24
Peak memory 205028 kb
Host smart-ceeace93-9ae0-42af-b7a0-0e6e9857a4a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665486089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.3665486089
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.882327427
Short name T325
Test name
Test status
Simulation time 2133916071 ps
CPU time 7.28 seconds
Started Jul 02 09:44:58 AM PDT 24
Finished Jul 02 09:45:07 AM PDT 24
Peak memory 204920 kb
Host smart-2adcdda7-3379-443b-a8ca-5cf936b9f595
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882327427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.882327427
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.845325281
Short name T287
Test name
Test status
Simulation time 915478505 ps
CPU time 2.91 seconds
Started Jul 02 09:45:04 AM PDT 24
Finished Jul 02 09:45:08 AM PDT 24
Peak memory 204796 kb
Host smart-f79382a4-2298-4c44-a9c1-c0b938866217
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845325281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.845325281
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3491106719
Short name T116
Test name
Test status
Simulation time 942399401 ps
CPU time 7.91 seconds
Started Jul 02 09:44:58 AM PDT 24
Finished Jul 02 09:45:06 AM PDT 24
Peak memory 205088 kb
Host smart-dc2f25d9-2eca-4ebd-8070-9b4b59965585
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491106719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3491106719
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.879526964
Short name T310
Test name
Test status
Simulation time 221662149 ps
CPU time 5.47 seconds
Started Jul 02 09:44:55 AM PDT 24
Finished Jul 02 09:45:01 AM PDT 24
Peak memory 213268 kb
Host smart-5f11ccbf-75db-44d1-80db-80490356ce8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879526964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.879526964
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.665757152
Short name T328
Test name
Test status
Simulation time 3292367775 ps
CPU time 4.9 seconds
Started Jul 02 09:44:59 AM PDT 24
Finished Jul 02 09:45:05 AM PDT 24
Peak memory 219640 kb
Host smart-0eaa8c70-1c59-46c6-a105-2820fe7b485a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665757152 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.665757152
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1985595650
Short name T315
Test name
Test status
Simulation time 6149863797 ps
CPU time 11.65 seconds
Started Jul 02 09:45:01 AM PDT 24
Finished Jul 02 09:45:13 AM PDT 24
Peak memory 205004 kb
Host smart-188f1528-1512-4fe5-bea9-782af12ec5fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985595650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.1985595650
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.88980901
Short name T298
Test name
Test status
Simulation time 1738679940 ps
CPU time 4.9 seconds
Started Jul 02 09:45:00 AM PDT 24
Finished Jul 02 09:45:06 AM PDT 24
Peak memory 204968 kb
Host smart-a15a63fe-939d-4686-aa73-3bbc589af4e6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88980901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.88980901
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3971692303
Short name T329
Test name
Test status
Simulation time 992577609 ps
CPU time 0.97 seconds
Started Jul 02 09:44:58 AM PDT 24
Finished Jul 02 09:45:00 AM PDT 24
Peak memory 204744 kb
Host smart-c1237af0-e4c9-43bb-a81c-5e8166eb014a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971692303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3971692303
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2669663736
Short name T355
Test name
Test status
Simulation time 1051642386 ps
CPU time 4.44 seconds
Started Jul 02 09:44:57 AM PDT 24
Finished Jul 02 09:45:02 AM PDT 24
Peak memory 205108 kb
Host smart-27006198-75ac-4c2c-afc1-950d758a36e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669663736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2669663736
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4106917060
Short name T335
Test name
Test status
Simulation time 85313816 ps
CPU time 3.68 seconds
Started Jul 02 09:45:01 AM PDT 24
Finished Jul 02 09:45:05 AM PDT 24
Peak memory 213424 kb
Host smart-d4e88ec0-ec56-445e-b911-3fefd678066c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106917060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.4106917060
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1208949105
Short name T162
Test name
Test status
Simulation time 1148499842 ps
CPU time 17.36 seconds
Started Jul 02 09:45:04 AM PDT 24
Finished Jul 02 09:45:22 AM PDT 24
Peak memory 213292 kb
Host smart-a27c5287-e081-4106-862f-cfe715b5a72f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208949105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
208949105
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1142975337
Short name T397
Test name
Test status
Simulation time 2058784337 ps
CPU time 2.69 seconds
Started Jul 02 09:45:01 AM PDT 24
Finished Jul 02 09:45:05 AM PDT 24
Peak memory 213416 kb
Host smart-7d5642fc-0155-4941-a2bf-45b54de8cd46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142975337 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1142975337
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3984158986
Short name T353
Test name
Test status
Simulation time 256070891 ps
CPU time 1.73 seconds
Started Jul 02 09:45:01 AM PDT 24
Finished Jul 02 09:45:04 AM PDT 24
Peak memory 213220 kb
Host smart-cfa7f232-ee67-4ca1-adaf-a083bd4a674e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984158986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3984158986
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3752660761
Short name T283
Test name
Test status
Simulation time 8956153858 ps
CPU time 25.64 seconds
Started Jul 02 09:44:59 AM PDT 24
Finished Jul 02 09:45:26 AM PDT 24
Peak memory 205064 kb
Host smart-353e1f93-f10c-4971-8837-5a96c5eeca8a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752660761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.3752660761
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1738739432
Short name T284
Test name
Test status
Simulation time 5342092596 ps
CPU time 14.79 seconds
Started Jul 02 09:44:59 AM PDT 24
Finished Jul 02 09:45:15 AM PDT 24
Peak memory 205000 kb
Host smart-ea74d9a4-d64e-4ca3-b04b-82cc10d9c1ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738739432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1738739432
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4054723522
Short name T280
Test name
Test status
Simulation time 148697901 ps
CPU time 1.05 seconds
Started Jul 02 09:44:57 AM PDT 24
Finished Jul 02 09:44:59 AM PDT 24
Peak memory 204784 kb
Host smart-f33f06de-5e9e-40bb-bed3-57815035589e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054723522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
4054723522
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1065002920
Short name T117
Test name
Test status
Simulation time 1058081759 ps
CPU time 8.17 seconds
Started Jul 02 09:45:02 AM PDT 24
Finished Jul 02 09:45:11 AM PDT 24
Peak memory 205064 kb
Host smart-6c704a6d-f12e-4816-b55f-e016c6c1eb0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065002920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1065002920
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3903376963
Short name T69
Test name
Test status
Simulation time 245371905 ps
CPU time 4.52 seconds
Started Jul 02 09:45:06 AM PDT 24
Finished Jul 02 09:45:11 AM PDT 24
Peak memory 213268 kb
Host smart-840c3e31-1bb1-48f8-bca4-f56af0f8a2ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903376963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3903376963
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3888230084
Short name T381
Test name
Test status
Simulation time 1508718553 ps
CPU time 11.72 seconds
Started Jul 02 09:45:04 AM PDT 24
Finished Jul 02 09:45:17 AM PDT 24
Peak memory 213312 kb
Host smart-a2b303be-4d3b-47f0-b163-170ac70be649
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888230084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
888230084
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3375314589
Short name T364
Test name
Test status
Simulation time 1937377218 ps
CPU time 5.07 seconds
Started Jul 02 09:45:00 AM PDT 24
Finished Jul 02 09:45:06 AM PDT 24
Peak memory 213360 kb
Host smart-f3880394-9205-49a7-8d01-f6803f1f420a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375314589 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3375314589
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3092569538
Short name T418
Test name
Test status
Simulation time 434257794 ps
CPU time 2.48 seconds
Started Jul 02 09:45:04 AM PDT 24
Finished Jul 02 09:45:06 AM PDT 24
Peak memory 213264 kb
Host smart-38bac501-d697-4efe-aa55-58b0fc2926ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092569538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3092569538
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3225578728
Short name T342
Test name
Test status
Simulation time 53244848218 ps
CPU time 154.08 seconds
Started Jul 02 09:45:00 AM PDT 24
Finished Jul 02 09:47:36 AM PDT 24
Peak memory 205040 kb
Host smart-5fe6811a-080d-462e-91ed-34203cb10430
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225578728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.3225578728
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3807934329
Short name T340
Test name
Test status
Simulation time 10188999664 ps
CPU time 8.19 seconds
Started Jul 02 09:45:02 AM PDT 24
Finished Jul 02 09:45:11 AM PDT 24
Peak memory 204988 kb
Host smart-56b4758f-5b94-4775-9473-c162c4fe378a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807934329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3807934329
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2100415398
Short name T402
Test name
Test status
Simulation time 1055336711 ps
CPU time 3.37 seconds
Started Jul 02 09:45:02 AM PDT 24
Finished Jul 02 09:45:06 AM PDT 24
Peak memory 204716 kb
Host smart-cb9e37bd-97c3-48d6-a379-5edc40ea3d79
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100415398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2100415398
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1561691792
Short name T114
Test name
Test status
Simulation time 1758839335 ps
CPU time 7.41 seconds
Started Jul 02 09:45:00 AM PDT 24
Finished Jul 02 09:45:08 AM PDT 24
Peak memory 205096 kb
Host smart-cfe0b22b-6b2f-4e39-8db8-ff85769a3a80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561691792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1561691792
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2426007237
Short name T333
Test name
Test status
Simulation time 162969639 ps
CPU time 3.09 seconds
Started Jul 02 09:45:02 AM PDT 24
Finished Jul 02 09:45:05 AM PDT 24
Peak memory 221476 kb
Host smart-9afc6c36-f68b-4597-9d20-2d3c030ce063
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426007237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2426007237
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.812065480
Short name T346
Test name
Test status
Simulation time 1203275960 ps
CPU time 10.82 seconds
Started Jul 02 09:45:02 AM PDT 24
Finished Jul 02 09:45:13 AM PDT 24
Peak memory 213276 kb
Host smart-47c5fe42-9692-4ffb-873f-72a87b70f3b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812065480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.812065480
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.740480714
Short name T356
Test name
Test status
Simulation time 361303232 ps
CPU time 4.61 seconds
Started Jul 02 09:45:08 AM PDT 24
Finished Jul 02 09:45:14 AM PDT 24
Peak memory 219556 kb
Host smart-a24c92ce-2a36-4403-80e0-b7bb6919db4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740480714 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.740480714
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3078168193
Short name T112
Test name
Test status
Simulation time 124742615 ps
CPU time 2.36 seconds
Started Jul 02 09:45:07 AM PDT 24
Finished Jul 02 09:45:10 AM PDT 24
Peak memory 213304 kb
Host smart-adc40bb2-5aa6-432b-b49b-db00d8509db0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078168193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3078168193
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1792999098
Short name T277
Test name
Test status
Simulation time 12826264562 ps
CPU time 36.34 seconds
Started Jul 02 09:45:05 AM PDT 24
Finished Jul 02 09:45:42 AM PDT 24
Peak memory 205032 kb
Host smart-ef82ae3c-d167-4dbe-9d26-6aab2e7cde6d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792999098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.1792999098
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2523679522
Short name T419
Test name
Test status
Simulation time 10989067372 ps
CPU time 15.11 seconds
Started Jul 02 09:45:06 AM PDT 24
Finished Jul 02 09:45:22 AM PDT 24
Peak memory 205024 kb
Host smart-eb9db14b-b226-4010-a12b-0d478e0214ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523679522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2523679522
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2733467077
Short name T76
Test name
Test status
Simulation time 152714132 ps
CPU time 0.86 seconds
Started Jul 02 09:45:04 AM PDT 24
Finished Jul 02 09:45:05 AM PDT 24
Peak memory 204784 kb
Host smart-a5cc054e-d7d6-4ca3-8b7a-bf64f04704cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733467077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2733467077
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3338072867
Short name T103
Test name
Test status
Simulation time 122436884 ps
CPU time 3.84 seconds
Started Jul 02 09:45:07 AM PDT 24
Finished Jul 02 09:45:12 AM PDT 24
Peak memory 204996 kb
Host smart-db768512-0c00-4ad9-859a-29cdb8ae6acd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338072867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3338072867
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3810883169
Short name T338
Test name
Test status
Simulation time 229230320 ps
CPU time 4.12 seconds
Started Jul 02 09:45:08 AM PDT 24
Finished Jul 02 09:45:13 AM PDT 24
Peak memory 213296 kb
Host smart-a2d174ae-5b7e-4e80-a5c7-33cbd960a544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810883169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3810883169
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.4223595310
Short name T159
Test name
Test status
Simulation time 1673387970 ps
CPU time 18.4 seconds
Started Jul 02 09:45:06 AM PDT 24
Finished Jul 02 09:45:25 AM PDT 24
Peak memory 221380 kb
Host smart-031610f0-fccd-4cbe-855a-52c0a2f30389
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223595310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.4
223595310
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2352417412
Short name T386
Test name
Test status
Simulation time 5017846400 ps
CPU time 10.41 seconds
Started Jul 02 09:45:09 AM PDT 24
Finished Jul 02 09:45:20 AM PDT 24
Peak memory 220256 kb
Host smart-5d1accbb-b8c2-4ba2-a1bf-4a0a4782bf61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352417412 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2352417412
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1288279122
Short name T110
Test name
Test status
Simulation time 90389620 ps
CPU time 2.17 seconds
Started Jul 02 09:45:05 AM PDT 24
Finished Jul 02 09:45:07 AM PDT 24
Peak memory 213348 kb
Host smart-805e9a3b-fd7d-4479-a82f-bbb47b1204da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288279122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1288279122
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3739497827
Short name T304
Test name
Test status
Simulation time 31363221040 ps
CPU time 43.63 seconds
Started Jul 02 09:45:08 AM PDT 24
Finished Jul 02 09:45:53 AM PDT 24
Peak memory 205024 kb
Host smart-362df2a1-d192-4c22-a549-d926b6ab8643
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739497827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.3739497827
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4221022289
Short name T279
Test name
Test status
Simulation time 1506376278 ps
CPU time 2.59 seconds
Started Jul 02 09:45:07 AM PDT 24
Finished Jul 02 09:45:10 AM PDT 24
Peak memory 204920 kb
Host smart-09937bf9-303a-4724-a380-001b101ba654
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221022289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
4221022289
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3474672228
Short name T352
Test name
Test status
Simulation time 467871252 ps
CPU time 0.88 seconds
Started Jul 02 09:45:07 AM PDT 24
Finished Jul 02 09:45:08 AM PDT 24
Peak memory 204740 kb
Host smart-15c605f6-ce56-443f-835d-14be17a636d3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474672228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3474672228
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.645634778
Short name T370
Test name
Test status
Simulation time 925564435 ps
CPU time 4.23 seconds
Started Jul 02 09:45:08 AM PDT 24
Finished Jul 02 09:45:13 AM PDT 24
Peak memory 205068 kb
Host smart-3f565596-52f2-45fa-870a-7f92bc7a1914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645634778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.645634778
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.797595041
Short name T367
Test name
Test status
Simulation time 266267563 ps
CPU time 2.99 seconds
Started Jul 02 09:45:07 AM PDT 24
Finished Jul 02 09:45:11 AM PDT 24
Peak memory 213256 kb
Host smart-4b4ba69c-fede-44db-bdca-8b1d4cb0a4a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797595041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.797595041
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1022207690
Short name T158
Test name
Test status
Simulation time 5725504701 ps
CPU time 30.08 seconds
Started Jul 02 09:45:06 AM PDT 24
Finished Jul 02 09:45:37 AM PDT 24
Peak memory 213272 kb
Host smart-39d413fb-c9aa-4696-9a7e-fe6de88cda4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022207690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
022207690
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2432079053
Short name T404
Test name
Test status
Simulation time 1076951913 ps
CPU time 5.24 seconds
Started Jul 02 09:45:06 AM PDT 24
Finished Jul 02 09:45:12 AM PDT 24
Peak memory 218884 kb
Host smart-e6e96a34-bfd6-4e8f-8204-993e97e260f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432079053 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2432079053
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1106614993
Short name T406
Test name
Test status
Simulation time 255402614 ps
CPU time 1.52 seconds
Started Jul 02 09:45:07 AM PDT 24
Finished Jul 02 09:45:09 AM PDT 24
Peak memory 213292 kb
Host smart-35353fe6-914f-459e-90d9-6de7705d7b45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106614993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1106614993
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1792674417
Short name T293
Test name
Test status
Simulation time 2396862903 ps
CPU time 4.33 seconds
Started Jul 02 09:45:06 AM PDT 24
Finished Jul 02 09:45:11 AM PDT 24
Peak memory 204992 kb
Host smart-09cde38f-6573-493b-a92b-b44eee9018ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792674417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.1792674417
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2881210475
Short name T289
Test name
Test status
Simulation time 6707806580 ps
CPU time 18.06 seconds
Started Jul 02 09:45:07 AM PDT 24
Finished Jul 02 09:45:26 AM PDT 24
Peak memory 204992 kb
Host smart-13d93531-d453-4ba7-b5ab-4307b5f0dd84
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881210475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2881210475
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.248872783
Short name T77
Test name
Test status
Simulation time 395831502 ps
CPU time 0.76 seconds
Started Jul 02 09:45:06 AM PDT 24
Finished Jul 02 09:45:08 AM PDT 24
Peak memory 204956 kb
Host smart-4ea363e3-7f43-4297-8244-5a3b49811da0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248872783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.248872783
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.676118742
Short name T374
Test name
Test status
Simulation time 838984232 ps
CPU time 7.56 seconds
Started Jul 02 09:45:09 AM PDT 24
Finished Jul 02 09:45:17 AM PDT 24
Peak memory 205132 kb
Host smart-8698f836-43a6-4ef9-8d63-630796d47f14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676118742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.676118742
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.284138253
Short name T316
Test name
Test status
Simulation time 599548865 ps
CPU time 6.31 seconds
Started Jul 02 09:45:09 AM PDT 24
Finished Jul 02 09:45:16 AM PDT 24
Peak memory 213280 kb
Host smart-5dc18ccf-75f3-43d8-b1e2-ef1b1a468c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284138253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.284138253
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2415963692
Short name T412
Test name
Test status
Simulation time 2103305688 ps
CPU time 4.94 seconds
Started Jul 02 09:45:12 AM PDT 24
Finished Jul 02 09:45:17 AM PDT 24
Peak memory 221420 kb
Host smart-88434e3d-0716-4908-992b-0376146b3112
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415963692 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2415963692
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1282441743
Short name T107
Test name
Test status
Simulation time 124254504 ps
CPU time 1.71 seconds
Started Jul 02 09:45:17 AM PDT 24
Finished Jul 02 09:45:19 AM PDT 24
Peak memory 213428 kb
Host smart-9e381b68-7d4a-46fc-9ba7-ec98e39e167d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282441743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1282441743
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2067624564
Short name T288
Test name
Test status
Simulation time 13761763455 ps
CPU time 12.12 seconds
Started Jul 02 09:45:07 AM PDT 24
Finished Jul 02 09:45:20 AM PDT 24
Peak memory 205004 kb
Host smart-96a54887-443f-4bc9-95e8-2bbaac9722eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067624564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2067624564
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1217059779
Short name T313
Test name
Test status
Simulation time 1573148435 ps
CPU time 5.13 seconds
Started Jul 02 09:45:07 AM PDT 24
Finished Jul 02 09:45:13 AM PDT 24
Peak memory 204936 kb
Host smart-22c53a9b-4ecb-48e2-904f-cb5c8b1d94dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217059779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1217059779
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2090550936
Short name T383
Test name
Test status
Simulation time 203188933 ps
CPU time 0.99 seconds
Started Jul 02 09:45:06 AM PDT 24
Finished Jul 02 09:45:08 AM PDT 24
Peak memory 204744 kb
Host smart-de48b45f-773d-4e56-9ebb-3c726fbf0b95
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090550936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2090550936
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3933021218
Short name T427
Test name
Test status
Simulation time 517729468 ps
CPU time 7.42 seconds
Started Jul 02 09:45:12 AM PDT 24
Finished Jul 02 09:45:21 AM PDT 24
Peak memory 205088 kb
Host smart-d7f85daa-bc3f-4bf4-b70a-624036c1427a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933021218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3933021218
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2340441569
Short name T348
Test name
Test status
Simulation time 1083823671 ps
CPU time 4.45 seconds
Started Jul 02 09:45:05 AM PDT 24
Finished Jul 02 09:45:10 AM PDT 24
Peak memory 213268 kb
Host smart-b729c11c-9a7d-438b-8262-612671f85c26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340441569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2340441569
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2189857732
Short name T164
Test name
Test status
Simulation time 641655755 ps
CPU time 8.57 seconds
Started Jul 02 09:45:08 AM PDT 24
Finished Jul 02 09:45:18 AM PDT 24
Peak memory 221420 kb
Host smart-25256453-163e-4745-90ff-21357be9a425
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189857732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
189857732
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3783429600
Short name T398
Test name
Test status
Simulation time 5922942582 ps
CPU time 6.28 seconds
Started Jul 02 09:45:12 AM PDT 24
Finished Jul 02 09:45:19 AM PDT 24
Peak memory 221540 kb
Host smart-f440511b-5061-4055-b783-0c5be209acbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783429600 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3783429600
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.130145769
Short name T88
Test name
Test status
Simulation time 222606497 ps
CPU time 1.53 seconds
Started Jul 02 09:45:13 AM PDT 24
Finished Jul 02 09:45:15 AM PDT 24
Peak memory 213220 kb
Host smart-e5a8da43-4d59-4b96-9db0-fd824e2d1ff7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130145769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.130145769
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3991171358
Short name T320
Test name
Test status
Simulation time 18582308057 ps
CPU time 25.22 seconds
Started Jul 02 09:45:10 AM PDT 24
Finished Jul 02 09:45:36 AM PDT 24
Peak memory 205048 kb
Host smart-f73097ca-efb9-45d6-a0ab-0eca7cfdcaac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991171358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.3991171358
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2554390233
Short name T336
Test name
Test status
Simulation time 889466362 ps
CPU time 2.4 seconds
Started Jul 02 09:45:14 AM PDT 24
Finished Jul 02 09:45:17 AM PDT 24
Peak memory 204836 kb
Host smart-27237cc5-fffc-4353-9671-51db0c11ac55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554390233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2554390233
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2206183520
Short name T309
Test name
Test status
Simulation time 584842824 ps
CPU time 2.22 seconds
Started Jul 02 09:45:13 AM PDT 24
Finished Jul 02 09:45:16 AM PDT 24
Peak memory 204776 kb
Host smart-8c852861-ff1a-4958-a7a3-6e614d85387a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206183520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2206183520
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1724318288
Short name T388
Test name
Test status
Simulation time 468677330 ps
CPU time 7.61 seconds
Started Jul 02 09:45:13 AM PDT 24
Finished Jul 02 09:45:21 AM PDT 24
Peak memory 205068 kb
Host smart-d55914ad-2757-4232-ab54-05e7cb0433a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724318288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1724318288
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2028087533
Short name T120
Test name
Test status
Simulation time 273905748 ps
CPU time 5.93 seconds
Started Jul 02 09:45:11 AM PDT 24
Finished Jul 02 09:45:18 AM PDT 24
Peak memory 213616 kb
Host smart-277d212e-d281-4846-9c38-720935404d3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028087533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2028087533
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2064513862
Short name T160
Test name
Test status
Simulation time 2073670020 ps
CPU time 16.95 seconds
Started Jul 02 09:45:11 AM PDT 24
Finished Jul 02 09:45:29 AM PDT 24
Peak memory 213292 kb
Host smart-268837a8-94cd-4a0e-9aa5-68ed22015925
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064513862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
064513862
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3036255345
Short name T87
Test name
Test status
Simulation time 6749076792 ps
CPU time 71.05 seconds
Started Jul 02 09:44:28 AM PDT 24
Finished Jul 02 09:45:39 AM PDT 24
Peak memory 213372 kb
Host smart-25b39a71-d36e-4b5f-b8d5-d3fe9f912e63
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036255345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3036255345
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2040659835
Short name T394
Test name
Test status
Simulation time 11200896558 ps
CPU time 32.93 seconds
Started Jul 02 09:44:33 AM PDT 24
Finished Jul 02 09:45:06 AM PDT 24
Peak memory 213400 kb
Host smart-57d3df06-3163-4aec-a596-5dfcd39ed8a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040659835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2040659835
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3176157573
Short name T72
Test name
Test status
Simulation time 212460117 ps
CPU time 1.61 seconds
Started Jul 02 09:44:31 AM PDT 24
Finished Jul 02 09:44:33 AM PDT 24
Peak memory 213264 kb
Host smart-76b9fee2-a20f-464a-b5b5-dbfa91d3fc8c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176157573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3176157573
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1624622170
Short name T82
Test name
Test status
Simulation time 314797561 ps
CPU time 2.6 seconds
Started Jul 02 09:44:32 AM PDT 24
Finished Jul 02 09:44:36 AM PDT 24
Peak memory 213240 kb
Host smart-23d6b00b-0006-4dfd-9b96-806162768480
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624622170 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1624622170
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1201344034
Short name T403
Test name
Test status
Simulation time 161279672 ps
CPU time 1.63 seconds
Started Jul 02 09:44:32 AM PDT 24
Finished Jul 02 09:44:35 AM PDT 24
Peak memory 213280 kb
Host smart-289e90a1-e1fc-4072-9850-914eab7d657b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201344034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1201344034
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4070313488
Short name T405
Test name
Test status
Simulation time 82695390527 ps
CPU time 72.18 seconds
Started Jul 02 09:44:28 AM PDT 24
Finished Jul 02 09:45:41 AM PDT 24
Peak memory 205028 kb
Host smart-4f3398c9-21db-4078-a615-4edbd509c441
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070313488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.4070313488
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2557779258
Short name T361
Test name
Test status
Simulation time 5925338430 ps
CPU time 17.55 seconds
Started Jul 02 09:44:29 AM PDT 24
Finished Jul 02 09:44:47 AM PDT 24
Peak memory 205024 kb
Host smart-2651a779-1e66-4336-9a96-583928e48a02
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557779258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.2557779258
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.869352336
Short name T95
Test name
Test status
Simulation time 10546536451 ps
CPU time 25.41 seconds
Started Jul 02 09:44:28 AM PDT 24
Finished Jul 02 09:44:54 AM PDT 24
Peak memory 205040 kb
Host smart-58f53dac-9a88-4d56-b05b-f45e8380b15b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869352336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.869352336
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3949364446
Short name T278
Test name
Test status
Simulation time 4550043003 ps
CPU time 6.8 seconds
Started Jul 02 09:44:28 AM PDT 24
Finished Jul 02 09:44:35 AM PDT 24
Peak memory 205000 kb
Host smart-38be752a-6912-449a-9c9e-c25e25b3ed89
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949364446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
949364446
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3021897770
Short name T78
Test name
Test status
Simulation time 1126172398 ps
CPU time 1.73 seconds
Started Jul 02 09:44:29 AM PDT 24
Finished Jul 02 09:44:32 AM PDT 24
Peak memory 204800 kb
Host smart-86e61ab0-919d-4c9b-96d8-f42154d142ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021897770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3021897770
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4291246892
Short name T281
Test name
Test status
Simulation time 31431289151 ps
CPU time 85.57 seconds
Started Jul 02 09:44:29 AM PDT 24
Finished Jul 02 09:45:56 AM PDT 24
Peak memory 205028 kb
Host smart-61bae6a0-7d85-4d7c-adb1-dea393e310b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291246892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.4291246892
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1978284976
Short name T297
Test name
Test status
Simulation time 392549569 ps
CPU time 1.56 seconds
Started Jul 02 09:44:29 AM PDT 24
Finished Jul 02 09:44:31 AM PDT 24
Peak memory 204772 kb
Host smart-6fc70851-e797-4743-bbee-21efb454d6a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978284976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1978284976
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2785225877
Short name T431
Test name
Test status
Simulation time 255103702 ps
CPU time 1.12 seconds
Started Jul 02 09:44:32 AM PDT 24
Finished Jul 02 09:44:33 AM PDT 24
Peak memory 204576 kb
Host smart-7a2fdd54-a41f-4d22-8b5a-d1ad3376379b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785225877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
785225877
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.260351651
Short name T308
Test name
Test status
Simulation time 100961498 ps
CPU time 0.8 seconds
Started Jul 02 09:44:27 AM PDT 24
Finished Jul 02 09:44:29 AM PDT 24
Peak memory 204712 kb
Host smart-c255cf3e-c25a-4446-a409-bab1f036892b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260351651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part
ial_access.260351651
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2288661842
Short name T295
Test name
Test status
Simulation time 62324962 ps
CPU time 0.66 seconds
Started Jul 02 09:44:29 AM PDT 24
Finished Jul 02 09:44:31 AM PDT 24
Peak memory 204776 kb
Host smart-f1954382-a1fc-40d7-86cf-b443b3565c02
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288661842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2288661842
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2197791542
Short name T393
Test name
Test status
Simulation time 169169740 ps
CPU time 3.56 seconds
Started Jul 02 09:44:34 AM PDT 24
Finished Jul 02 09:44:38 AM PDT 24
Peak memory 205004 kb
Host smart-f6518408-bb6e-417d-9856-55407631cf83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197791542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2197791542
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2083088628
Short name T385
Test name
Test status
Simulation time 20220878139 ps
CPU time 34.22 seconds
Started Jul 02 09:44:29 AM PDT 24
Finished Jul 02 09:45:03 AM PDT 24
Peak memory 221108 kb
Host smart-9477cdbc-8826-4e1c-baf9-b9e80e5498bc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083088628 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2083088628
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1429726763
Short name T400
Test name
Test status
Simulation time 321659917 ps
CPU time 5.83 seconds
Started Jul 02 09:44:32 AM PDT 24
Finished Jul 02 09:44:38 AM PDT 24
Peak memory 215448 kb
Host smart-1c6c78ad-ae82-443e-a90e-ae7705614443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429726763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1429726763
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.241155959
Short name T390
Test name
Test status
Simulation time 1974519063 ps
CPU time 10.67 seconds
Started Jul 02 09:44:28 AM PDT 24
Finished Jul 02 09:44:39 AM PDT 24
Peak memory 213300 kb
Host smart-ea087ee6-62fd-45cc-8f90-1cdb3df1c40b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241155959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.241155959
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1513140278
Short name T425
Test name
Test status
Simulation time 4735848451 ps
CPU time 33.29 seconds
Started Jul 02 09:44:36 AM PDT 24
Finished Jul 02 09:45:10 AM PDT 24
Peak memory 205072 kb
Host smart-d3294847-cbf8-4df5-a498-cfefcb669eae
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513140278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1513140278
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2188624948
Short name T108
Test name
Test status
Simulation time 7025417902 ps
CPU time 36.06 seconds
Started Jul 02 09:44:41 AM PDT 24
Finished Jul 02 09:45:18 AM PDT 24
Peak memory 213400 kb
Host smart-31a0a286-74dc-4a07-b82a-88de93092cec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188624948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2188624948
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1913467272
Short name T387
Test name
Test status
Simulation time 87204816 ps
CPU time 1.63 seconds
Started Jul 02 09:44:37 AM PDT 24
Finished Jul 02 09:44:39 AM PDT 24
Peak memory 213148 kb
Host smart-5a74a6a1-a6b9-46b7-a9d8-d078c3143ead
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913467272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1913467272
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.896607252
Short name T330
Test name
Test status
Simulation time 625626018 ps
CPU time 2.61 seconds
Started Jul 02 09:44:41 AM PDT 24
Finished Jul 02 09:44:44 AM PDT 24
Peak memory 218876 kb
Host smart-308401fa-c2a3-4a21-8cab-0067f5ba2477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896607252 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.896607252
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1212122235
Short name T415
Test name
Test status
Simulation time 121529604 ps
CPU time 2.3 seconds
Started Jul 02 09:44:37 AM PDT 24
Finished Jul 02 09:44:40 AM PDT 24
Peak memory 213336 kb
Host smart-973ed0b1-e8b3-44b3-92a6-2f97392d5e23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212122235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1212122235
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1172520420
Short name T392
Test name
Test status
Simulation time 104922549214 ps
CPU time 309.26 seconds
Started Jul 02 09:44:39 AM PDT 24
Finished Jul 02 09:49:48 AM PDT 24
Peak memory 205072 kb
Host smart-56c5507e-6742-4bc5-8bed-02392f2aabeb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172520420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1172520420
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1994265753
Short name T314
Test name
Test status
Simulation time 15960567357 ps
CPU time 44.19 seconds
Started Jul 02 09:44:38 AM PDT 24
Finished Jul 02 09:45:23 AM PDT 24
Peak memory 205008 kb
Host smart-3d45fa89-a5ea-4cd5-912a-6838f7de54fc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994265753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.1994265753
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4077524717
Short name T96
Test name
Test status
Simulation time 20686072762 ps
CPU time 15.61 seconds
Started Jul 02 09:44:33 AM PDT 24
Finished Jul 02 09:44:49 AM PDT 24
Peak memory 213240 kb
Host smart-756cbd52-e0e2-4c5e-98e4-65f11bfa061c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077524717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.4077524717
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.653446037
Short name T341
Test name
Test status
Simulation time 14293598769 ps
CPU time 27.02 seconds
Started Jul 02 09:44:36 AM PDT 24
Finished Jul 02 09:45:03 AM PDT 24
Peak memory 205036 kb
Host smart-65bc37ec-737c-4528-945d-5f1e1f1165f9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653446037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.653446037
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2142624855
Short name T291
Test name
Test status
Simulation time 1033192677 ps
CPU time 1.49 seconds
Started Jul 02 09:44:32 AM PDT 24
Finished Jul 02 09:44:34 AM PDT 24
Peak memory 204780 kb
Host smart-a7eb88f0-afd7-411c-9df1-9f54e165e405
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142624855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2142624855
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.958575274
Short name T301
Test name
Test status
Simulation time 2634982752 ps
CPU time 4.65 seconds
Started Jul 02 09:44:32 AM PDT 24
Finished Jul 02 09:44:38 AM PDT 24
Peak memory 205020 kb
Host smart-c2279f84-2d2c-4642-91e9-ff790e2e34a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958575274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.958575274
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.81465197
Short name T424
Test name
Test status
Simulation time 344610829 ps
CPU time 1.54 seconds
Started Jul 02 09:44:32 AM PDT 24
Finished Jul 02 09:44:34 AM PDT 24
Peak memory 204748 kb
Host smart-4ca71ee0-a2c5-4acc-8c89-93add812e3bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81465197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_
hw_reset.81465197
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3568647145
Short name T357
Test name
Test status
Simulation time 1124012006 ps
CPU time 1.59 seconds
Started Jul 02 09:44:32 AM PDT 24
Finished Jul 02 09:44:34 AM PDT 24
Peak memory 204780 kb
Host smart-065e1a73-03e0-4eeb-808d-b8e61b469166
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568647145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
568647145
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2930556711
Short name T416
Test name
Test status
Simulation time 67353372 ps
CPU time 0.67 seconds
Started Jul 02 09:44:37 AM PDT 24
Finished Jul 02 09:44:38 AM PDT 24
Peak memory 204700 kb
Host smart-86eae82b-2340-4e2a-8935-4438565b5b78
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930556711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2930556711
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.51609748
Short name T375
Test name
Test status
Simulation time 120129309 ps
CPU time 0.7 seconds
Started Jul 02 09:44:38 AM PDT 24
Finished Jul 02 09:44:39 AM PDT 24
Peak memory 204764 kb
Host smart-38cfdca3-5c48-4025-8247-f13a73a3ea60
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51609748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.51609748
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4024838203
Short name T89
Test name
Test status
Simulation time 7691264324 ps
CPU time 8.55 seconds
Started Jul 02 09:44:37 AM PDT 24
Finished Jul 02 09:44:46 AM PDT 24
Peak memory 205124 kb
Host smart-721cb541-3ee1-48d3-9c59-1067bda62870
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024838203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.4024838203
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4281443892
Short name T345
Test name
Test status
Simulation time 136600708 ps
CPU time 4.9 seconds
Started Jul 02 09:44:37 AM PDT 24
Finished Jul 02 09:44:42 AM PDT 24
Peak memory 213256 kb
Host smart-0d40622b-9e8a-47a3-9091-566d190b005e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281443892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4281443892
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3180439127
Short name T318
Test name
Test status
Simulation time 683864053 ps
CPU time 28.45 seconds
Started Jul 02 09:44:46 AM PDT 24
Finished Jul 02 09:45:15 AM PDT 24
Peak memory 213256 kb
Host smart-50fd7363-171c-4670-af5b-d7412a240962
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180439127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3180439127
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4100919820
Short name T363
Test name
Test status
Simulation time 3686098338 ps
CPU time 38.32 seconds
Started Jul 02 09:44:40 AM PDT 24
Finished Jul 02 09:45:19 AM PDT 24
Peak memory 205164 kb
Host smart-cc341f74-3147-43f3-8cc6-0d3a4672d2f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100919820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.4100919820
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2947189266
Short name T101
Test name
Test status
Simulation time 145083549 ps
CPU time 2.45 seconds
Started Jul 02 09:44:44 AM PDT 24
Finished Jul 02 09:44:46 AM PDT 24
Peak memory 213456 kb
Host smart-dac973bc-4e94-418f-9595-3e8b792cc09e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947189266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2947189266
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.412518075
Short name T323
Test name
Test status
Simulation time 3258815480 ps
CPU time 6.39 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:45:01 AM PDT 24
Peak memory 221524 kb
Host smart-a698b722-5d4e-4aa7-a0ee-817b8027c805
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412518075 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.412518075
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1800341632
Short name T395
Test name
Test status
Simulation time 107268887 ps
CPU time 1.51 seconds
Started Jul 02 09:44:45 AM PDT 24
Finished Jul 02 09:44:47 AM PDT 24
Peak memory 213248 kb
Host smart-99cf15f4-74d8-4831-bd55-d378c85d5f08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800341632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1800341632
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.826546509
Short name T324
Test name
Test status
Simulation time 38542990244 ps
CPU time 21.34 seconds
Started Jul 02 09:44:42 AM PDT 24
Finished Jul 02 09:45:04 AM PDT 24
Peak memory 205020 kb
Host smart-58a5b295-6b2f-4c5c-9524-f8544ac4473b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826546509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.826546509
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.713402186
Short name T389
Test name
Test status
Simulation time 21100488022 ps
CPU time 52.85 seconds
Started Jul 02 09:44:45 AM PDT 24
Finished Jul 02 09:45:38 AM PDT 24
Peak memory 204968 kb
Host smart-d3b12657-745b-4d10-af11-b84426a446d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713402186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.713402186
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3830239677
Short name T97
Test name
Test status
Simulation time 4300234761 ps
CPU time 8.26 seconds
Started Jul 02 09:44:46 AM PDT 24
Finished Jul 02 09:44:55 AM PDT 24
Peak memory 205120 kb
Host smart-2b8ac2f6-c306-47a7-a9e6-851d8651f6e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830239677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3830239677
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.476299937
Short name T382
Test name
Test status
Simulation time 3063112901 ps
CPU time 8.9 seconds
Started Jul 02 09:44:40 AM PDT 24
Finished Jul 02 09:44:49 AM PDT 24
Peak memory 205004 kb
Host smart-081f7d38-25ba-4248-b4fd-f4e7c84e28d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476299937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.476299937
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3777872276
Short name T299
Test name
Test status
Simulation time 442756866 ps
CPU time 0.79 seconds
Started Jul 02 09:44:46 AM PDT 24
Finished Jul 02 09:44:47 AM PDT 24
Peak memory 204756 kb
Host smart-b00ec25a-578e-422b-acaa-15f92bac1703
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777872276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3777872276
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.709163797
Short name T366
Test name
Test status
Simulation time 20052646461 ps
CPU time 54.53 seconds
Started Jul 02 09:44:41 AM PDT 24
Finished Jul 02 09:45:36 AM PDT 24
Peak memory 205040 kb
Host smart-5abdb799-c159-43bc-b1e8-8736e79a6a29
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709163797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.709163797
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.47088503
Short name T300
Test name
Test status
Simulation time 1016006499 ps
CPU time 3 seconds
Started Jul 02 09:44:44 AM PDT 24
Finished Jul 02 09:44:47 AM PDT 24
Peak memory 204772 kb
Host smart-1d409dce-01a3-455e-8a60-70d48b3feeef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47088503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_
hw_reset.47088503
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.742698983
Short name T339
Test name
Test status
Simulation time 130261371 ps
CPU time 1 seconds
Started Jul 02 09:44:42 AM PDT 24
Finished Jul 02 09:44:43 AM PDT 24
Peak memory 204784 kb
Host smart-392e79d5-f098-4328-a817-efe77451afbd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742698983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.742698983
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1965716716
Short name T276
Test name
Test status
Simulation time 50638460 ps
CPU time 0.73 seconds
Started Jul 02 09:44:43 AM PDT 24
Finished Jul 02 09:44:44 AM PDT 24
Peak memory 204692 kb
Host smart-041cc24e-a3cd-4ffc-b88d-1c28716a2412
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965716716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1965716716
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2425215026
Short name T349
Test name
Test status
Simulation time 29684943 ps
CPU time 0.73 seconds
Started Jul 02 09:44:41 AM PDT 24
Finished Jul 02 09:44:42 AM PDT 24
Peak memory 204728 kb
Host smart-d201998a-e83b-4388-8c9b-7e2a21f27142
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425215026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2425215026
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3902863375
Short name T102
Test name
Test status
Simulation time 574954350 ps
CPU time 8.02 seconds
Started Jul 02 09:44:51 AM PDT 24
Finished Jul 02 09:44:59 AM PDT 24
Peak memory 205060 kb
Host smart-01083b0d-fb7e-4224-9395-945261c5a0d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902863375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3902863375
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3950231133
Short name T358
Test name
Test status
Simulation time 21173688910 ps
CPU time 58.71 seconds
Started Jul 02 09:44:42 AM PDT 24
Finished Jul 02 09:45:41 AM PDT 24
Peak memory 221572 kb
Host smart-d866a675-f3da-4bd8-9110-b3bf83971b6b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950231133 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3950231133
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.111654803
Short name T354
Test name
Test status
Simulation time 1120404379 ps
CPU time 6.76 seconds
Started Jul 02 09:44:43 AM PDT 24
Finished Jul 02 09:44:50 AM PDT 24
Peak memory 213276 kb
Host smart-b9a87554-75b6-4349-86cb-78e085b9fe25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111654803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.111654803
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2671710702
Short name T422
Test name
Test status
Simulation time 3150470175 ps
CPU time 10.48 seconds
Started Jul 02 09:44:43 AM PDT 24
Finished Jul 02 09:44:53 AM PDT 24
Peak memory 213336 kb
Host smart-17d9c170-9497-4ba2-929e-aeb4e51991cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671710702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2671710702
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3744182914
Short name T79
Test name
Test status
Simulation time 1392352410 ps
CPU time 4.12 seconds
Started Jul 02 09:44:46 AM PDT 24
Finished Jul 02 09:44:51 AM PDT 24
Peak memory 217764 kb
Host smart-7f8c106f-8223-46ee-bfeb-f0327f5422c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744182914 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3744182914
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.296630987
Short name T391
Test name
Test status
Simulation time 470284149 ps
CPU time 2.2 seconds
Started Jul 02 09:44:48 AM PDT 24
Finished Jul 02 09:44:51 AM PDT 24
Peak memory 213236 kb
Host smart-b24c1482-d714-48d2-bce3-973abf92c1a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296630987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.296630987
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4003196385
Short name T302
Test name
Test status
Simulation time 17082678152 ps
CPU time 13.13 seconds
Started Jul 02 09:44:46 AM PDT 24
Finished Jul 02 09:45:00 AM PDT 24
Peak memory 205012 kb
Host smart-df6b5931-591d-413a-9a91-9010816abcc9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003196385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.4003196385
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4154028632
Short name T368
Test name
Test status
Simulation time 4578100235 ps
CPU time 12.36 seconds
Started Jul 02 09:44:46 AM PDT 24
Finished Jul 02 09:44:59 AM PDT 24
Peak memory 204908 kb
Host smart-2755c5b0-ad90-4171-9835-2b64be9c6488
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154028632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.4
154028632
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2602438944
Short name T303
Test name
Test status
Simulation time 137027118 ps
CPU time 0.83 seconds
Started Jul 02 09:44:48 AM PDT 24
Finished Jul 02 09:44:49 AM PDT 24
Peak memory 204756 kb
Host smart-403f6760-6688-4037-9831-0ddf30451834
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602438944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2
602438944
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3689303726
Short name T100
Test name
Test status
Simulation time 306121125 ps
CPU time 3.45 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:44:58 AM PDT 24
Peak memory 205024 kb
Host smart-ac8cec9d-b9e2-4f03-82e7-b50efb798b79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689303726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3689303726
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4014303684
Short name T332
Test name
Test status
Simulation time 783833811 ps
CPU time 6.34 seconds
Started Jul 02 09:44:51 AM PDT 24
Finished Jul 02 09:44:58 AM PDT 24
Peak memory 221376 kb
Host smart-8578c467-9af9-4fe8-8aa1-5ee3b475fce5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014303684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.4014303684
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.428666121
Short name T67
Test name
Test status
Simulation time 2013680957 ps
CPU time 22.99 seconds
Started Jul 02 09:44:44 AM PDT 24
Finished Jul 02 09:45:08 AM PDT 24
Peak memory 213360 kb
Host smart-03b08a24-e3eb-4fe4-8f36-bbfa229eeef7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428666121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.428666121
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.159945305
Short name T360
Test name
Test status
Simulation time 2094859853 ps
CPU time 4.17 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:44:59 AM PDT 24
Peak memory 215804 kb
Host smart-8849c7e2-fc48-461a-9b52-a1675a1de981
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159945305 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.159945305
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3107033038
Short name T104
Test name
Test status
Simulation time 1122227425 ps
CPU time 2.46 seconds
Started Jul 02 09:44:54 AM PDT 24
Finished Jul 02 09:44:57 AM PDT 24
Peak memory 213264 kb
Host smart-3fba46b0-390d-47db-942a-26ce8f4b047a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107033038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3107033038
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3759166581
Short name T413
Test name
Test status
Simulation time 16870497769 ps
CPU time 34.27 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:45:29 AM PDT 24
Peak memory 205016 kb
Host smart-ee8f7c57-5dfe-4ec4-9292-ac0c79ceb380
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759166581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.3759166581
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.427563403
Short name T377
Test name
Test status
Simulation time 1109158734 ps
CPU time 1.63 seconds
Started Jul 02 09:44:51 AM PDT 24
Finished Jul 02 09:44:53 AM PDT 24
Peak memory 204888 kb
Host smart-ee4a572c-d0af-41d4-9e4a-0f2af949c255
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427563403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.427563403
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2111138490
Short name T362
Test name
Test status
Simulation time 247900534 ps
CPU time 0.89 seconds
Started Jul 02 09:44:45 AM PDT 24
Finished Jul 02 09:44:46 AM PDT 24
Peak memory 204736 kb
Host smart-71c0dc74-05d4-43cc-9638-7b636f6cb110
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111138490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
111138490
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3290778798
Short name T115
Test name
Test status
Simulation time 632506770 ps
CPU time 7.97 seconds
Started Jul 02 09:44:45 AM PDT 24
Finished Jul 02 09:44:54 AM PDT 24
Peak memory 205136 kb
Host smart-5ce08bb7-0fb0-4c52-b4b2-8ef81be48d39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290778798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3290778798
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3797973011
Short name T351
Test name
Test status
Simulation time 53791151678 ps
CPU time 58.84 seconds
Started Jul 02 09:44:52 AM PDT 24
Finished Jul 02 09:45:51 AM PDT 24
Peak memory 222564 kb
Host smart-b7d54527-e9e5-4fa4-a7c7-e8162e9f6526
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797973011 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3797973011
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2648231260
Short name T428
Test name
Test status
Simulation time 629003684 ps
CPU time 5.37 seconds
Started Jul 02 09:44:46 AM PDT 24
Finished Jul 02 09:44:52 AM PDT 24
Peak memory 213184 kb
Host smart-91cd42cd-f327-45bd-847a-dd5d2dc5495d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648231260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2648231260
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1474852394
Short name T157
Test name
Test status
Simulation time 874953843 ps
CPU time 9.85 seconds
Started Jul 02 09:44:51 AM PDT 24
Finished Jul 02 09:45:02 AM PDT 24
Peak memory 213288 kb
Host smart-1cb896c3-e464-476a-9791-c4a83c4735b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474852394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1474852394
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1783227768
Short name T81
Test name
Test status
Simulation time 2741279154 ps
CPU time 2.98 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:44:57 AM PDT 24
Peak memory 215820 kb
Host smart-52fd5221-3e6b-4948-9e65-e8b761f0c82d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783227768 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1783227768
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4130204695
Short name T105
Test name
Test status
Simulation time 911920749 ps
CPU time 2.57 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:44:56 AM PDT 24
Peak memory 213288 kb
Host smart-1aac6313-758b-47ce-baa8-3c520ce1f4bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130204695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.4130204695
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.418028840
Short name T290
Test name
Test status
Simulation time 40081603374 ps
CPU time 11.62 seconds
Started Jul 02 09:44:52 AM PDT 24
Finished Jul 02 09:45:04 AM PDT 24
Peak memory 204992 kb
Host smart-a86783f6-fa57-41cb-8f55-59ad3d0c474c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418028840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r
v_dm_jtag_dmi_csr_bit_bash.418028840
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1230420629
Short name T292
Test name
Test status
Simulation time 2773836041 ps
CPU time 3.36 seconds
Started Jul 02 09:44:48 AM PDT 24
Finished Jul 02 09:44:52 AM PDT 24
Peak memory 204984 kb
Host smart-4236133d-d77c-4b0b-9c96-a25630a8e304
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230420629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
230420629
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2635768239
Short name T317
Test name
Test status
Simulation time 872917199 ps
CPU time 1.8 seconds
Started Jul 02 09:44:50 AM PDT 24
Finished Jul 02 09:44:52 AM PDT 24
Peak memory 204724 kb
Host smart-0584b16c-0460-447e-b6f7-5792f4791e6b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635768239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
635768239
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.594060859
Short name T378
Test name
Test status
Simulation time 481205454 ps
CPU time 3.97 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:44:57 AM PDT 24
Peak memory 205064 kb
Host smart-5ad7f037-51aa-4444-9f92-f7f97fa23653
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594060859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.594060859
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4130780321
Short name T60
Test name
Test status
Simulation time 41281698383 ps
CPU time 117.36 seconds
Started Jul 02 09:44:52 AM PDT 24
Finished Jul 02 09:46:49 AM PDT 24
Peak memory 221540 kb
Host smart-0b6011ec-8ab4-4c5f-96d6-4bacf132e9dc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130780321 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.4130780321
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4184950876
Short name T68
Test name
Test status
Simulation time 268672539 ps
CPU time 4.68 seconds
Started Jul 02 09:44:51 AM PDT 24
Finished Jul 02 09:44:56 AM PDT 24
Peak memory 213220 kb
Host smart-82b72b1d-76fc-474d-abcb-1034edad578e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184950876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.4184950876
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1660939961
Short name T156
Test name
Test status
Simulation time 789267551 ps
CPU time 9.38 seconds
Started Jul 02 09:44:55 AM PDT 24
Finished Jul 02 09:45:05 AM PDT 24
Peak memory 213304 kb
Host smart-707cdb15-b52a-4d18-9990-67f0abc4eb13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660939961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1660939961
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3231232382
Short name T420
Test name
Test status
Simulation time 329433800 ps
CPU time 3.76 seconds
Started Jul 02 09:44:56 AM PDT 24
Finished Jul 02 09:45:00 AM PDT 24
Peak memory 221412 kb
Host smart-7d82c1f1-2312-483b-9528-08b2eef3e80f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231232382 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3231232382
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3240005984
Short name T408
Test name
Test status
Simulation time 59552115 ps
CPU time 2.29 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:44:57 AM PDT 24
Peak memory 213256 kb
Host smart-bd2f50b9-e7fa-45d9-afe2-a362f6ba6704
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240005984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3240005984
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.900476464
Short name T343
Test name
Test status
Simulation time 5489451492 ps
CPU time 8.12 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:45:02 AM PDT 24
Peak memory 204988 kb
Host smart-3665328c-0ebc-461d-bda5-dd30b7d6f6bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900476464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
v_dm_jtag_dmi_csr_bit_bash.900476464
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1960949824
Short name T414
Test name
Test status
Simulation time 1382113841 ps
CPU time 2.27 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:44:55 AM PDT 24
Peak memory 204924 kb
Host smart-0c98d2af-b958-475f-9846-fa203e9dfa09
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960949824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
960949824
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3525734704
Short name T359
Test name
Test status
Simulation time 253836562 ps
CPU time 0.76 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:44:55 AM PDT 24
Peak memory 204756 kb
Host smart-b95f687d-25b7-4996-9e74-e445a8c5e546
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525734704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
525734704
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1306742281
Short name T85
Test name
Test status
Simulation time 293449653 ps
CPU time 3.61 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:44:58 AM PDT 24
Peak memory 205164 kb
Host smart-9f304af3-db3f-429e-b504-23012ce0ac65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306742281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1306742281
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1777681011
Short name T80
Test name
Test status
Simulation time 166119908 ps
CPU time 3.02 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:44:56 AM PDT 24
Peak memory 215816 kb
Host smart-a7940ea5-9689-4922-a5da-be0e9f47d53a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777681011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1777681011
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2552130602
Short name T163
Test name
Test status
Simulation time 1937392606 ps
CPU time 18.46 seconds
Started Jul 02 09:44:52 AM PDT 24
Finished Jul 02 09:45:10 AM PDT 24
Peak memory 213276 kb
Host smart-abd2cf86-410a-4b22-becd-f72b8a573439
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552130602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2552130602
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3239237022
Short name T83
Test name
Test status
Simulation time 4249634449 ps
CPU time 8.76 seconds
Started Jul 02 09:44:59 AM PDT 24
Finished Jul 02 09:45:09 AM PDT 24
Peak memory 221580 kb
Host smart-6b4972b2-f243-41b5-aee1-e0fe76e2852e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239237022 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3239237022
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1289686646
Short name T399
Test name
Test status
Simulation time 320808295 ps
CPU time 1.63 seconds
Started Jul 02 09:44:56 AM PDT 24
Finished Jul 02 09:44:58 AM PDT 24
Peak memory 213200 kb
Host smart-a2da381c-1e69-4a83-833a-a1c485b7b793
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289686646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1289686646
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.219077873
Short name T312
Test name
Test status
Simulation time 13524964781 ps
CPU time 33.85 seconds
Started Jul 02 09:44:55 AM PDT 24
Finished Jul 02 09:45:30 AM PDT 24
Peak memory 205012 kb
Host smart-ffe9ba2c-ef74-4ac2-8f72-47a1a29733a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219077873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r
v_dm_jtag_dmi_csr_bit_bash.219077873
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2528865515
Short name T294
Test name
Test status
Simulation time 1546287588 ps
CPU time 1.87 seconds
Started Jul 02 09:44:55 AM PDT 24
Finished Jul 02 09:44:57 AM PDT 24
Peak memory 204964 kb
Host smart-2c022f4c-6ea0-4925-a76f-4cabd10b5fc5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528865515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
528865515
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2780328973
Short name T407
Test name
Test status
Simulation time 498326489 ps
CPU time 2.02 seconds
Started Jul 02 09:44:55 AM PDT 24
Finished Jul 02 09:44:58 AM PDT 24
Peak memory 204792 kb
Host smart-018a6c1c-6f28-4117-98d6-fdaf6d4e8fc7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780328973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
780328973
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.82776431
Short name T373
Test name
Test status
Simulation time 552763328 ps
CPU time 6.51 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:45:01 AM PDT 24
Peak memory 205124 kb
Host smart-1ff71692-efbc-4364-bb41-22924c7951e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82776431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_cs
r_outstanding.82776431
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3925631454
Short name T347
Test name
Test status
Simulation time 58155538041 ps
CPU time 106.5 seconds
Started Jul 02 09:44:56 AM PDT 24
Finished Jul 02 09:46:43 AM PDT 24
Peak memory 222868 kb
Host smart-ef26e402-e89c-4ee1-82db-dab64a9b8f28
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925631454 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3925631454
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2149767840
Short name T306
Test name
Test status
Simulation time 172813816 ps
CPU time 3.41 seconds
Started Jul 02 09:44:53 AM PDT 24
Finished Jul 02 09:44:57 AM PDT 24
Peak memory 213248 kb
Host smart-fac617bc-39ed-462c-ba96-0b7950f5226b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149767840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2149767840
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.728446348
Short name T192
Test name
Test status
Simulation time 89427617 ps
CPU time 0.77 seconds
Started Jul 02 09:45:20 AM PDT 24
Finished Jul 02 09:45:21 AM PDT 24
Peak memory 204992 kb
Host smart-389b3a5a-c61b-40b2-bfd2-a61418928fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728446348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.728446348
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.595884427
Short name T188
Test name
Test status
Simulation time 6321124670 ps
CPU time 18.41 seconds
Started Jul 02 09:45:14 AM PDT 24
Finished Jul 02 09:45:33 AM PDT 24
Peak memory 213652 kb
Host smart-2b86dce7-4e77-4350-bb8f-15ae5f51a07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595884427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.595884427
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1451446368
Short name T274
Test name
Test status
Simulation time 13370314182 ps
CPU time 9.14 seconds
Started Jul 02 09:45:10 AM PDT 24
Finished Jul 02 09:45:20 AM PDT 24
Peak memory 213596 kb
Host smart-73ad030f-0a0a-4c97-96e1-4ca58ad3062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451446368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1451446368
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1265624874
Short name T22
Test name
Test status
Simulation time 306398276 ps
CPU time 1.28 seconds
Started Jul 02 09:45:14 AM PDT 24
Finished Jul 02 09:45:16 AM PDT 24
Peak memory 204932 kb
Host smart-315ddc72-92e9-440c-9600-a848226ad7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265624874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1265624874
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1232807624
Short name T171
Test name
Test status
Simulation time 268521914 ps
CPU time 0.95 seconds
Started Jul 02 09:45:15 AM PDT 24
Finished Jul 02 09:45:16 AM PDT 24
Peak memory 205000 kb
Host smart-2ed788f2-c8a3-4ea8-b10f-72f18b3bf8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232807624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1232807624
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2221963270
Short name T167
Test name
Test status
Simulation time 337231299 ps
CPU time 1.12 seconds
Started Jul 02 09:45:15 AM PDT 24
Finished Jul 02 09:45:17 AM PDT 24
Peak memory 204968 kb
Host smart-9b38ea58-2c60-42f4-ba93-c84cd449a031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221963270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2221963270
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.2487079943
Short name T40
Test name
Test status
Simulation time 143861848 ps
CPU time 0.83 seconds
Started Jul 02 09:45:22 AM PDT 24
Finished Jul 02 09:45:23 AM PDT 24
Peak memory 215692 kb
Host smart-00642ba7-ab58-4745-a4bc-82f67e4463a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487079943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2487079943
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3371031372
Short name T135
Test name
Test status
Simulation time 1412977950 ps
CPU time 3.06 seconds
Started Jul 02 09:45:12 AM PDT 24
Finished Jul 02 09:45:16 AM PDT 24
Peak memory 205464 kb
Host smart-5e24adbd-7b32-48f4-a7d6-ce4272cd924d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3371031372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3371031372
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.270049448
Short name T7
Test name
Test status
Simulation time 441749393 ps
CPU time 1.93 seconds
Started Jul 02 09:45:15 AM PDT 24
Finished Jul 02 09:45:18 AM PDT 24
Peak memory 204988 kb
Host smart-e9208c13-a713-462d-b88e-8a53354b1898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270049448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.270049448
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.997362152
Short name T249
Test name
Test status
Simulation time 927864426 ps
CPU time 1.3 seconds
Started Jul 02 09:45:13 AM PDT 24
Finished Jul 02 09:45:15 AM PDT 24
Peak memory 204976 kb
Host smart-5713d241-aa4f-4ca4-aaa4-187d15d058dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997362152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.997362152
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.86410304
Short name T265
Test name
Test status
Simulation time 782338847 ps
CPU time 1.87 seconds
Started Jul 02 09:45:16 AM PDT 24
Finished Jul 02 09:45:19 AM PDT 24
Peak memory 204976 kb
Host smart-66010884-7acc-4af3-aa3f-c0e2af2ad6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86410304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.86410304
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2116862305
Short name T237
Test name
Test status
Simulation time 1048098469 ps
CPU time 1.77 seconds
Started Jul 02 09:45:16 AM PDT 24
Finished Jul 02 09:45:18 AM PDT 24
Peak memory 205004 kb
Host smart-ffc7dd5a-5372-48a3-9912-59d20006f9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116862305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2116862305
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2709455024
Short name T208
Test name
Test status
Simulation time 969325748 ps
CPU time 3.4 seconds
Started Jul 02 09:45:24 AM PDT 24
Finished Jul 02 09:45:28 AM PDT 24
Peak memory 204984 kb
Host smart-f3e93fbb-7461-45cb-81f1-8449484bc0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709455024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2709455024
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3636761753
Short name T236
Test name
Test status
Simulation time 271360052 ps
CPU time 0.99 seconds
Started Jul 02 09:45:14 AM PDT 24
Finished Jul 02 09:45:16 AM PDT 24
Peak memory 204920 kb
Host smart-7377df83-81b0-4fc9-8003-5707165b28ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636761753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3636761753
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1615613830
Short name T166
Test name
Test status
Simulation time 1411561627 ps
CPU time 2.59 seconds
Started Jul 02 09:45:15 AM PDT 24
Finished Jul 02 09:45:19 AM PDT 24
Peak memory 205000 kb
Host smart-022bbd70-3fe4-46b9-8069-5a3ee72e3dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615613830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1615613830
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.210591799
Short name T168
Test name
Test status
Simulation time 2236490354 ps
CPU time 3.73 seconds
Started Jul 02 09:45:15 AM PDT 24
Finished Jul 02 09:45:20 AM PDT 24
Peak memory 205056 kb
Host smart-eb5b36fe-63f7-4238-95b5-4b1f8c337cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210591799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.210591799
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2433393993
Short name T30
Test name
Test status
Simulation time 158441779 ps
CPU time 0.88 seconds
Started Jul 02 09:45:15 AM PDT 24
Finished Jul 02 09:45:17 AM PDT 24
Peak memory 205000 kb
Host smart-680002bd-79e7-40e6-aff7-12781e860601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433393993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2433393993
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2924670682
Short name T56
Test name
Test status
Simulation time 327441476 ps
CPU time 1.55 seconds
Started Jul 02 09:45:24 AM PDT 24
Finished Jul 02 09:45:27 AM PDT 24
Peak memory 204980 kb
Host smart-9427ff84-19ee-4415-956e-01b06ea75deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924670682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2924670682
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3360931075
Short name T52
Test name
Test status
Simulation time 87155038 ps
CPU time 0.82 seconds
Started Jul 02 09:45:25 AM PDT 24
Finished Jul 02 09:45:26 AM PDT 24
Peak memory 213260 kb
Host smart-4963db39-45dd-4a82-aba8-e0cfbdc6d4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360931075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3360931075
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3297281255
Short name T240
Test name
Test status
Simulation time 5328615994 ps
CPU time 7.9 seconds
Started Jul 02 09:45:14 AM PDT 24
Finished Jul 02 09:45:23 AM PDT 24
Peak memory 213344 kb
Host smart-a6763656-0cb8-40c1-bbbc-0b20cafb4ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297281255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3297281255
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.1274956966
Short name T38
Test name
Test status
Simulation time 2895750340 ps
CPU time 3.27 seconds
Started Jul 02 09:45:21 AM PDT 24
Finished Jul 02 09:45:25 AM PDT 24
Peak memory 237172 kb
Host smart-309396aa-99ce-4eff-85ef-8f785003fd3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274956966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1274956966
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2683814062
Short name T199
Test name
Test status
Simulation time 3912854848 ps
CPU time 3.89 seconds
Started Jul 02 09:45:14 AM PDT 24
Finished Jul 02 09:45:18 AM PDT 24
Peak memory 205192 kb
Host smart-af0581b0-b3e4-48cf-b165-280641c0763d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683814062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2683814062
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1787727054
Short name T273
Test name
Test status
Simulation time 94769498 ps
CPU time 0.76 seconds
Started Jul 02 09:45:25 AM PDT 24
Finished Jul 02 09:45:27 AM PDT 24
Peak memory 204992 kb
Host smart-caf8761c-cedc-425d-9296-5396e929a701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787727054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1787727054
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.840821017
Short name T197
Test name
Test status
Simulation time 12318870393 ps
CPU time 34.95 seconds
Started Jul 02 09:45:23 AM PDT 24
Finished Jul 02 09:45:59 AM PDT 24
Peak memory 213584 kb
Host smart-127f09db-083a-4bb1-a33c-d3b2be57ee2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840821017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.840821017
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.634508826
Short name T50
Test name
Test status
Simulation time 867264118 ps
CPU time 3.04 seconds
Started Jul 02 09:45:24 AM PDT 24
Finished Jul 02 09:45:28 AM PDT 24
Peak memory 204964 kb
Host smart-88023f16-8ef1-4766-a0cc-b7b987a2f8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634508826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.634508826
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2430652791
Short name T34
Test name
Test status
Simulation time 179596853 ps
CPU time 0.79 seconds
Started Jul 02 09:45:20 AM PDT 24
Finished Jul 02 09:45:21 AM PDT 24
Peak memory 204992 kb
Host smart-a650bf44-3fa4-4e1d-81e6-d6c3b30d95e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430652791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2430652791
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1268346608
Short name T165
Test name
Test status
Simulation time 176338703 ps
CPU time 1.03 seconds
Started Jul 02 09:45:21 AM PDT 24
Finished Jul 02 09:45:23 AM PDT 24
Peak memory 204924 kb
Host smart-dea3ea6b-a7be-47b9-b51d-3237673e2274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268346608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1268346608
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.426219801
Short name T44
Test name
Test status
Simulation time 2807712645 ps
CPU time 3.11 seconds
Started Jul 02 09:45:19 AM PDT 24
Finished Jul 02 09:45:23 AM PDT 24
Peak memory 213532 kb
Host smart-9fb05fad-6310-4035-823e-66cbcb2e76ae
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=426219801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl
_access.426219801
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3182784793
Short name T124
Test name
Test status
Simulation time 590184326 ps
CPU time 2.03 seconds
Started Jul 02 09:45:25 AM PDT 24
Finished Jul 02 09:45:28 AM PDT 24
Peak memory 204988 kb
Host smart-f6caf48a-25cb-4caa-b6a9-7419b9dd986e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182784793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3182784793
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1553275135
Short name T245
Test name
Test status
Simulation time 68295636 ps
CPU time 0.82 seconds
Started Jul 02 09:45:26 AM PDT 24
Finished Jul 02 09:45:28 AM PDT 24
Peak memory 204984 kb
Host smart-26be0ae1-c029-4791-90d1-a9f71109b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553275135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1553275135
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.719898624
Short name T10
Test name
Test status
Simulation time 1278089804 ps
CPU time 1.61 seconds
Started Jul 02 09:45:26 AM PDT 24
Finished Jul 02 09:45:29 AM PDT 24
Peak memory 204968 kb
Host smart-c6c78f57-0e23-4c53-82d2-e8a3ddfc30ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719898624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.719898624
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1561783048
Short name T264
Test name
Test status
Simulation time 592071680 ps
CPU time 1.16 seconds
Started Jul 02 09:45:27 AM PDT 24
Finished Jul 02 09:45:29 AM PDT 24
Peak memory 204980 kb
Host smart-323d9c23-6624-48c6-956a-15b9e4464f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561783048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1561783048
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.56117322
Short name T174
Test name
Test status
Simulation time 153617658 ps
CPU time 1.1 seconds
Started Jul 02 09:45:25 AM PDT 24
Finished Jul 02 09:45:27 AM PDT 24
Peak memory 204976 kb
Host smart-a85ca3c6-7e70-43b7-b2bb-28ef2d3f34af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56117322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.56117322
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2949828677
Short name T61
Test name
Test status
Simulation time 140705906 ps
CPU time 0.95 seconds
Started Jul 02 09:45:30 AM PDT 24
Finished Jul 02 09:45:32 AM PDT 24
Peak memory 204980 kb
Host smart-9bce4ee6-2ad4-4e90-9828-27c93edabc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949828677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2949828677
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3693107514
Short name T125
Test name
Test status
Simulation time 376321473 ps
CPU time 1.05 seconds
Started Jul 02 09:45:21 AM PDT 24
Finished Jul 02 09:45:23 AM PDT 24
Peak memory 204972 kb
Host smart-11944026-a37b-4a91-b211-f2c98a2428e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693107514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3693107514
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.2454820529
Short name T25
Test name
Test status
Simulation time 781863057 ps
CPU time 1.7 seconds
Started Jul 02 09:45:25 AM PDT 24
Finished Jul 02 09:45:27 AM PDT 24
Peak memory 204948 kb
Host smart-75ce8f65-5b86-4834-bc73-58781f55ae22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454820529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2454820529
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2413149050
Short name T3
Test name
Test status
Simulation time 5175488344 ps
CPU time 14.65 seconds
Started Jul 02 09:45:21 AM PDT 24
Finished Jul 02 09:45:37 AM PDT 24
Peak memory 205332 kb
Host smart-f0576970-c8e0-4cd9-96ad-b8befed377b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413149050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2413149050
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.1923235650
Short name T45
Test name
Test status
Simulation time 2182044002 ps
CPU time 5.82 seconds
Started Jul 02 09:45:26 AM PDT 24
Finished Jul 02 09:45:32 AM PDT 24
Peak memory 237272 kb
Host smart-b8a60f03-dd57-465f-a1bc-6360aad5d221
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923235650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1923235650
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3525946524
Short name T190
Test name
Test status
Simulation time 1008596089 ps
CPU time 0.97 seconds
Started Jul 02 09:45:23 AM PDT 24
Finished Jul 02 09:45:24 AM PDT 24
Peak memory 204952 kb
Host smart-5376d951-9869-4b44-bd56-b3a2391ee3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525946524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3525946524
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.2203195491
Short name T15
Test name
Test status
Simulation time 8748941316 ps
CPU time 25.02 seconds
Started Jul 02 09:45:24 AM PDT 24
Finished Jul 02 09:45:50 AM PDT 24
Peak memory 213424 kb
Host smart-4536aa9f-9da8-4030-be97-50dde74ad547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203195491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2203195491
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3048277553
Short name T262
Test name
Test status
Simulation time 75028825 ps
CPU time 0.79 seconds
Started Jul 02 09:45:36 AM PDT 24
Finished Jul 02 09:45:39 AM PDT 24
Peak memory 204996 kb
Host smart-e834e56a-69f0-45d5-aba7-25528814ed34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048277553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3048277553
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2141063509
Short name T257
Test name
Test status
Simulation time 14869922566 ps
CPU time 13.4 seconds
Started Jul 02 09:45:36 AM PDT 24
Finished Jul 02 09:45:52 AM PDT 24
Peak memory 213592 kb
Host smart-19375178-d29a-4c48-8e7f-52e6805ba25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141063509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2141063509
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2166429670
Short name T126
Test name
Test status
Simulation time 1482883035 ps
CPU time 2.03 seconds
Started Jul 02 09:45:36 AM PDT 24
Finished Jul 02 09:45:40 AM PDT 24
Peak memory 213496 kb
Host smart-8d4bbdf6-b8fc-4c4d-a704-3e0ac1f3057f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166429670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2166429670
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3930445859
Short name T231
Test name
Test status
Simulation time 1194440542 ps
CPU time 4.43 seconds
Started Jul 02 09:45:35 AM PDT 24
Finished Jul 02 09:45:41 AM PDT 24
Peak memory 213552 kb
Host smart-47ad5e92-e8bc-46d2-8e83-4b82f6108b35
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3930445859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3930445859
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.2329983497
Short name T261
Test name
Test status
Simulation time 3846444485 ps
CPU time 10.44 seconds
Started Jul 02 09:45:39 AM PDT 24
Finished Jul 02 09:45:51 AM PDT 24
Peak memory 205320 kb
Host smart-eadae480-048f-46ad-a135-c25e364d5c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329983497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.2329983497
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.3269792391
Short name T13
Test name
Test status
Simulation time 14067316394 ps
CPU time 5.49 seconds
Started Jul 02 09:45:36 AM PDT 24
Finished Jul 02 09:45:44 AM PDT 24
Peak memory 213496 kb
Host smart-ce01c5af-e2fd-4bf0-aee7-da12345314e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269792391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3269792391
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3429629929
Short name T37
Test name
Test status
Simulation time 95032799 ps
CPU time 0.83 seconds
Started Jul 02 09:45:36 AM PDT 24
Finished Jul 02 09:45:38 AM PDT 24
Peak memory 204972 kb
Host smart-1d0102d2-7296-490c-8798-a5dd877e0781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429629929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3429629929
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.262411282
Short name T241
Test name
Test status
Simulation time 4014848257 ps
CPU time 12 seconds
Started Jul 02 09:45:38 AM PDT 24
Finished Jul 02 09:45:51 AM PDT 24
Peak memory 215788 kb
Host smart-a7a4b4e9-0799-40cd-96ce-05d5a5c68e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262411282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.262411282
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1690311886
Short name T269
Test name
Test status
Simulation time 5864349922 ps
CPU time 4.37 seconds
Started Jul 02 09:45:37 AM PDT 24
Finished Jul 02 09:45:43 AM PDT 24
Peak memory 213540 kb
Host smart-adbe8579-fc2d-4a3d-84fa-7f2e1edcf3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690311886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1690311886
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.112816957
Short name T239
Test name
Test status
Simulation time 775369990 ps
CPU time 2.78 seconds
Started Jul 02 09:45:36 AM PDT 24
Finished Jul 02 09:45:40 AM PDT 24
Peak memory 205356 kb
Host smart-4ca7966e-0beb-4b30-b116-c66317ecea95
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112816957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.112816957
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3293175673
Short name T179
Test name
Test status
Simulation time 3752854459 ps
CPU time 2.35 seconds
Started Jul 02 09:45:36 AM PDT 24
Finished Jul 02 09:45:40 AM PDT 24
Peak memory 213604 kb
Host smart-01186d71-7c20-4cc4-b233-1e6fe5319730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293175673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3293175673
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1478871282
Short name T247
Test name
Test status
Simulation time 49703410 ps
CPU time 0.77 seconds
Started Jul 02 09:45:41 AM PDT 24
Finished Jul 02 09:45:43 AM PDT 24
Peak memory 204988 kb
Host smart-3ac20745-b716-4e79-80dd-92050776c188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478871282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1478871282
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.367112603
Short name T230
Test name
Test status
Simulation time 13589961184 ps
CPU time 17.38 seconds
Started Jul 02 09:45:35 AM PDT 24
Finished Jul 02 09:45:55 AM PDT 24
Peak memory 213524 kb
Host smart-01f714a8-2bbb-4c90-8404-861e5c50adee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367112603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.367112603
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1661124188
Short name T43
Test name
Test status
Simulation time 1091483965 ps
CPU time 4.01 seconds
Started Jul 02 09:45:35 AM PDT 24
Finished Jul 02 09:45:41 AM PDT 24
Peak memory 205256 kb
Host smart-35d3ef42-4bb0-4b71-bf8b-e3a46b6bf3bf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1661124188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1661124188
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.4223042094
Short name T216
Test name
Test status
Simulation time 5831274142 ps
CPU time 15.78 seconds
Started Jul 02 09:45:37 AM PDT 24
Finished Jul 02 09:45:54 AM PDT 24
Peak memory 205360 kb
Host smart-98718954-7f33-4485-ae0a-b525c8727e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223042094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.4223042094
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.4141883850
Short name T271
Test name
Test status
Simulation time 59216698 ps
CPU time 0.71 seconds
Started Jul 02 09:45:39 AM PDT 24
Finished Jul 02 09:45:41 AM PDT 24
Peak memory 204984 kb
Host smart-6d748d32-91a4-487b-bd9a-2142df7598f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141883850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4141883850
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3001781291
Short name T207
Test name
Test status
Simulation time 1943711578 ps
CPU time 3.68 seconds
Started Jul 02 09:45:42 AM PDT 24
Finished Jul 02 09:45:47 AM PDT 24
Peak memory 213456 kb
Host smart-750c9161-7e6e-4030-8d71-5423edaeee26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001781291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3001781291
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.965080005
Short name T232
Test name
Test status
Simulation time 2940313249 ps
CPU time 6.49 seconds
Started Jul 02 09:45:43 AM PDT 24
Finished Jul 02 09:45:51 AM PDT 24
Peak memory 213512 kb
Host smart-1cd33bf3-15b1-462c-8b55-148862ab7349
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965080005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.965080005
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3253030293
Short name T272
Test name
Test status
Simulation time 1019160891 ps
CPU time 3.05 seconds
Started Jul 02 09:45:40 AM PDT 24
Finished Jul 02 09:45:45 AM PDT 24
Peak memory 205228 kb
Host smart-4d06ed10-5bdf-4d24-95a6-c439cacc2091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253030293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3253030293
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1002635714
Short name T180
Test name
Test status
Simulation time 63412617 ps
CPU time 0.77 seconds
Started Jul 02 09:45:40 AM PDT 24
Finished Jul 02 09:45:43 AM PDT 24
Peak memory 204976 kb
Host smart-4a951df0-07e2-4af2-aa51-311c0f23600b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002635714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1002635714
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3233484534
Short name T33
Test name
Test status
Simulation time 14620184427 ps
CPU time 22.74 seconds
Started Jul 02 09:45:39 AM PDT 24
Finished Jul 02 09:46:04 AM PDT 24
Peak memory 213592 kb
Host smart-f5609312-c5a8-4a92-8b68-192f67f95169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233484534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3233484534
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2175379687
Short name T47
Test name
Test status
Simulation time 6169343092 ps
CPU time 17.87 seconds
Started Jul 02 09:45:41 AM PDT 24
Finished Jul 02 09:46:01 AM PDT 24
Peak memory 213600 kb
Host smart-33541eb7-7157-4ccc-824b-f8042f884700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175379687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2175379687
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3034682652
Short name T228
Test name
Test status
Simulation time 3121158646 ps
CPU time 3.49 seconds
Started Jul 02 09:45:40 AM PDT 24
Finished Jul 02 09:45:45 AM PDT 24
Peak memory 205280 kb
Host smart-c6ce5c08-23b5-42d0-9e64-d641bb046f9f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3034682652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3034682652
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.3606626110
Short name T253
Test name
Test status
Simulation time 3455488840 ps
CPU time 3.37 seconds
Started Jul 02 09:45:41 AM PDT 24
Finished Jul 02 09:45:46 AM PDT 24
Peak memory 213548 kb
Host smart-4a938496-7e8b-426e-a8af-d363872e832d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606626110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3606626110
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3236973623
Short name T254
Test name
Test status
Simulation time 135251082 ps
CPU time 1.01 seconds
Started Jul 02 09:45:44 AM PDT 24
Finished Jul 02 09:45:47 AM PDT 24
Peak memory 204984 kb
Host smart-b35dfe6c-bb51-423f-97c9-858f80c2d7cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236973623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3236973623
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.992128539
Short name T173
Test name
Test status
Simulation time 37662261046 ps
CPU time 110.61 seconds
Started Jul 02 09:45:41 AM PDT 24
Finished Jul 02 09:47:34 AM PDT 24
Peak memory 213536 kb
Host smart-59762769-3045-4758-9709-29a8286e4e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992128539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.992128539
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.77684238
Short name T133
Test name
Test status
Simulation time 1501486549 ps
CPU time 5.29 seconds
Started Jul 02 09:45:45 AM PDT 24
Finished Jul 02 09:45:53 AM PDT 24
Peak memory 213492 kb
Host smart-74cd9d91-e96e-441e-9295-fab27dd11cd2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77684238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl
_access.77684238
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.3722609547
Short name T212
Test name
Test status
Simulation time 764439373 ps
CPU time 1.26 seconds
Started Jul 02 09:45:42 AM PDT 24
Finished Jul 02 09:45:45 AM PDT 24
Peak memory 213484 kb
Host smart-8144c730-950a-4a53-a092-6abd4b4b020c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722609547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3722609547
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.577661124
Short name T184
Test name
Test status
Simulation time 113752388 ps
CPU time 0.93 seconds
Started Jul 02 09:45:39 AM PDT 24
Finished Jul 02 09:45:41 AM PDT 24
Peak memory 204960 kb
Host smart-7e759638-8fd0-4df6-aeef-2a2bb6cfb6d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577661124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.577661124
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3106368915
Short name T29
Test name
Test status
Simulation time 670337233 ps
CPU time 2.5 seconds
Started Jul 02 09:45:41 AM PDT 24
Finished Jul 02 09:45:45 AM PDT 24
Peak memory 205444 kb
Host smart-28fe6e1e-3d90-452b-8907-54568e133817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106368915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3106368915
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3713636732
Short name T137
Test name
Test status
Simulation time 10410349758 ps
CPU time 6.55 seconds
Started Jul 02 09:45:41 AM PDT 24
Finished Jul 02 09:45:50 AM PDT 24
Peak memory 213564 kb
Host smart-a840aa5e-91bb-4e6b-92a2-5f9cc980ea4f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3713636732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.3713636732
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.886839650
Short name T62
Test name
Test status
Simulation time 91562744 ps
CPU time 0.72 seconds
Started Jul 02 09:45:42 AM PDT 24
Finished Jul 02 09:45:44 AM PDT 24
Peak memory 204956 kb
Host smart-0477e7f8-be8d-4cb6-b77b-ba11ee1b7d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886839650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.886839650
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2694889512
Short name T31
Test name
Test status
Simulation time 1933530351 ps
CPU time 3.99 seconds
Started Jul 02 09:45:41 AM PDT 24
Finished Jul 02 09:45:47 AM PDT 24
Peak memory 213512 kb
Host smart-c95b862e-3d0c-48aa-8138-86aaf0d781bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694889512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2694889512
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.4236749770
Short name T263
Test name
Test status
Simulation time 4050407267 ps
CPU time 4.69 seconds
Started Jul 02 09:45:39 AM PDT 24
Finished Jul 02 09:45:45 AM PDT 24
Peak memory 213552 kb
Host smart-14fe9a94-36bd-44f7-be9d-3817cc25d7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236749770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.4236749770
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2335633419
Short name T132
Test name
Test status
Simulation time 3831201122 ps
CPU time 2.95 seconds
Started Jul 02 09:45:42 AM PDT 24
Finished Jul 02 09:45:47 AM PDT 24
Peak memory 213628 kb
Host smart-6712ecf3-e5d9-4887-a702-dd2f2777e402
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2335633419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.2335633419
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3523115247
Short name T139
Test name
Test status
Simulation time 913877674 ps
CPU time 3.11 seconds
Started Jul 02 09:45:45 AM PDT 24
Finished Jul 02 09:45:50 AM PDT 24
Peak memory 205344 kb
Host smart-3d72ca32-2b8f-4b15-979b-4eb0aadc51fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523115247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3523115247
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3152235677
Short name T181
Test name
Test status
Simulation time 165365201 ps
CPU time 0.82 seconds
Started Jul 02 09:45:44 AM PDT 24
Finished Jul 02 09:45:47 AM PDT 24
Peak memory 204996 kb
Host smart-fd0c2a90-6a6b-4b44-a410-27a45aeae47c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152235677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3152235677
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.640890784
Short name T178
Test name
Test status
Simulation time 1104107283 ps
CPU time 2.39 seconds
Started Jul 02 09:45:40 AM PDT 24
Finished Jul 02 09:45:44 AM PDT 24
Peak memory 213500 kb
Host smart-a7724b9d-d500-48a3-8b1e-4d05d01b6097
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=640890784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.640890784
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.741114044
Short name T217
Test name
Test status
Simulation time 2087227893 ps
CPU time 2.84 seconds
Started Jul 02 09:45:38 AM PDT 24
Finished Jul 02 09:45:42 AM PDT 24
Peak memory 213536 kb
Host smart-c772278a-f3a5-4d54-aa26-f4835b49b809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741114044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.741114044
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.2162620294
Short name T144
Test name
Test status
Simulation time 3057937236 ps
CPU time 5.17 seconds
Started Jul 02 09:45:43 AM PDT 24
Finished Jul 02 09:45:50 AM PDT 24
Peak memory 213416 kb
Host smart-15467d15-0bbc-493e-b636-b8cd959e4454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162620294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2162620294
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2150330662
Short name T215
Test name
Test status
Simulation time 86846830 ps
CPU time 0.72 seconds
Started Jul 02 09:45:45 AM PDT 24
Finished Jul 02 09:45:48 AM PDT 24
Peak memory 204988 kb
Host smart-db5395eb-1d74-48c9-b272-d3084c8223e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150330662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2150330662
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3810108287
Short name T250
Test name
Test status
Simulation time 15547197124 ps
CPU time 44.46 seconds
Started Jul 02 09:45:44 AM PDT 24
Finished Jul 02 09:46:30 AM PDT 24
Peak memory 217872 kb
Host smart-797e00fc-6ba1-4379-8d1e-3c189c9d05b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810108287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3810108287
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.939129058
Short name T267
Test name
Test status
Simulation time 12107920778 ps
CPU time 34.71 seconds
Started Jul 02 09:45:46 AM PDT 24
Finished Jul 02 09:46:23 AM PDT 24
Peak memory 213552 kb
Host smart-2b73abf6-314b-4e02-ba52-70636f5f2998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939129058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.939129058
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3196247741
Short name T128
Test name
Test status
Simulation time 4240886064 ps
CPU time 12.35 seconds
Started Jul 02 09:45:46 AM PDT 24
Finished Jul 02 09:46:00 AM PDT 24
Peak memory 221760 kb
Host smart-7d3625d6-4655-482f-a08f-4e8b8f396d59
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3196247741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3196247741
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.322339260
Short name T260
Test name
Test status
Simulation time 1192944531 ps
CPU time 1.45 seconds
Started Jul 02 09:45:46 AM PDT 24
Finished Jul 02 09:45:50 AM PDT 24
Peak memory 205360 kb
Host smart-4f4d2b29-7993-4ee5-89e0-b9103b0a7c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322339260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.322339260
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.790551175
Short name T187
Test name
Test status
Simulation time 11314636460 ps
CPU time 7.7 seconds
Started Jul 02 09:45:26 AM PDT 24
Finished Jul 02 09:45:34 AM PDT 24
Peak memory 213636 kb
Host smart-ed665157-18e9-4429-99c2-31c87eb7178e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790551175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.790551175
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3027965238
Short name T42
Test name
Test status
Simulation time 3668407122 ps
CPU time 4.13 seconds
Started Jul 02 09:45:23 AM PDT 24
Finished Jul 02 09:45:28 AM PDT 24
Peak memory 213600 kb
Host smart-3a37dca7-a2b6-4957-8602-2a5455c7ee52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027965238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3027965238
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.466658249
Short name T242
Test name
Test status
Simulation time 6550266900 ps
CPU time 8.96 seconds
Started Jul 02 09:45:24 AM PDT 24
Finished Jul 02 09:45:34 AM PDT 24
Peak memory 214752 kb
Host smart-0f5e012a-c533-4e83-a55f-e58ef0a8770f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466658249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.466658249
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2782044999
Short name T235
Test name
Test status
Simulation time 260669026 ps
CPU time 1.06 seconds
Started Jul 02 09:45:23 AM PDT 24
Finished Jul 02 09:45:25 AM PDT 24
Peak memory 204960 kb
Host smart-86e978ac-4c52-433f-817a-f8aaa147b118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782044999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2782044999
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.2849497255
Short name T46
Test name
Test status
Simulation time 3825168700 ps
CPU time 8.41 seconds
Started Jul 02 09:45:27 AM PDT 24
Finished Jul 02 09:45:36 AM PDT 24
Peak memory 213580 kb
Host smart-ca1f0887-2d7e-4a38-9f1d-b9eac667aaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849497255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2849497255
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.406798502
Short name T75
Test name
Test status
Simulation time 1076127223 ps
CPU time 3.7 seconds
Started Jul 02 09:45:27 AM PDT 24
Finished Jul 02 09:45:32 AM PDT 24
Peak memory 237416 kb
Host smart-e191846e-a8de-4d44-8eb3-022c4a7c69df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406798502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.406798502
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.1194222616
Short name T151
Test name
Test status
Simulation time 13726922074 ps
CPU time 21.55 seconds
Started Jul 02 09:45:29 AM PDT 24
Finished Jul 02 09:45:51 AM PDT 24
Peak memory 213360 kb
Host smart-f1d9c420-639b-4727-872b-9627d581486f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194222616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1194222616
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3708033982
Short name T266
Test name
Test status
Simulation time 130118334 ps
CPU time 1 seconds
Started Jul 02 09:45:46 AM PDT 24
Finished Jul 02 09:45:49 AM PDT 24
Peak memory 204976 kb
Host smart-0f7c3f95-8e9f-4161-9c1c-d7698b1e96c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708033982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3708033982
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2905058459
Short name T27
Test name
Test status
Simulation time 5277723122 ps
CPU time 8.54 seconds
Started Jul 02 09:45:43 AM PDT 24
Finished Jul 02 09:45:54 AM PDT 24
Peak memory 213404 kb
Host smart-5a05a9bd-abf1-4515-968d-716ba439d472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905058459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2905058459
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.4077545796
Short name T210
Test name
Test status
Simulation time 47275224 ps
CPU time 0.86 seconds
Started Jul 02 09:45:45 AM PDT 24
Finished Jul 02 09:45:49 AM PDT 24
Peak memory 204996 kb
Host smart-6c6cd2d1-25bb-4484-b5b0-3f064828f36e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077545796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.4077545796
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3885594240
Short name T182
Test name
Test status
Simulation time 85043888 ps
CPU time 0.83 seconds
Started Jul 02 09:45:46 AM PDT 24
Finished Jul 02 09:45:49 AM PDT 24
Peak memory 204984 kb
Host smart-4f82b74c-379c-4c1d-8233-f3e961470f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885594240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3885594240
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1601827208
Short name T205
Test name
Test status
Simulation time 173208717 ps
CPU time 0.75 seconds
Started Jul 02 09:45:44 AM PDT 24
Finished Jul 02 09:45:47 AM PDT 24
Peak memory 204976 kb
Host smart-1dec6db8-200f-4d37-967a-397f4ac35f02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601827208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1601827208
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2754373537
Short name T186
Test name
Test status
Simulation time 47721705 ps
CPU time 0.74 seconds
Started Jul 02 09:45:44 AM PDT 24
Finished Jul 02 09:45:47 AM PDT 24
Peak memory 204984 kb
Host smart-59c9efa5-e298-4756-9ac2-e784a44d7ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754373537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2754373537
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1480632422
Short name T209
Test name
Test status
Simulation time 78202555 ps
CPU time 0.9 seconds
Started Jul 02 09:45:47 AM PDT 24
Finished Jul 02 09:45:50 AM PDT 24
Peak memory 204924 kb
Host smart-fa1bf59b-74d2-414b-a3a4-3e8bd8ab5598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480632422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1480632422
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.4062196574
Short name T219
Test name
Test status
Simulation time 55064887 ps
CPU time 0.78 seconds
Started Jul 02 09:45:47 AM PDT 24
Finished Jul 02 09:45:50 AM PDT 24
Peak memory 205164 kb
Host smart-dd58e957-a1a5-463b-987d-4f3c85135b7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062196574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.4062196574
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.1845937023
Short name T150
Test name
Test status
Simulation time 5829647276 ps
CPU time 16.57 seconds
Started Jul 02 09:45:47 AM PDT 24
Finished Jul 02 09:46:05 AM PDT 24
Peak memory 213324 kb
Host smart-d9ab9992-970c-409a-9aff-2948524a4a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845937023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1845937023
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3981445808
Short name T194
Test name
Test status
Simulation time 44999259 ps
CPU time 0.79 seconds
Started Jul 02 09:45:51 AM PDT 24
Finished Jul 02 09:45:54 AM PDT 24
Peak memory 204984 kb
Host smart-484e0246-6ae3-4297-8f47-7d5c0122cd23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981445808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3981445808
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1963745424
Short name T63
Test name
Test status
Simulation time 94638656 ps
CPU time 0.74 seconds
Started Jul 02 09:45:51 AM PDT 24
Finished Jul 02 09:45:54 AM PDT 24
Peak memory 204968 kb
Host smart-77212152-209b-44ae-96a8-4de3d25249cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963745424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1963745424
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3680134882
Short name T206
Test name
Test status
Simulation time 157645954 ps
CPU time 0.87 seconds
Started Jul 02 09:45:48 AM PDT 24
Finished Jul 02 09:45:50 AM PDT 24
Peak memory 204948 kb
Host smart-4a93fdf8-9d49-4c47-b42f-b29134d4f233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680134882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3680134882
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.3500492653
Short name T55
Test name
Test status
Simulation time 9406622889 ps
CPU time 7.98 seconds
Started Jul 02 09:45:48 AM PDT 24
Finished Jul 02 09:45:58 AM PDT 24
Peak memory 213384 kb
Host smart-223345f3-6f4c-48df-bb7a-4cee27d964d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500492653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3500492653
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1871630737
Short name T255
Test name
Test status
Simulation time 60849616 ps
CPU time 0.78 seconds
Started Jul 02 09:45:40 AM PDT 24
Finished Jul 02 09:45:42 AM PDT 24
Peak memory 204992 kb
Host smart-fac51dcd-f4d2-4565-8e65-e4404258e22d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871630737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1871630737
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1243370952
Short name T198
Test name
Test status
Simulation time 1147872733 ps
CPU time 2.56 seconds
Started Jul 02 09:45:31 AM PDT 24
Finished Jul 02 09:45:34 AM PDT 24
Peak memory 205312 kb
Host smart-e4a02d95-1d69-4f05-9368-69376fba5b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243370952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1243370952
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.586766555
Short name T214
Test name
Test status
Simulation time 7434400669 ps
CPU time 16.91 seconds
Started Jul 02 09:45:30 AM PDT 24
Finished Jul 02 09:45:47 AM PDT 24
Peak memory 213552 kb
Host smart-51eef8f8-c897-4c7f-839f-99b230d9c229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586766555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.586766555
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4181614694
Short name T41
Test name
Test status
Simulation time 3030091523 ps
CPU time 5.92 seconds
Started Jul 02 09:45:30 AM PDT 24
Finished Jul 02 09:45:37 AM PDT 24
Peak memory 213552 kb
Host smart-ce4c4205-ecf5-4e27-a7aa-98378c6c51a5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181614694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.4181614694
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1722630422
Short name T256
Test name
Test status
Simulation time 140585882 ps
CPU time 0.79 seconds
Started Jul 02 09:45:41 AM PDT 24
Finished Jul 02 09:45:44 AM PDT 24
Peak memory 205000 kb
Host smart-9cdc11b7-d3af-4193-8f8c-414f7ff3538e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722630422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1722630422
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3024927715
Short name T183
Test name
Test status
Simulation time 57817402 ps
CPU time 0.79 seconds
Started Jul 02 09:45:46 AM PDT 24
Finished Jul 02 09:45:49 AM PDT 24
Peak memory 205008 kb
Host smart-787718f3-e755-4425-98fd-30f7d20c020f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024927715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3024927715
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2039204667
Short name T176
Test name
Test status
Simulation time 135692149 ps
CPU time 0.72 seconds
Started Jul 02 09:45:50 AM PDT 24
Finished Jul 02 09:45:52 AM PDT 24
Peak memory 204952 kb
Host smart-9db81b8c-1247-4345-8805-c8d9b2e4b251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039204667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2039204667
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.1966518172
Short name T14
Test name
Test status
Simulation time 11480088088 ps
CPU time 6.72 seconds
Started Jul 02 09:45:47 AM PDT 24
Finished Jul 02 09:45:55 AM PDT 24
Peak memory 205176 kb
Host smart-a27f621e-dea0-4af1-b88a-d78213015cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966518172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1966518172
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1942321229
Short name T218
Test name
Test status
Simulation time 67988920 ps
CPU time 0.83 seconds
Started Jul 02 09:45:49 AM PDT 24
Finished Jul 02 09:45:52 AM PDT 24
Peak memory 204992 kb
Host smart-952a547b-0b5b-4dff-b48a-3f5bf74eb08a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942321229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1942321229
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.4055066896
Short name T204
Test name
Test status
Simulation time 172244469 ps
CPU time 1.04 seconds
Started Jul 02 09:46:02 AM PDT 24
Finished Jul 02 09:46:05 AM PDT 24
Peak memory 205004 kb
Host smart-4fecf93f-3f9a-446d-80a2-a5839d90afce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055066896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.4055066896
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.795752790
Short name T191
Test name
Test status
Simulation time 41563121 ps
CPU time 0.79 seconds
Started Jul 02 09:45:51 AM PDT 24
Finished Jul 02 09:45:53 AM PDT 24
Peak memory 204996 kb
Host smart-1afccd10-6325-4d10-9475-2ec6c423ee3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795752790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.795752790
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2516772087
Short name T26
Test name
Test status
Simulation time 11952024780 ps
CPU time 20.99 seconds
Started Jul 02 09:45:51 AM PDT 24
Finished Jul 02 09:46:14 AM PDT 24
Peak memory 213396 kb
Host smart-8da3f970-0fc7-4053-9749-2bd357cc9ba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516772087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2516772087
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2243711798
Short name T252
Test name
Test status
Simulation time 124185655 ps
CPU time 1 seconds
Started Jul 02 09:45:49 AM PDT 24
Finished Jul 02 09:45:51 AM PDT 24
Peak memory 204992 kb
Host smart-226b530c-12ad-4e9f-9e41-579c9530c1f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243711798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2243711798
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.2121681663
Short name T175
Test name
Test status
Simulation time 55578575 ps
CPU time 0.81 seconds
Started Jul 02 09:45:51 AM PDT 24
Finished Jul 02 09:45:53 AM PDT 24
Peak memory 204952 kb
Host smart-2170f2cb-3c4f-4642-b8d1-aadb38985c50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121681663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2121681663
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.797491045
Short name T224
Test name
Test status
Simulation time 43875379 ps
CPU time 0.8 seconds
Started Jul 02 09:45:59 AM PDT 24
Finished Jul 02 09:46:02 AM PDT 24
Peak memory 205004 kb
Host smart-35220892-55be-450b-a8b4-3663adb5d96d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797491045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.797491045
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.2961089636
Short name T142
Test name
Test status
Simulation time 8387777324 ps
CPU time 4.85 seconds
Started Jul 02 09:45:49 AM PDT 24
Finished Jul 02 09:45:55 AM PDT 24
Peak memory 205204 kb
Host smart-56306d09-3e75-4cc6-9194-dc907cb6f4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961089636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2961089636
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.322066902
Short name T268
Test name
Test status
Simulation time 56881581 ps
CPU time 0.87 seconds
Started Jul 02 09:45:48 AM PDT 24
Finished Jul 02 09:45:50 AM PDT 24
Peak memory 204992 kb
Host smart-c09a5659-32d8-47b2-9353-8bd78eb77319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322066902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.322066902
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.3688969559
Short name T12
Test name
Test status
Simulation time 4300517298 ps
CPU time 8.47 seconds
Started Jul 02 09:45:51 AM PDT 24
Finished Jul 02 09:46:01 AM PDT 24
Peak memory 205192 kb
Host smart-602fd822-0579-4f76-b2ae-b19aff3f1e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688969559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3688969559
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.782181731
Short name T177
Test name
Test status
Simulation time 116864202 ps
CPU time 0.74 seconds
Started Jul 02 09:45:49 AM PDT 24
Finished Jul 02 09:45:52 AM PDT 24
Peak memory 205136 kb
Host smart-10c9bb11-9817-4e17-96d1-ab755a925e61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782181731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.782181731
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3667246440
Short name T275
Test name
Test status
Simulation time 194308019 ps
CPU time 0.79 seconds
Started Jul 02 09:45:33 AM PDT 24
Finished Jul 02 09:45:35 AM PDT 24
Peak memory 204980 kb
Host smart-a9438718-dfd9-4d07-b466-996292506c2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667246440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3667246440
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2548628890
Short name T127
Test name
Test status
Simulation time 1638941317 ps
CPU time 2.48 seconds
Started Jul 02 09:45:35 AM PDT 24
Finished Jul 02 09:45:39 AM PDT 24
Peak memory 205336 kb
Host smart-64d82590-50ba-4ee5-b7cf-6cdc3fc96cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548628890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2548628890
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3067518401
Short name T196
Test name
Test status
Simulation time 1958075558 ps
CPU time 3.06 seconds
Started Jul 02 09:45:31 AM PDT 24
Finished Jul 02 09:45:34 AM PDT 24
Peak memory 213472 kb
Host smart-ac5cd5aa-ce14-429c-9ef8-0dacff5eba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067518401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3067518401
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2201076123
Short name T131
Test name
Test status
Simulation time 1520955654 ps
CPU time 2.19 seconds
Started Jul 02 09:45:27 AM PDT 24
Finished Jul 02 09:45:30 AM PDT 24
Peak memory 205312 kb
Host smart-e072b8a2-5ced-4712-b1b6-d7252d28d5a9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201076123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2201076123
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3571515465
Short name T259
Test name
Test status
Simulation time 153341672 ps
CPU time 0.81 seconds
Started Jul 02 09:45:31 AM PDT 24
Finished Jul 02 09:45:33 AM PDT 24
Peak memory 204956 kb
Host smart-39788449-dd90-4feb-915b-932851671942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571515465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3571515465
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1635769535
Short name T223
Test name
Test status
Simulation time 899985370 ps
CPU time 3.21 seconds
Started Jul 02 09:45:38 AM PDT 24
Finished Jul 02 09:45:43 AM PDT 24
Peak memory 213488 kb
Host smart-c94e8c6c-d5cc-44be-a919-e612a62f3783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635769535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1635769535
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2648482939
Short name T74
Test name
Test status
Simulation time 1175842412 ps
CPU time 1.56 seconds
Started Jul 02 09:45:43 AM PDT 24
Finished Jul 02 09:45:47 AM PDT 24
Peak memory 237092 kb
Host smart-3604954c-930a-4319-82e7-8fb16c75ef13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648482939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2648482939
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1306562719
Short name T226
Test name
Test status
Simulation time 294322293 ps
CPU time 0.74 seconds
Started Jul 02 09:45:47 AM PDT 24
Finished Jul 02 09:45:49 AM PDT 24
Peak memory 204996 kb
Host smart-9a44029f-b185-4b79-95af-98e01759f425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306562719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1306562719
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3053680818
Short name T211
Test name
Test status
Simulation time 79062300 ps
CPU time 0.72 seconds
Started Jul 02 09:45:50 AM PDT 24
Finished Jul 02 09:45:52 AM PDT 24
Peak memory 204968 kb
Host smart-bae80cad-1cd1-43d7-a33e-0a9c5e337f5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053680818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3053680818
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.4140346200
Short name T169
Test name
Test status
Simulation time 3976950996 ps
CPU time 10 seconds
Started Jul 02 09:45:49 AM PDT 24
Finished Jul 02 09:46:00 AM PDT 24
Peak memory 213416 kb
Host smart-b701fbde-3216-4c96-8961-f63ed49278fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140346200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.4140346200
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1342143160
Short name T201
Test name
Test status
Simulation time 92934863 ps
CPU time 0.96 seconds
Started Jul 02 09:45:54 AM PDT 24
Finished Jul 02 09:45:58 AM PDT 24
Peak memory 204980 kb
Host smart-e4eb4c46-53d4-41b1-b5d2-79edbd0b3c3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342143160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1342143160
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3153223827
Short name T195
Test name
Test status
Simulation time 95994672 ps
CPU time 0.71 seconds
Started Jul 02 09:45:54 AM PDT 24
Finished Jul 02 09:45:56 AM PDT 24
Peak memory 204924 kb
Host smart-8fde3993-4adf-4487-aa5f-046f9c15c921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153223827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3153223827
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.7694217
Short name T154
Test name
Test status
Simulation time 2634835483 ps
CPU time 4.73 seconds
Started Jul 02 09:45:54 AM PDT 24
Finished Jul 02 09:46:00 AM PDT 24
Peak memory 213560 kb
Host smart-060c28b7-ce92-46b2-b524-9dba3b7ebd90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7694217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.7694217
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2635131565
Short name T73
Test name
Test status
Simulation time 64662510 ps
CPU time 0.76 seconds
Started Jul 02 09:45:54 AM PDT 24
Finished Jul 02 09:45:56 AM PDT 24
Peak memory 204952 kb
Host smart-b57ff2b7-1784-4980-afd7-08979ad2c276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635131565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2635131565
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.1129631107
Short name T170
Test name
Test status
Simulation time 9322912593 ps
CPU time 25.45 seconds
Started Jul 02 09:45:54 AM PDT 24
Finished Jul 02 09:46:20 AM PDT 24
Peak memory 213424 kb
Host smart-5561fa81-7310-41f1-b1ed-c5087eb86d4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129631107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1129631107
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2834939683
Short name T65
Test name
Test status
Simulation time 103854644 ps
CPU time 0.83 seconds
Started Jul 02 09:45:51 AM PDT 24
Finished Jul 02 09:45:54 AM PDT 24
Peak memory 204928 kb
Host smart-8911dcda-1396-4a65-9c6c-200f2daf487d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834939683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2834939683
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2729269898
Short name T213
Test name
Test status
Simulation time 141499160 ps
CPU time 0.75 seconds
Started Jul 02 09:45:54 AM PDT 24
Finished Jul 02 09:45:56 AM PDT 24
Peak memory 205168 kb
Host smart-f9a407da-51a5-4a5e-9463-997a44139af6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729269898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2729269898
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.418108622
Short name T152
Test name
Test status
Simulation time 2681899486 ps
CPU time 8.58 seconds
Started Jul 02 09:45:56 AM PDT 24
Finished Jul 02 09:46:07 AM PDT 24
Peak memory 213388 kb
Host smart-940b6157-c48e-493a-a1a9-fd777a4874e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418108622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.418108622
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2220661723
Short name T244
Test name
Test status
Simulation time 219427868 ps
CPU time 0.8 seconds
Started Jul 02 09:45:54 AM PDT 24
Finished Jul 02 09:45:56 AM PDT 24
Peak memory 204968 kb
Host smart-56270391-04af-4e50-a79b-84582e29ebfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220661723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2220661723
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3305563755
Short name T203
Test name
Test status
Simulation time 124120948 ps
CPU time 0.99 seconds
Started Jul 02 09:45:57 AM PDT 24
Finished Jul 02 09:46:01 AM PDT 24
Peak memory 204968 kb
Host smart-bd1c17d7-27a2-4e92-84cf-d1d9c747f3ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305563755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3305563755
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.4071133397
Short name T155
Test name
Test status
Simulation time 9486718625 ps
CPU time 3.03 seconds
Started Jul 02 09:45:52 AM PDT 24
Finished Jul 02 09:45:57 AM PDT 24
Peak memory 213380 kb
Host smart-aa6bf0f3-2c7a-47f6-9b86-5d19e286b499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071133397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.4071133397
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1827300682
Short name T238
Test name
Test status
Simulation time 48433015 ps
CPU time 0.83 seconds
Started Jul 02 09:45:53 AM PDT 24
Finished Jul 02 09:45:55 AM PDT 24
Peak memory 204996 kb
Host smart-33d50de2-f904-4ae0-bc33-f4e44cb0f680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827300682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1827300682
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.1534119013
Short name T16
Test name
Test status
Simulation time 14719117103 ps
CPU time 22.04 seconds
Started Jul 02 09:45:54 AM PDT 24
Finished Jul 02 09:46:18 AM PDT 24
Peak memory 205196 kb
Host smart-6f96787f-1804-491c-a6a6-0a70fedb1d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534119013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.1534119013
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3522889204
Short name T220
Test name
Test status
Simulation time 133540515 ps
CPU time 0.94 seconds
Started Jul 02 09:45:32 AM PDT 24
Finished Jul 02 09:45:34 AM PDT 24
Peak memory 204984 kb
Host smart-bbc6a1e2-922b-440f-8c57-0d3c4765f974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522889204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3522889204
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2572541452
Short name T221
Test name
Test status
Simulation time 10247159326 ps
CPU time 26.34 seconds
Started Jul 02 09:45:31 AM PDT 24
Finished Jul 02 09:45:59 AM PDT 24
Peak memory 213548 kb
Host smart-22a3e8bc-17a0-4445-a85f-4e4d8a8d079e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572541452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2572541452
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.437704308
Short name T258
Test name
Test status
Simulation time 2140798102 ps
CPU time 1.41 seconds
Started Jul 02 09:45:30 AM PDT 24
Finished Jul 02 09:45:32 AM PDT 24
Peak memory 213452 kb
Host smart-06cf1f21-e96b-440e-bc0c-e21b1082472e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=437704308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.437704308
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.4162612455
Short name T246
Test name
Test status
Simulation time 3887643741 ps
CPU time 9.71 seconds
Started Jul 02 09:45:34 AM PDT 24
Finished Jul 02 09:45:45 AM PDT 24
Peak memory 205372 kb
Host smart-49671d79-a678-4c62-b368-ed76622f2869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162612455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.4162612455
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1100677232
Short name T229
Test name
Test status
Simulation time 117711993 ps
CPU time 0.75 seconds
Started Jul 02 09:45:41 AM PDT 24
Finished Jul 02 09:45:44 AM PDT 24
Peak memory 204992 kb
Host smart-1bdd6b60-d349-4828-9cf9-3ecf7cbc8b3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100677232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1100677232
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2107765051
Short name T227
Test name
Test status
Simulation time 17089621064 ps
CPU time 27.6 seconds
Started Jul 02 09:45:34 AM PDT 24
Finished Jul 02 09:46:02 AM PDT 24
Peak memory 213468 kb
Host smart-0c518cc6-c4b5-4b2d-a37f-b337966272ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107765051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2107765051
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.84164278
Short name T243
Test name
Test status
Simulation time 5065056438 ps
CPU time 15.58 seconds
Started Jul 02 09:45:43 AM PDT 24
Finished Jul 02 09:46:01 AM PDT 24
Peak memory 213608 kb
Host smart-9ae587a2-867d-4d35-897b-e25c3c811fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84164278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.84164278
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2736423322
Short name T222
Test name
Test status
Simulation time 2461373778 ps
CPU time 3.72 seconds
Started Jul 02 09:45:34 AM PDT 24
Finished Jul 02 09:45:38 AM PDT 24
Peak memory 205296 kb
Host smart-e70be06e-5606-4702-996c-f2aa61cce87e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2736423322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2736423322
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3625235670
Short name T234
Test name
Test status
Simulation time 1497155792 ps
CPU time 1.79 seconds
Started Jul 02 09:45:41 AM PDT 24
Finished Jul 02 09:45:45 AM PDT 24
Peak memory 205296 kb
Host smart-9664d2cd-f299-4ddb-b9de-39cebcc53989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625235670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3625235670
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.2511597074
Short name T153
Test name
Test status
Simulation time 14230392656 ps
CPU time 9.98 seconds
Started Jul 02 09:45:43 AM PDT 24
Finished Jul 02 09:45:55 AM PDT 24
Peak memory 213392 kb
Host smart-2f4a8888-6908-4d5a-8404-85a05308fa2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511597074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2511597074
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3217961840
Short name T172
Test name
Test status
Simulation time 130459143 ps
CPU time 0.97 seconds
Started Jul 02 09:45:33 AM PDT 24
Finished Jul 02 09:45:35 AM PDT 24
Peak memory 204984 kb
Host smart-468ad1dd-3253-49c5-879a-cba6e715d2b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217961840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3217961840
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1786328631
Short name T193
Test name
Test status
Simulation time 8703451115 ps
CPU time 7.76 seconds
Started Jul 02 09:45:31 AM PDT 24
Finished Jul 02 09:45:40 AM PDT 24
Peak memory 215656 kb
Host smart-e15cecb2-b05a-4175-bae5-ef717ae9566f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786328631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1786328631
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3233865635
Short name T270
Test name
Test status
Simulation time 3967734017 ps
CPU time 6.49 seconds
Started Jul 02 09:45:44 AM PDT 24
Finished Jul 02 09:45:52 AM PDT 24
Peak memory 214916 kb
Host smart-c5ef9550-c099-42a8-90a0-3033338736bf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233865635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3233865635
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1912187158
Short name T225
Test name
Test status
Simulation time 3190008572 ps
CPU time 5.4 seconds
Started Jul 02 09:45:39 AM PDT 24
Finished Jul 02 09:45:46 AM PDT 24
Peak memory 205436 kb
Host smart-6f74a81b-897c-4392-b845-70d46b888610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912187158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1912187158
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2085112238
Short name T248
Test name
Test status
Simulation time 44882739 ps
CPU time 0.73 seconds
Started Jul 02 09:45:36 AM PDT 24
Finished Jul 02 09:45:39 AM PDT 24
Peak memory 204964 kb
Host smart-1f4d4563-16e8-4043-a78a-463cffbd7c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085112238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2085112238
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3894597229
Short name T233
Test name
Test status
Simulation time 19399747656 ps
CPU time 53.51 seconds
Started Jul 02 09:45:44 AM PDT 24
Finished Jul 02 09:46:40 AM PDT 24
Peak memory 213560 kb
Host smart-853c92db-abe5-4480-86fc-82b93689075c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894597229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3894597229
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3508270298
Short name T1
Test name
Test status
Simulation time 1075515906 ps
CPU time 1.56 seconds
Started Jul 02 09:45:39 AM PDT 24
Finished Jul 02 09:45:42 AM PDT 24
Peak memory 213528 kb
Host smart-41a25a4c-b3bb-4a1e-ab96-311f272d702e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508270298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3508270298
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.581396127
Short name T2
Test name
Test status
Simulation time 10054552064 ps
CPU time 8.11 seconds
Started Jul 02 09:45:33 AM PDT 24
Finished Jul 02 09:45:42 AM PDT 24
Peak memory 215012 kb
Host smart-eae9f47f-cdee-4f35-8e5c-de72570fc5b8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=581396127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.581396127
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.2736038600
Short name T189
Test name
Test status
Simulation time 4122546310 ps
CPU time 2.47 seconds
Started Jul 02 09:45:30 AM PDT 24
Finished Jul 02 09:45:33 AM PDT 24
Peak memory 213560 kb
Host smart-cd6fdbba-9a93-44ae-ba09-728019d3fc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736038600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2736038600
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.826442240
Short name T5
Test name
Test status
Simulation time 5258942608 ps
CPU time 4.79 seconds
Started Jul 02 09:45:43 AM PDT 24
Finished Jul 02 09:45:50 AM PDT 24
Peak memory 213416 kb
Host smart-12b5441d-0966-4c9e-8f43-a147543b6c21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826442240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.826442240
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1609298375
Short name T185
Test name
Test status
Simulation time 150274272 ps
CPU time 0.74 seconds
Started Jul 02 09:45:38 AM PDT 24
Finished Jul 02 09:45:40 AM PDT 24
Peak memory 205024 kb
Host smart-433b2b9c-2dec-481c-bdae-74d864ca077b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609298375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1609298375
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.999398311
Short name T251
Test name
Test status
Simulation time 51884251279 ps
CPU time 81.99 seconds
Started Jul 02 09:45:36 AM PDT 24
Finished Jul 02 09:47:00 AM PDT 24
Peak memory 213608 kb
Host smart-ff25ea4c-2ef5-448d-ba33-38bf2c593b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999398311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.999398311
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.315285024
Short name T202
Test name
Test status
Simulation time 2733641658 ps
CPU time 5.41 seconds
Started Jul 02 09:45:37 AM PDT 24
Finished Jul 02 09:45:44 AM PDT 24
Peak memory 213584 kb
Host smart-05490609-3b85-4405-98d3-6e23199acc6d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=315285024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.315285024
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%