Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 188812 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 542739 1 T4 15 T6 5 T33 8



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 455548 1 T4 18 T34 6 T36 6
values[0x0] 135315 1 T4 15 T5 4 T8 1
values[0x1] 140688 1 T9 1 T7 1 T4 11



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 143309 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 588242 1 T4 18 T8 1 T6 8



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2724 1 T30 1 T26 1 T53 8
valid_sources[0x01] 3557 1 T33 1 T43 29 T53 10
valid_sources[0x02] 2610 1 T50 1 T144 1 T53 7
valid_sources[0x03] 2746 1 T14 1 T154 14 T177 1
valid_sources[0x04] 3031 1 T178 1 T53 6 T64 2
valid_sources[0x05] 2805 1 T53 8 T64 3 T65 11
valid_sources[0x06] 3191 1 T5 1 T36 1 T53 7
valid_sources[0x07] 3045 1 T53 15 T63 5 T64 2
valid_sources[0x08] 2551 1 T23 4 T144 2 T53 6
valid_sources[0x09] 2479 1 T33 1 T53 13 T63 7
valid_sources[0x0a] 2356 1 T16 1 T44 5 T53 9
valid_sources[0x0b] 2723 1 T26 1 T53 8 T64 2
valid_sources[0x0c] 2517 1 T140 1 T44 1 T22 4
valid_sources[0x0d] 2563 1 T36 1 T44 1 T22 2
valid_sources[0x0e] 2320 1 T177 1 T133 1 T53 17
valid_sources[0x0f] 2751 1 T140 1 T44 2 T53 2
valid_sources[0x10] 2529 1 T177 1 T44 1 T53 9
valid_sources[0x11] 2719 1 T46 1 T53 10 T63 1
valid_sources[0x12] 2737 1 T177 1 T44 2 T22 2
valid_sources[0x13] 2496 1 T53 7 T64 1 T65 12
valid_sources[0x14] 2892 1 T22 2 T53 11 T63 3
valid_sources[0x15] 2811 1 T48 4 T138 5 T53 9
valid_sources[0x16] 3000 1 T144 1 T53 13 T63 2
valid_sources[0x17] 2862 1 T144 1 T44 3 T53 9
valid_sources[0x18] 2579 1 T53 13 T63 2 T65 9
valid_sources[0x19] 2432 1 T53 9 T63 3 T65 14
valid_sources[0x1a] 2991 1 T50 1 T53 17 T64 4
valid_sources[0x1b] 2840 1 T53 12 T63 1 T64 1
valid_sources[0x1c] 2707 1 T36 1 T30 1 T53 12
valid_sources[0x1d] 2634 1 T36 1 T53 6 T63 2
valid_sources[0x1e] 2980 1 T5 1 T145 26 T22 4
valid_sources[0x1f] 2171 1 T140 1 T53 2 T64 2
valid_sources[0x20] 2974 1 T53 9 T64 2 T65 16
valid_sources[0x21] 2838 1 T53 19 T64 2 T65 15
valid_sources[0x22] 2535 1 T53 7 T63 1 T64 5
valid_sources[0x23] 2574 1 T44 2 T53 11 T63 2
valid_sources[0x24] 2474 1 T53 9 T63 5 T65 12
valid_sources[0x25] 2473 1 T177 1 T44 1 T53 7
valid_sources[0x26] 3140 1 T36 1 T53 8 T63 1
valid_sources[0x27] 2194 1 T49 3 T177 1 T22 1
valid_sources[0x28] 3231 1 T48 4 T53 9 T64 2
valid_sources[0x29] 2456 1 T136 3 T53 9 T64 2
valid_sources[0x2a] 2568 1 T144 1 T53 10 T63 1
valid_sources[0x2b] 2842 1 T144 1 T53 14 T63 1
valid_sources[0x2c] 2654 1 T30 1 T140 2 T44 3
valid_sources[0x2d] 2951 1 T33 1 T179 2 T45 1
valid_sources[0x2e] 3206 1 T43 27 T49 2 T16 2
valid_sources[0x2f] 2675 1 T36 1 T177 1 T53 10
valid_sources[0x30] 2491 1 T133 2 T53 10 T63 1
valid_sources[0x31] 2726 1 T53 8 T63 1 T64 3
valid_sources[0x32] 2862 1 T53 11 T63 2 T65 12
valid_sources[0x33] 2695 1 T51 1 T53 9 T63 3
valid_sources[0x34] 2386 1 T39 2 T44 7 T53 6
valid_sources[0x35] 2581 1 T144 1 T53 1 T63 4
valid_sources[0x36] 2438 1 T6 16 T30 1 T177 1
valid_sources[0x37] 2877 1 T15 2 T53 12 T63 2
valid_sources[0x38] 3242 1 T65 17 T62 3 T96 69
valid_sources[0x39] 2346 1 T36 1 T14 1 T22 2
valid_sources[0x3a] 2593 1 T50 1 T24 3 T53 3
valid_sources[0x3b] 2906 1 T53 8 T63 4 T64 3
valid_sources[0x3c] 2532 1 T36 1 T53 7 T63 3
valid_sources[0x3d] 3677 1 T53 12 T63 3 T64 3
valid_sources[0x3e] 3318 1 T49 3 T15 16 T44 2
valid_sources[0x3f] 3216 1 T34 3 T53 4 T63 2
valid_sources[0x40] 2737 1 T144 1 T53 9 T63 4
valid_sources[0x41] 2970 1 T36 1 T53 3 T63 8
valid_sources[0x42] 2614 1 T52 3 T53 14 T63 2
valid_sources[0x43] 3068 1 T30 1 T136 1 T53 15
valid_sources[0x44] 2334 1 T53 6 T64 3 T65 15
valid_sources[0x45] 2795 1 T53 8 T64 2 T65 12
valid_sources[0x46] 2281 1 T34 6 T36 2 T53 5
valid_sources[0x47] 3709 1 T53 7 T63 1 T65 20
valid_sources[0x48] 2651 1 T49 1 T178 1 T53 14
valid_sources[0x49] 2899 1 T44 4 T53 8 T63 5
valid_sources[0x4a] 2929 1 T53 16 T63 1 T64 6
valid_sources[0x4b] 2499 1 T43 14 T53 7 T63 5
valid_sources[0x4c] 2748 1 T33 1 T46 2 T22 2
valid_sources[0x4d] 3261 1 T50 1 T53 18 T63 1
valid_sources[0x4e] 2551 1 T22 2 T53 12 T63 3
valid_sources[0x4f] 4817 1 T44 2 T53 10 T63 4
valid_sources[0x50] 2470 1 T30 2 T53 2 T63 2
valid_sources[0x51] 2505 1 T36 1 T26 1 T53 10
valid_sources[0x52] 2857 1 T48 1 T177 1 T142 9
valid_sources[0x53] 2608 1 T36 2 T140 1 T44 3
valid_sources[0x54] 2940 1 T19 2 T53 6 T64 3
valid_sources[0x55] 2710 1 T44 1 T53 7 T63 1
valid_sources[0x56] 2609 1 T36 1 T45 1 T46 1
valid_sources[0x57] 2734 1 T33 2 T40 1 T53 8
valid_sources[0x58] 2544 1 T30 1 T22 1 T53 12
valid_sources[0x59] 2638 1 T49 1 T44 1 T53 11
valid_sources[0x5a] 2695 1 T138 2 T53 12 T63 3
valid_sources[0x5b] 2693 1 T179 1 T44 1 T53 11
valid_sources[0x5c] 2870 1 T30 1 T53 6 T63 1
valid_sources[0x5d] 3461 1 T53 10 T64 3 T65 14
valid_sources[0x5e] 4441 1 T53 11 T63 4 T64 3
valid_sources[0x5f] 2935 1 T33 3 T53 8 T63 1
valid_sources[0x60] 2722 1 T52 2 T44 1 T53 8
valid_sources[0x61] 2342 1 T30 5 T53 5 T64 5
valid_sources[0x62] 2518 1 T33 2 T45 1 T53 7
valid_sources[0x63] 2808 1 T53 10 T63 1 T64 3
valid_sources[0x64] 16442 1 T53 13 T63 5 T64 1
valid_sources[0x65] 2970 1 T53 14 T63 4 T64 1
valid_sources[0x66] 2587 1 T53 15 T64 4 T65 18
valid_sources[0x67] 2305 1 T53 15 T64 1 T65 7
valid_sources[0x68] 2908 1 T36 1 T53 7 T65 10
valid_sources[0x69] 2902 1 T138 2 T53 7 T63 2
valid_sources[0x6a] 3094 1 T53 8 T63 2 T64 1
valid_sources[0x6b] 2799 1 T45 1 T53 1 T63 3
valid_sources[0x6c] 2754 1 T30 1 T53 5 T63 4
valid_sources[0x6d] 2471 1 T22 1 T53 8 T63 1
valid_sources[0x6e] 11069 1 T53 7 T63 7 T64 2
valid_sources[0x6f] 2720 1 T5 1 T17 2 T53 4
valid_sources[0x70] 2903 1 T36 1 T29 22 T53 11
valid_sources[0x71] 3040 1 T53 13 T63 1 T64 3
valid_sources[0x72] 2893 1 T46 1 T53 16 T63 3
valid_sources[0x73] 2723 1 T50 1 T53 7 T63 2
valid_sources[0x74] 2316 1 T9 1 T44 3 T53 3
valid_sources[0x75] 2380 1 T140 1 T53 12 T64 1
valid_sources[0x76] 2708 1 T140 1 T53 8 T63 2
valid_sources[0x77] 2353 1 T33 2 T138 1 T53 9
valid_sources[0x78] 2729 1 T52 1 T53 7 T63 16
valid_sources[0x79] 2712 1 T179 2 T138 3 T44 5
valid_sources[0x7a] 2755 1 T53 5 T63 8 T65 13
valid_sources[0x7b] 2888 1 T36 1 T53 6 T64 3
valid_sources[0x7c] 2741 1 T7 1 T49 8 T53 3
valid_sources[0x7d] 2737 1 T177 1 T22 3 T53 4
valid_sources[0x7e] 3021 1 T53 12 T63 4 T64 2
valid_sources[0x7f] 2605 1 T53 8 T63 2 T65 10
valid_sources[0x80] 2630 1 T21 5 T136 9 T53 13



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 276948 1 T4 10 T34 1 T36 4
values[0x0] all_enables biggest_size 133365 1 T4 3 T6 4 T33 5
values[0x1] all_enables biggest_size 132426 1 T4 2 T6 1 T33 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4360 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 21244 1 T1 1 T2 4 T9 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 8944 1 T53 554 T63 3 T64 3
values[0x0] 8063 1 T1 4 T2 5 T3 7
values[0x1] 8597 1 T1 2 T2 10 T9 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3266 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 22338 1 T1 1 T2 6 T9 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 74 1 T53 1 T65 2 T61 1
valid_sources[0x01] 75 1 T180 1 T14 2 T53 6
valid_sources[0x02] 98 1 T69 1 T181 1 T182 2
valid_sources[0x03] 63 1 T141 1 T144 3 T183 1
valid_sources[0x04] 82 1 T53 5 T61 1 T89 2
valid_sources[0x05] 93 1 T20 1 T36 1 T53 10
valid_sources[0x06] 97 1 T1 6 T156 1 T137 2
valid_sources[0x07] 66 1 T14 1 T53 6 T54 2
valid_sources[0x08] 66 1 T184 3 T185 1 T53 9
valid_sources[0x09] 83 1 T36 1 T186 1 T141 1
valid_sources[0x0a] 85 1 T156 1 T53 4 T61 1
valid_sources[0x0b] 89 1 T29 1 T137 1 T53 5
valid_sources[0x0c] 111 1 T10 1 T187 1 T188 1
valid_sources[0x0d] 86 1 T156 1 T185 1 T189 3
valid_sources[0x0e] 100 1 T70 1 T190 18 T137 1
valid_sources[0x0f] 118 1 T183 1 T191 1 T160 8
valid_sources[0x10] 103 1 T134 3 T15 9 T192 1
valid_sources[0x11] 85 1 T30 1 T79 1 T19 7
valid_sources[0x12] 73 1 T53 35 T62 1 T95 1
valid_sources[0x13] 49 1 T76 1 T193 2 T53 3
valid_sources[0x14] 115 1 T194 1 T53 19 T61 2
valid_sources[0x15] 114 1 T66 1 T195 1 T53 6
valid_sources[0x16] 85 1 T196 15 T53 8 T61 2
valid_sources[0x17] 231 1 T30 1 T156 1 T53 6
valid_sources[0x18] 72 1 T2 1 T185 1 T16 1
valid_sources[0x19] 68 1 T18 1 T53 5 T65 5
valid_sources[0x1a] 113 1 T2 1 T71 1 T197 4
valid_sources[0x1b] 90 1 T198 1 T53 3 T54 1
valid_sources[0x1c] 83 1 T180 1 T195 1 T53 9
valid_sources[0x1d] 80 1 T199 1 T76 1 T53 4
valid_sources[0x1e] 113 1 T72 1 T156 1 T186 1
valid_sources[0x1f] 79 1 T200 1 T186 1 T53 10
valid_sources[0x20] 78 1 T148 1 T155 1 T53 3
valid_sources[0x21] 129 1 T32 1 T78 2 T201 1
valid_sources[0x22] 99 1 T146 1 T163 1 T53 4
valid_sources[0x23] 53 1 T48 1 T53 3 T95 2
valid_sources[0x24] 68 1 T202 1 T53 7 T61 1
valid_sources[0x25] 129 1 T68 1 T16 1 T203 2
valid_sources[0x26] 92 1 T204 1 T49 1 T183 1
valid_sources[0x27] 80 1 T205 1 T193 1 T53 14
valid_sources[0x28] 126 1 T77 1 T53 1 T95 2
valid_sources[0x29] 92 1 T53 5 T61 9 T62 2
valid_sources[0x2a] 101 1 T185 1 T206 1 T53 20
valid_sources[0x2b] 114 1 T180 1 T204 1 T53 27
valid_sources[0x2c] 97 1 T2 2 T9 1 T7 1
valid_sources[0x2d] 76 1 T186 1 T207 1 T193 1
valid_sources[0x2e] 115 1 T34 2 T208 15 T53 18
valid_sources[0x2f] 108 1 T30 1 T23 1 T185 1
valid_sources[0x30] 64 1 T53 12 T62 1 T95 1
valid_sources[0x31] 102 1 T185 1 T203 1 T53 6
valid_sources[0x32] 99 1 T36 2 T23 1 T209 1
valid_sources[0x33] 134 1 T203 1 T53 4 T61 1
valid_sources[0x34] 68 1 T210 1 T185 1 T53 5
valid_sources[0x35] 62 1 T10 1 T53 10 T126 4
valid_sources[0x36] 73 1 T80 2 T53 6 T54 1
valid_sources[0x37] 96 1 T29 1 T53 24 T89 3
valid_sources[0x38] 65 1 T194 2 T53 15 T91 1
valid_sources[0x39] 85 1 T14 1 T184 1 T79 2
valid_sources[0x3a] 104 1 T211 1 T76 1 T212 1
valid_sources[0x3b] 97 1 T204 1 T177 6 T144 3
valid_sources[0x3c] 66 1 T180 1 T186 1 T53 2
valid_sources[0x3d] 83 1 T53 14 T54 1 T89 1
valid_sources[0x3e] 142 1 T213 11 T214 10 T53 17
valid_sources[0x3f] 80 1 T35 1 T205 1 T53 3
valid_sources[0x40] 84 1 T70 3 T186 1 T16 1
valid_sources[0x41] 64 1 T215 5 T70 2 T53 1
valid_sources[0x42] 118 1 T3 13 T181 2 T14 1
valid_sources[0x43] 81 1 T158 1 T53 9 T62 4
valid_sources[0x44] 72 1 T215 1 T183 1 T53 3
valid_sources[0x45] 101 1 T206 1 T53 20 T61 1
valid_sources[0x46] 99 1 T12 1 T206 1 T133 1
valid_sources[0x47] 78 1 T194 1 T53 5 T61 2
valid_sources[0x48] 99 1 T53 2 T91 1 T95 2
valid_sources[0x49] 84 1 T2 1 T141 1 T53 22
valid_sources[0x4a] 77 1 T181 2 T216 3 T53 4
valid_sources[0x4b] 85 1 T217 7 T204 1 T53 15
valid_sources[0x4c] 107 1 T186 1 T209 1 T53 11
valid_sources[0x4d] 91 1 T209 2 T53 5 T61 6
valid_sources[0x4e] 118 1 T76 1 T53 20 T61 1
valid_sources[0x4f] 97 1 T11 1 T72 1 T206 2
valid_sources[0x50] 207 1 T185 1 T44 1 T53 11
valid_sources[0x51] 90 1 T53 11 T64 4 T62 2
valid_sources[0x52] 76 1 T29 1 T141 1 T53 3
valid_sources[0x53] 138 1 T70 1 T53 10 T62 2
valid_sources[0x54] 107 1 T145 6 T218 10 T209 1
valid_sources[0x55] 84 1 T200 1 T133 1 T53 3
valid_sources[0x56] 74 1 T202 1 T53 22 T54 2
valid_sources[0x57] 68 1 T83 1 T53 4 T61 1
valid_sources[0x58] 102 1 T219 4 T53 14 T54 1
valid_sources[0x59] 106 1 T220 1 T183 1 T76 1
valid_sources[0x5a] 107 1 T221 1 T53 6 T62 2
valid_sources[0x5b] 105 1 T53 2 T93 1 T95 4
valid_sources[0x5c] 90 1 T31 2 T34 2 T53 5
valid_sources[0x5d] 100 1 T194 2 T14 1 T183 1
valid_sources[0x5e] 88 1 T36 1 T186 1 T81 1
valid_sources[0x5f] 108 1 T222 1 T79 1 T223 2
valid_sources[0x60] 101 1 T53 1 T61 4 T92 2
valid_sources[0x61] 76 1 T156 1 T76 3 T22 2
valid_sources[0x62] 143 1 T198 1 T224 10 T185 2
valid_sources[0x63] 75 1 T225 1 T53 6 T62 1
valid_sources[0x64] 51 1 T134 1 T23 1 T53 1
valid_sources[0x65] 93 1 T82 3 T53 19 T62 2
valid_sources[0x66] 87 1 T203 1 T53 9 T95 1
valid_sources[0x67] 489 1 T79 1 T53 9 T54 4
valid_sources[0x68] 70 1 T226 12 T53 3 T96 1
valid_sources[0x69] 95 1 T53 4 T54 3 T90 26
valid_sources[0x6a] 82 1 T140 1 T53 16 T54 1
valid_sources[0x6b] 109 1 T227 3 T228 1 T135 5
valid_sources[0x6c] 81 1 T33 4 T180 1 T53 16
valid_sources[0x6d] 92 1 T36 1 T204 1 T53 22
valid_sources[0x6e] 91 1 T10 1 T229 1 T133 1
valid_sources[0x6f] 78 1 T39 1 T91 1 T93 1
valid_sources[0x70] 113 1 T141 1 T77 1 T191 1
valid_sources[0x71] 110 1 T230 1 T231 3 T53 17
valid_sources[0x72] 84 1 T21 6 T78 1 T225 1
valid_sources[0x73] 108 1 T71 2 T206 1 T53 1
valid_sources[0x74] 65 1 T53 4 T54 2 T90 8
valid_sources[0x75] 121 1 T80 2 T53 7 T62 3
valid_sources[0x76] 65 1 T55 1 T79 1 T53 3
valid_sources[0x77] 117 1 T232 1 T223 1 T193 1
valid_sources[0x78] 83 1 T233 1 T234 1 T76 1
valid_sources[0x79] 71 1 T235 1 T53 1 T62 4
valid_sources[0x7a] 86 1 T67 6 T28 5 T53 5
valid_sources[0x7b] 89 1 T236 1 T237 1 T23 1
valid_sources[0x7c] 102 1 T195 1 T137 1 T182 2
valid_sources[0x7d] 82 1 T204 1 T61 1 T54 1
valid_sources[0x7e] 60 1 T61 1 T62 2 T96 1
valid_sources[0x7f] 90 1 T234 1 T53 2 T61 2
valid_sources[0x80] 62 1 T72 1 T79 1 T238 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 6592 1 T53 543 T63 1 T64 1
values[0x0] all_enables biggest_size 7306 1 T1 1 T2 2 T3 1
values[0x1] all_enables biggest_size 7346 1 T2 2 T9 1 T3 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%