SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 761739 | 1 | T7 | 1 | T4 | 44 | T5 | 4 | |||
auto[1] | 25155 | 1 | T43 | 80 | T44 | 80 | T53 | 2278 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 786685 | 1 | T7 | 1 | T4 | 44 | T5 | 4 | |||
values[1] | 22 | 1 | T89 | 1 | T92 | 2 | T94 | 2 | |||
values[2] | 2 | 1 | T164 | 1 | T165 | 1 | - | - | |||
values[3] | 100 | 1 | T60 | 6 | T89 | 7 | T92 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 786691 | 1 | T7 | 1 | T4 | 44 | T5 | 4 | |||
values[1] | 21 | 1 | T60 | 1 | T89 | 2 | T94 | 3 | |||
values[2] | 4 | 1 | T165 | 1 | T166 | 1 | T167 | 1 | |||
values[3] | 114 | 1 | T60 | 4 | T89 | 5 | T92 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 786584 | 1 | T7 | 1 | T4 | 44 | T5 | 4 | |||
auto[TlIntgErrCmd] | 107 | 1 | T60 | 3 | T89 | 8 | T92 | 4 | |||
auto[TlIntgErrData] | 101 | 1 | T60 | 2 | T89 | 7 | T92 | 4 | |||
auto[TlIntgErrBoth] | 102 | 1 | T60 | 5 | T89 | 5 | T92 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 49019 | 0 | T1 | 6 | T2 | 15 | T9 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 48808 | 1 | T1 | 6 | T2 | 15 | T9 | 1 | |||
values[1] | 23 | 1 | T60 | 1 | T89 | 1 | T92 | 1 | |||
values[2] | 7 | 1 | T168 | 1 | T166 | 3 | T169 | 1 | |||
values[3] | 108 | 1 | T60 | 3 | T89 | 9 | T92 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 48811 | 1 | T1 | 6 | T2 | 15 | T9 | 1 | |||
values[1] | 20 | 1 | T89 | 1 | T92 | 1 | T94 | 1 | |||
values[2] | 9 | 1 | T60 | 1 | T170 | 2 | T165 | 1 | |||
values[3] | 107 | 1 | T60 | 2 | T89 | 6 | T92 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 48709 | 1 | T1 | 6 | T2 | 15 | T9 | 1 | |||
auto[TlIntgErrCmd] | 102 | 1 | T60 | 5 | T89 | 10 | T92 | 3 | |||
auto[TlIntgErrData] | 99 | 1 | T60 | 3 | T89 | 5 | T92 | 4 | |||
auto[TlIntgErrBoth] | 109 | 1 | T60 | 2 | T89 | 5 | T92 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |