Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	241948	1		T7	1		T4	29		T5	4
full_word	544946	1		T4	15		T6	5		T33	8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	786584	1		T7	1		T4	44		T5	4
auto[TlIntgErrCmd]	107	1		T60	3		T89	8		T92	4
auto[TlIntgErrData]	101	1		T60	2		T89	7		T92	4
auto[TlIntgErrBoth]	102	1		T60	5		T89	5		T92	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	458305	1		T4	18		T34	6		T36	6
auto[1]	328589	1		T7	1		T4	26		T5	4

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	180929	1		T4	8		T34	5		T36	2
auto[TlIntgErrNone]	partial	auto[1]	60734	1		T7	1		T4	21		T5	4
auto[TlIntgErrNone]	full_word	auto[0]	277223	1		T4	10		T34	1		T36	4
auto[TlIntgErrNone]	full_word	auto[1]	267698	1		T4	5		T6	5		T33	8
auto[TlIntgErrCmd]	partial	auto[0]	46	1		T60	1		T89	3		T92	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T60	2		T89	5		T92	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T171	1		T168	1		T167	2
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T172	1		T173	1		-	-
auto[TlIntgErrData]	partial	auto[0]	50	1		T60	1		T89	1		T92	2
auto[TlIntgErrData]	partial	auto[1]	44	1		T89	4		T92	2		T94	6
auto[TlIntgErrData]	full_word	auto[0]	2	1		T89	1		T167	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T60	1		T89	1		T164	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1		T60	4		T89	3		T92	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T60	1		T89	1		T94	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T164	2		T174	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T89	1		T168	1		T165	1