Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 241948 1 T7 1 T4 29 T5 4
full_word 544946 1 T4 15 T6 5 T33 8



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 786584 1 T7 1 T4 44 T5 4
auto[TlIntgErrCmd] 107 1 T60 3 T89 8 T92 4
auto[TlIntgErrData] 101 1 T60 2 T89 7 T92 4
auto[TlIntgErrBoth] 102 1 T60 5 T89 5 T92 2



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 458305 1 T4 18 T34 6 T36 6
auto[1] 328589 1 T7 1 T4 26 T5 4



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 180929 1 T4 8 T34 5 T36 2
auto[TlIntgErrNone] partial auto[1] 60734 1 T7 1 T4 21 T5 4
auto[TlIntgErrNone] full_word auto[0] 277223 1 T4 10 T34 1 T36 4
auto[TlIntgErrNone] full_word auto[1] 267698 1 T4 5 T6 5 T33 8
auto[TlIntgErrCmd] partial auto[0] 46 1 T60 1 T89 3 T92 1
auto[TlIntgErrCmd] partial auto[1] 53 1 T60 2 T89 5 T92 3
auto[TlIntgErrCmd] full_word auto[0] 6 1 T171 1 T168 1 T167 2
auto[TlIntgErrCmd] full_word auto[1] 2 1 T172 1 T173 1 - -
auto[TlIntgErrData] partial auto[0] 50 1 T60 1 T89 1 T92 2
auto[TlIntgErrData] partial auto[1] 44 1 T89 4 T92 2 T94 6
auto[TlIntgErrData] full_word auto[0] 2 1 T89 1 T167 1 - -
auto[TlIntgErrData] full_word auto[1] 5 1 T60 1 T89 1 T164 1
auto[TlIntgErrBoth] partial auto[0] 46 1 T60 4 T89 3 T92 2
auto[TlIntgErrBoth] partial auto[1] 46 1 T60 1 T89 1 T94 5
auto[TlIntgErrBoth] full_word auto[0] 3 1 T164 2 T174 1 - -
auto[TlIntgErrBoth] full_word auto[1] 7 1 T89 1 T168 1 T165 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%