Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	87.50	100.00					75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm_enable_checker

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
36	1	1

---

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	57635244	4334952	0	0
MemTLResponseWithoutDebugIsError_A	57635244	2	0	0
NdmResetAckNeedsDebug_A	57635244	0	0	0
SbaTLRequestNeedsDebug_A	57635244	12306	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57635244	4334952	0	0
T4	261123	89299	0	0
T5	15206	12372	0	0
T6	0	138192	0	0
T7	4746	3151	0	0
T8	5848	4959	0	0
T10	649798	249081	0	0
T20	158450	0	0	0
T21	0	77402	0	0
T31	580771	0	0	0
T33	0	106113	0	0
T34	0	65230	0	0
T35	45205	0	0	0
T36	0	90426	0	0
T59	2477	0	0	0
T67	7580	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57635244	2	0	0
T3	2176	0	0	0
T4	261123	0	0	0
T7	4746	0	0	0
T9	5024	1	0	0
T10	649798	0	0	0
T11	152920	0	0	0
T12	5146	0	0	0
T13	130534	0	0	0
T20	158450	0	0	0
T55	0	1	0	0
T59	2477	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57635244	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57635244	12306	0	0
T4	261123	0	0	0
T5	15206	0	0	0
T7	4746	0	0	0
T10	649798	0	0	0
T11	152920	65	0	0
T12	5146	0	0	0
T13	130534	117	0	0
T20	158450	61	0	0
T31	580771	76	0	0
T32	0	20	0	0
T37	0	540	0	0
T59	2477	0	0	0
T66	0	35	0	0
T83	0	73	0	0
T84	0	22	0	0
T85	0	104	0	0