Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T9
01CoveredT1,T2,T9
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T9
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T9
11CoveredT1,T2,T9

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9072965 9071677 0 0
selKnown1 64069187 64067899 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9072965 9071677 0 0
T1 322 320 0 0
T2 315 313 0 0
T3 397 395 0 0
T4 22 20 0 0
T5 2 0 0 0
T6 0 4 0 0
T7 2315 2311 0 0
T9 347 345 0 0
T10 43675 43671 0 0
T11 22885 22881 0 0
T12 557 553 0 0
T13 33807 33803 0 0
T20 17534 17530 0 0
T21 0 28 0 0
T31 12 10 0 0
T33 0 22 0 0
T34 0 20 0 0
T35 0 3 0 0
T36 0 8 0 0
T37 0 8 0 0
T59 2 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 64069187 64067899 0 0
T1 4755 4753 0 0
T2 6439 6437 0 0
T3 2374 2372 0 0
T4 14 12 0 0
T5 2 0 0 0
T6 0 4 0 0
T7 5904 5900 0 0
T9 5197 5195 0 0
T10 671639 671635 0 0
T11 164367 164363 0 0
T12 5425 5421 0 0
T13 147438 147434 0 0
T20 167218 167214 0 0
T21 0 8 0 0
T31 12 10 0 0
T33 0 4 0 0
T34 0 8 0 0
T36 0 6 0 0
T37 0 8 0 0
T59 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T9
01CoveredT1,T2,T9
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T9
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T9
11CoveredT1,T2,T9

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2638325 2638112 0 0
selKnown1 57635244 57635031 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2638325 2638112 0 0
T1 161 160 0 0
T2 157 156 0 0
T3 198 197 0 0
T7 1156 1155 0 0
T9 173 172 0 0
T10 21831 21830 0 0
T11 11437 11436 0 0
T12 277 276 0 0
T13 16902 16901 0 0
T20 8766 8765 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 57635244 57635031 0 0
T1 4594 4593 0 0
T2 6282 6281 0 0
T3 2176 2175 0 0
T7 4746 4745 0 0
T9 5024 5023 0 0
T10 649798 649797 0 0
T11 152920 152919 0 0
T12 5146 5145 0 0
T13 130534 130533 0 0
T20 158450 158449 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T9
01CoveredT1,T2,T9
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T9
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T9
11CoveredT1,T2,T9

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 728 515 0 0
selKnown1 578 365 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 728 515 0 0
T4 11 10 0 0
T5 1 0 0 0
T6 0 2 0 0
T7 1 0 0 0
T10 5 4 0 0
T11 5 4 0 0
T12 1 0 0 0
T13 1 0 0 0
T20 1 0 0 0
T21 0 14 0 0
T31 6 5 0 0
T33 0 11 0 0
T34 0 10 0 0
T36 0 8 0 0
T37 0 4 0 0
T59 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 578 365 0 0
T4 7 6 0 0
T5 1 0 0 0
T6 0 2 0 0
T7 1 0 0 0
T10 5 4 0 0
T11 5 4 0 0
T12 1 0 0 0
T13 1 0 0 0
T20 1 0 0 0
T21 0 4 0 0
T31 6 5 0 0
T33 0 2 0 0
T34 0 4 0 0
T36 0 3 0 0
T37 0 4 0 0
T59 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T9
01CoveredT1,T2,T9
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T9
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T9
11CoveredT1,T2,T9

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6431907 6431476 0 0
selKnown1 6431691 6431260 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431907 6431476 0 0
T1 161 160 0 0
T2 158 157 0 0
T3 199 198 0 0
T7 1157 1156 0 0
T9 174 173 0 0
T10 21832 21831 0 0
T11 11438 11437 0 0
T12 278 277 0 0
T13 16903 16902 0 0
T20 8766 8765 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431691 6431260 0 0
T1 161 160 0 0
T2 157 156 0 0
T3 198 197 0 0
T7 1156 1155 0 0
T9 173 172 0 0
T10 21831 21830 0 0
T11 11437 11436 0 0
T12 277 276 0 0
T13 16902 16901 0 0
T20 8766 8765 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T9
01CoveredT1,T2,T9
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T9
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T9
11CoveredT1,T2,T9

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2005 1574 0 0
selKnown1 1674 1243 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2005 1574 0 0
T4 11 10 0 0
T5 1 0 0 0
T6 0 2 0 0
T7 1 0 0 0
T10 7 6 0 0
T11 5 4 0 0
T12 1 0 0 0
T13 1 0 0 0
T20 1 0 0 0
T21 0 14 0 0
T31 6 5 0 0
T33 0 11 0 0
T34 0 10 0 0
T35 0 3 0 0
T37 0 4 0 0
T59 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1674 1243 0 0
T4 7 6 0 0
T5 1 0 0 0
T6 0 2 0 0
T7 1 0 0 0
T10 5 4 0 0
T11 5 4 0 0
T12 1 0 0 0
T13 1 0 0 0
T20 1 0 0 0
T21 0 4 0 0
T31 6 5 0 0
T33 0 2 0 0
T34 0 4 0 0
T36 0 3 0 0
T37 0 4 0 0
T59 1 0 0 0

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