SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
82.66 | 98.04 | 77.78 | 100.00 | 87.50 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1278 | 1278 | 0 | 0 |
OutputsKnown_A | 345811464 | 345577614 | 0 | 0 |
gen_flops.OutputDelay_A | 172905732 | 172783605 | 0 | 1917 |
gen_no_flops.OutputDelay_A | 172905732 | 172788807 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1278 | 1278 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T9 | 6 | 6 | 0 | 0 |
T10 | 6 | 6 | 0 | 0 |
T11 | 6 | 6 | 0 | 0 |
T12 | 6 | 6 | 0 | 0 |
T13 | 6 | 6 | 0 | 0 |
T20 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 345811464 | 345577614 | 0 | 0 |
T1 | 27564 | 27216 | 0 | 0 |
T2 | 37692 | 37374 | 0 | 0 |
T3 | 13056 | 12612 | 0 | 0 |
T7 | 28476 | 28104 | 0 | 0 |
T9 | 30144 | 29832 | 0 | 0 |
T10 | 3898788 | 3896604 | 0 | 0 |
T11 | 917520 | 915534 | 0 | 0 |
T12 | 30876 | 30474 | 0 | 0 |
T13 | 783204 | 782904 | 0 | 0 |
T20 | 950700 | 950382 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 172905732 | 172783605 | 0 | 1917 |
T1 | 13782 | 13599 | 0 | 9 |
T2 | 18846 | 18678 | 0 | 9 |
T3 | 6528 | 6297 | 0 | 9 |
T7 | 14238 | 14043 | 0 | 9 |
T9 | 15072 | 14907 | 0 | 9 |
T10 | 1949394 | 1948257 | 0 | 9 |
T11 | 458760 | 457722 | 0 | 9 |
T12 | 15438 | 15228 | 0 | 9 |
T13 | 391602 | 391443 | 0 | 9 |
T20 | 475350 | 475182 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 172905732 | 172788807 | 0 | 0 |
T1 | 13782 | 13608 | 0 | 0 |
T2 | 18846 | 18687 | 0 | 0 |
T3 | 6528 | 6306 | 0 | 0 |
T7 | 14238 | 14052 | 0 | 0 |
T9 | 15072 | 14916 | 0 | 0 |
T10 | 1949394 | 1948302 | 0 | 0 |
T11 | 458760 | 457767 | 0 | 0 |
T12 | 15438 | 15237 | 0 | 0 |
T13 | 391602 | 391452 | 0 | 0 |
T20 | 475350 | 475191 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 213 | 213 | 0 | 0 |
OutputsKnown_A | 57635244 | 57596269 | 0 | 0 |
gen_flops.OutputDelay_A | 57635244 | 57594535 | 0 | 639 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 213 | 213 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57635244 | 57596269 | 0 | 0 |
T1 | 4594 | 4536 | 0 | 0 |
T2 | 6282 | 6229 | 0 | 0 |
T3 | 2176 | 2102 | 0 | 0 |
T7 | 4746 | 4684 | 0 | 0 |
T9 | 5024 | 4972 | 0 | 0 |
T10 | 649798 | 649434 | 0 | 0 |
T11 | 152920 | 152589 | 0 | 0 |
T12 | 5146 | 5079 | 0 | 0 |
T13 | 130534 | 130484 | 0 | 0 |
T20 | 158450 | 158397 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57635244 | 57594535 | 0 | 639 |
T1 | 4594 | 4533 | 0 | 3 |
T2 | 6282 | 6226 | 0 | 3 |
T3 | 2176 | 2099 | 0 | 3 |
T7 | 4746 | 4681 | 0 | 3 |
T9 | 5024 | 4969 | 0 | 3 |
T10 | 649798 | 649419 | 0 | 3 |
T11 | 152920 | 152574 | 0 | 3 |
T12 | 5146 | 5076 | 0 | 3 |
T13 | 130534 | 130481 | 0 | 3 |
T20 | 158450 | 158394 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 213 | 213 | 0 | 0 |
OutputsKnown_A | 57635244 | 57596269 | 0 | 0 |
gen_flops.OutputDelay_A | 57635244 | 57594535 | 0 | 639 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 213 | 213 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57635244 | 57596269 | 0 | 0 |
T1 | 4594 | 4536 | 0 | 0 |
T2 | 6282 | 6229 | 0 | 0 |
T3 | 2176 | 2102 | 0 | 0 |
T7 | 4746 | 4684 | 0 | 0 |
T9 | 5024 | 4972 | 0 | 0 |
T10 | 649798 | 649434 | 0 | 0 |
T11 | 152920 | 152589 | 0 | 0 |
T12 | 5146 | 5079 | 0 | 0 |
T13 | 130534 | 130484 | 0 | 0 |
T20 | 158450 | 158397 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57635244 | 57594535 | 0 | 639 |
T1 | 4594 | 4533 | 0 | 3 |
T2 | 6282 | 6226 | 0 | 3 |
T3 | 2176 | 2099 | 0 | 3 |
T7 | 4746 | 4681 | 0 | 3 |
T9 | 5024 | 4969 | 0 | 3 |
T10 | 649798 | 649419 | 0 | 3 |
T11 | 152920 | 152574 | 0 | 3 |
T12 | 5146 | 5076 | 0 | 3 |
T13 | 130534 | 130481 | 0 | 3 |
T20 | 158450 | 158394 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 213 | 213 | 0 | 0 |
OutputsKnown_A | 57635244 | 57596269 | 0 | 0 |
gen_no_flops.OutputDelay_A | 57635244 | 57596269 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 213 | 213 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57635244 | 57596269 | 0 | 0 |
T1 | 4594 | 4536 | 0 | 0 |
T2 | 6282 | 6229 | 0 | 0 |
T3 | 2176 | 2102 | 0 | 0 |
T7 | 4746 | 4684 | 0 | 0 |
T9 | 5024 | 4972 | 0 | 0 |
T10 | 649798 | 649434 | 0 | 0 |
T11 | 152920 | 152589 | 0 | 0 |
T12 | 5146 | 5079 | 0 | 0 |
T13 | 130534 | 130484 | 0 | 0 |
T20 | 158450 | 158397 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57635244 | 57596269 | 0 | 0 |
T1 | 4594 | 4536 | 0 | 0 |
T2 | 6282 | 6229 | 0 | 0 |
T3 | 2176 | 2102 | 0 | 0 |
T7 | 4746 | 4684 | 0 | 0 |
T9 | 5024 | 4972 | 0 | 0 |
T10 | 649798 | 649434 | 0 | 0 |
T11 | 152920 | 152589 | 0 | 0 |
T12 | 5146 | 5079 | 0 | 0 |
T13 | 130534 | 130484 | 0 | 0 |
T20 | 158450 | 158397 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 213 | 213 | 0 | 0 |
OutputsKnown_A | 57635244 | 57596269 | 0 | 0 |
gen_flops.OutputDelay_A | 57635244 | 57594535 | 0 | 639 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 213 | 213 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57635244 | 57596269 | 0 | 0 |
T1 | 4594 | 4536 | 0 | 0 |
T2 | 6282 | 6229 | 0 | 0 |
T3 | 2176 | 2102 | 0 | 0 |
T7 | 4746 | 4684 | 0 | 0 |
T9 | 5024 | 4972 | 0 | 0 |
T10 | 649798 | 649434 | 0 | 0 |
T11 | 152920 | 152589 | 0 | 0 |
T12 | 5146 | 5079 | 0 | 0 |
T13 | 130534 | 130484 | 0 | 0 |
T20 | 158450 | 158397 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57635244 | 57594535 | 0 | 639 |
T1 | 4594 | 4533 | 0 | 3 |
T2 | 6282 | 6226 | 0 | 3 |
T3 | 2176 | 2099 | 0 | 3 |
T7 | 4746 | 4681 | 0 | 3 |
T9 | 5024 | 4969 | 0 | 3 |
T10 | 649798 | 649419 | 0 | 3 |
T11 | 152920 | 152574 | 0 | 3 |
T12 | 5146 | 5076 | 0 | 3 |
T13 | 130534 | 130481 | 0 | 3 |
T20 | 158450 | 158394 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 213 | 213 | 0 | 0 |
OutputsKnown_A | 57635244 | 57596269 | 0 | 0 |
gen_no_flops.OutputDelay_A | 57635244 | 57596269 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 213 | 213 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57635244 | 57596269 | 0 | 0 |
T1 | 4594 | 4536 | 0 | 0 |
T2 | 6282 | 6229 | 0 | 0 |
T3 | 2176 | 2102 | 0 | 0 |
T7 | 4746 | 4684 | 0 | 0 |
T9 | 5024 | 4972 | 0 | 0 |
T10 | 649798 | 649434 | 0 | 0 |
T11 | 152920 | 152589 | 0 | 0 |
T12 | 5146 | 5079 | 0 | 0 |
T13 | 130534 | 130484 | 0 | 0 |
T20 | 158450 | 158397 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57635244 | 57596269 | 0 | 0 |
T1 | 4594 | 4536 | 0 | 0 |
T2 | 6282 | 6229 | 0 | 0 |
T3 | 2176 | 2102 | 0 | 0 |
T7 | 4746 | 4684 | 0 | 0 |
T9 | 5024 | 4972 | 0 | 0 |
T10 | 649798 | 649434 | 0 | 0 |
T11 | 152920 | 152589 | 0 | 0 |
T12 | 5146 | 5079 | 0 | 0 |
T13 | 130534 | 130484 | 0 | 0 |
T20 | 158450 | 158397 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 213 | 213 | 0 | 0 |
OutputsKnown_A | 57635244 | 57596269 | 0 | 0 |
gen_no_flops.OutputDelay_A | 57635244 | 57596269 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 213 | 213 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57635244 | 57596269 | 0 | 0 |
T1 | 4594 | 4536 | 0 | 0 |
T2 | 6282 | 6229 | 0 | 0 |
T3 | 2176 | 2102 | 0 | 0 |
T7 | 4746 | 4684 | 0 | 0 |
T9 | 5024 | 4972 | 0 | 0 |
T10 | 649798 | 649434 | 0 | 0 |
T11 | 152920 | 152589 | 0 | 0 |
T12 | 5146 | 5079 | 0 | 0 |
T13 | 130534 | 130484 | 0 | 0 |
T20 | 158450 | 158397 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57635244 | 57596269 | 0 | 0 |
T1 | 4594 | 4536 | 0 | 0 |
T2 | 6282 | 6229 | 0 | 0 |
T3 | 2176 | 2102 | 0 | 0 |
T7 | 4746 | 4684 | 0 | 0 |
T9 | 5024 | 4972 | 0 | 0 |
T10 | 649798 | 649434 | 0 | 0 |
T11 | 152920 | 152589 | 0 | 0 |
T12 | 5146 | 5079 | 0 | 0 |
T13 | 130534 | 130484 | 0 | 0 |
T20 | 158450 | 158397 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |