Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201525	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	563930	1		T4	12		T5	8		T6	10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	472235	1		T5	6		T6	1		T29	1
values[0x0]	142529	1		T8	1		T4	13		T5	7
values[0x1]	150691	1		T4	16		T5	13		T6	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	152385	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	613070	1		T4	14		T5	13		T6	14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3397	1		T63	24		T67	18		T99	14
valid_sources[0x01]	3134	1		T4	1		T5	1		T35	3
valid_sources[0x02]	2547	1		T13	1		T63	14		T66	1
valid_sources[0x03]	4119	1		T5	1		T165	1		T170	1
valid_sources[0x04]	2479	1		T45	16		T17	1		T165	1
valid_sources[0x05]	2652	1		T35	1		T170	1		T13	1
valid_sources[0x06]	3323	1		T80	2		T37	1		T63	25
valid_sources[0x07]	3140	1		T17	1		T66	1		T67	71
valid_sources[0x08]	3322	1		T5	1		T66	8		T67	3
valid_sources[0x09]	3258	1		T17	1		T41	1		T165	1
valid_sources[0x0a]	2904	1		T18	2		T168	1		T63	13
valid_sources[0x0b]	5293	1		T34	1		T98	2		T172	2
valid_sources[0x0c]	3141	1		T18	2		T138	1		T165	1
valid_sources[0x0d]	3324	1		T63	11		T66	7		T67	12
valid_sources[0x0e]	2837	1		T36	80		T66	3		T67	9
valid_sources[0x0f]	3160	1		T6	4		T18	2		T63	8
valid_sources[0x10]	2698	1		T24	1		T66	13		T67	29
valid_sources[0x11]	2449	1		T12	3		T66	1		T99	13
valid_sources[0x12]	3732	1		T35	1		T192	1		T13	1
valid_sources[0x13]	2373	1		T172	1		T63	17		T66	2
valid_sources[0x14]	3068	1		T193	1		T172	1		T37	1
valid_sources[0x15]	2588	1		T13	2		T66	6		T67	4
valid_sources[0x16]	2537	1		T177	1		T63	28		T66	7
valid_sources[0x17]	2987	1		T37	1		T63	20		T66	6
valid_sources[0x18]	3065	1		T177	1		T63	39		T66	9
valid_sources[0x19]	2530	1		T18	1		T98	4		T41	1
valid_sources[0x1a]	2921	1		T63	115		T66	1		T99	18
valid_sources[0x1b]	2869	1		T63	54		T66	4		T67	9
valid_sources[0x1c]	3149	1		T46	1		T194	1		T66	5
valid_sources[0x1d]	2469	1		T23	1		T43	1		T99	9
valid_sources[0x1e]	2641	1		T18	1		T24	2		T14	1
valid_sources[0x1f]	2673	1		T13	1		T37	1		T63	20
valid_sources[0x20]	2707	1		T13	1		T63	22		T66	6
valid_sources[0x21]	3062	1		T35	1		T195	1		T63	5
valid_sources[0x22]	2673	1		T35	1		T172	5		T66	1
valid_sources[0x23]	2715	1		T4	1		T47	9		T66	4
valid_sources[0x24]	2585	1		T195	1		T37	2		T66	7
valid_sources[0x25]	2844	1		T18	1		T168	1		T169	1
valid_sources[0x26]	2474	1		T81	15		T63	28		T67	13
valid_sources[0x27]	2629	1		T17	1		T168	1		T43	1
valid_sources[0x28]	2519	1		T24	1		T66	5		T67	19
valid_sources[0x29]	2808	1		T35	3		T37	1		T63	22
valid_sources[0x2a]	2652	1		T19	10		T63	22		T66	2
valid_sources[0x2b]	2860	1		T8	1		T17	1		T177	3
valid_sources[0x2c]	2813	1		T4	1		T193	1		T46	1
valid_sources[0x2d]	2711	1		T46	1		T37	2		T63	9
valid_sources[0x2e]	3394	1		T4	1		T17	1		T63	164
valid_sources[0x2f]	3066	1		T35	1		T18	1		T63	59
valid_sources[0x30]	3116	1		T63	27		T66	2		T67	5
valid_sources[0x31]	2562	1		T20	1		T173	1		T63	8
valid_sources[0x32]	3511	1		T170	1		T37	1		T63	58
valid_sources[0x33]	3000	1		T18	1		T172	2		T63	17
valid_sources[0x34]	2815	1		T66	7		T67	4		T99	8
valid_sources[0x35]	2999	1		T66	4		T99	1		T65	1
valid_sources[0x36]	2768	1		T37	1		T63	19		T66	8
valid_sources[0x37]	3312	1		T37	1		T63	24		T66	4
valid_sources[0x38]	3474	1		T6	3		T63	5		T66	5
valid_sources[0x39]	2527	1		T80	2		T13	1		T63	6
valid_sources[0x3a]	2910	1		T13	1		T63	76		T66	5
valid_sources[0x3b]	3139	1		T173	1		T66	3		T99	6
valid_sources[0x3c]	2914	1		T63	61		T66	2		T67	8
valid_sources[0x3d]	3376	1		T18	1		T165	1		T63	7
valid_sources[0x3e]	3127	1		T173	1		T63	27		T66	3
valid_sources[0x3f]	2496	1		T6	3		T165	1		T66	7
valid_sources[0x40]	3573	1		T63	43		T66	3		T99	18
valid_sources[0x41]	2896	1		T165	1		T63	3		T66	5
valid_sources[0x42]	5290	1		T18	1		T193	1		T20	2
valid_sources[0x43]	3073	1		T63	14		T66	2		T67	105
valid_sources[0x44]	3266	1		T168	2		T41	1		T63	61
valid_sources[0x45]	2589	1		T66	1		T67	35		T99	4
valid_sources[0x46]	2311	1		T63	10		T66	4		T99	13
valid_sources[0x47]	2824	1		T63	28		T66	2		T99	18
valid_sources[0x48]	2726	1		T13	1		T173	1		T63	20
valid_sources[0x49]	2745	1		T179	1		T41	4		T173	1
valid_sources[0x4a]	2751	1		T63	34		T66	9		T67	22
valid_sources[0x4b]	3170	1		T175	19		T66	6		T67	64
valid_sources[0x4c]	3431	1		T4	1		T23	1		T66	2
valid_sources[0x4d]	2773	1		T18	2		T12	2		T63	19
valid_sources[0x4e]	3370	1		T172	3		T13	2		T173	1
valid_sources[0x4f]	3093	1		T18	1		T63	2		T66	6
valid_sources[0x50]	2713	1		T35	1		T43	1		T63	31
valid_sources[0x51]	2872	1		T46	1		T165	1		T13	2
valid_sources[0x52]	2565	1		T98	3		T24	1		T63	27
valid_sources[0x53]	3057	1		T178	2		T63	13		T66	5
valid_sources[0x54]	2666	1		T177	1		T99	7		T65	2
valid_sources[0x55]	3426	1		T4	1		T41	1		T63	76
valid_sources[0x56]	2940	1		T63	21		T66	1		T67	7
valid_sources[0x57]	3590	1		T169	1		T173	3		T63	31
valid_sources[0x58]	2462	1		T20	1		T63	42		T66	3
valid_sources[0x59]	2738	1		T12	1		T172	3		T63	15
valid_sources[0x5a]	3934	1		T4	1		T35	1		T63	45
valid_sources[0x5b]	3705	1		T10	2		T172	3		T63	2
valid_sources[0x5c]	2865	1		T18	1		T24	1		T23	1
valid_sources[0x5d]	2647	1		T15	14		T80	1		T37	4
valid_sources[0x5e]	2870	1		T98	4		T66	1		T67	23
valid_sources[0x5f]	3205	1		T80	1		T66	7		T99	12
valid_sources[0x60]	2657	1		T35	1		T165	1		T63	89
valid_sources[0x61]	2938	1		T18	1		T12	2		T194	1
valid_sources[0x62]	2900	1		T4	1		T18	1		T10	2
valid_sources[0x63]	2711	1		T17	1		T172	1		T13	1
valid_sources[0x64]	2631	1		T10	1		T63	31		T66	12
valid_sources[0x65]	2884	1		T18	1		T24	2		T172	5
valid_sources[0x66]	2378	1		T63	12		T66	3		T67	43
valid_sources[0x67]	2475	1		T18	1		T13	3		T66	2
valid_sources[0x68]	2591	1		T18	1		T80	1		T63	23
valid_sources[0x69]	2735	1		T63	65		T66	3		T67	6
valid_sources[0x6a]	3437	1		T98	1		T17	1		T170	2
valid_sources[0x6b]	3691	1		T5	6		T172	1		T37	1
valid_sources[0x6c]	2433	1		T46	2		T195	1		T99	3
valid_sources[0x6d]	3580	1		T4	2		T18	1		T170	1
valid_sources[0x6e]	3205	1		T4	2		T35	2		T179	1
valid_sources[0x6f]	4364	1		T16	2		T63	14		T66	2
valid_sources[0x70]	2836	1		T12	2		T63	24		T66	2
valid_sources[0x71]	3183	1		T80	4		T173	1		T63	24
valid_sources[0x72]	2667	1		T12	2		T63	11		T66	6
valid_sources[0x73]	2618	1		T4	1		T13	1		T63	7
valid_sources[0x74]	2404	1		T12	4		T196	1		T63	54
valid_sources[0x75]	3629	1		T13	2		T63	42		T66	3
valid_sources[0x76]	2742	1		T18	1		T63	1		T66	3
valid_sources[0x77]	3525	1		T17	1		T63	38		T66	1
valid_sources[0x78]	3632	1		T11	3		T13	2		T43	2
valid_sources[0x79]	3443	1		T63	3		T66	9		T67	60
valid_sources[0x7a]	2529	1		T63	4		T67	10		T99	20
valid_sources[0x7b]	2538	1		T193	1		T63	8		T66	4
valid_sources[0x7c]	3138	1		T63	1		T66	6		T67	9
valid_sources[0x7d]	3078	1		T22	1		T63	21		T66	1
valid_sources[0x7e]	3194	1		T23	1		T63	4		T66	9
valid_sources[0x7f]	3528	1		T63	12		T66	9		T67	9
valid_sources[0x80]	3107	1		T170	2		T63	4		T66	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

283320

1

T5

2

T29

1

T35

4

values[0x0]

all_enables

biggest_size

140344

1

T4

5

T5

2

T6

5

values[0x1]

all_enables

biggest_size

140266

1

T4

7

T5

4

T6

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4831	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	24025	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9868	1		T63	32		T66	6		T67	19
values[0x0]	9382	1		T1	1		T26	2		T7	1
values[0x1]	9606	1		T2	1		T3	1		T25	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3646	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	25210	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	84	1		T197	9		T198	1		T193	1
valid_sources[0x01]	103	1		T198	1		T65	4		T49	7
valid_sources[0x02]	153	1		T107	1		T199	1		T24	1
valid_sources[0x03]	93	1		T44	5		T65	2		T49	8
valid_sources[0x04]	99	1		T64	7		T65	1		T49	5
valid_sources[0x05]	88	1		T35	1		T152	1		T200	1
valid_sources[0x06]	89	1		T201	1		T63	1		T49	4
valid_sources[0x07]	130	1		T202	1		T49	5		T92	2
valid_sources[0x08]	81	1		T74	1		T65	2		T49	5
valid_sources[0x09]	78	1		T203	1		T198	1		T204	1
valid_sources[0x0a]	70	1		T4	1		T171	1		T65	1
valid_sources[0x0b]	93	1		T110	1		T205	4		T67	1
valid_sources[0x0c]	92	1		T22	1		T65	1		T49	6
valid_sources[0x0d]	99	1		T65	4		T49	7		T102	3
valid_sources[0x0e]	272	1		T174	3		T206	1		T167	1
valid_sources[0x0f]	319	1		T54	1		T203	1		T81	1
valid_sources[0x10]	73	1		T6	3		T204	2		T168	1
valid_sources[0x11]	77	1		T207	1		T65	1		T49	6
valid_sources[0x12]	115	1		T208	1		T65	6		T49	2
valid_sources[0x13]	116	1		T107	1		T16	1		T65	2
valid_sources[0x14]	70	1		T5	2		T59	3		T209	1
valid_sources[0x15]	104	1		T210	1		T208	1		T211	1
valid_sources[0x16]	104	1		T198	1		T149	1		T65	3
valid_sources[0x17]	76	1		T109	2		T63	7		T65	4
valid_sources[0x18]	96	1		T212	1		T213	2		T65	4
valid_sources[0x19]	77	1		T28	1		T65	3		T49	7
valid_sources[0x1a]	151	1		T20	1		T153	1		T65	1
valid_sources[0x1b]	147	1		T60	1		T4	1		T198	1
valid_sources[0x1c]	72	1		T65	2		T49	9		T92	1
valid_sources[0x1d]	102	1		T214	1		T99	1		T65	3
valid_sources[0x1e]	123	1		T85	1		T65	6		T49	3
valid_sources[0x1f]	67	1		T198	1		T65	3		T49	4
valid_sources[0x20]	80	1		T35	1		T148	2		T215	1
valid_sources[0x21]	92	1		T216	1		T65	9		T49	6
valid_sources[0x22]	104	1		T198	1		T24	1		T65	2
valid_sources[0x23]	113	1		T29	1		T154	2		T167	2
valid_sources[0x24]	91	1		T210	1		T149	3		T14	1
valid_sources[0x25]	101	1		T54	1		T200	1		T213	2
valid_sources[0x26]	97	1		T202	2		T200	1		T201	1
valid_sources[0x27]	80	1		T217	1		T214	1		T153	1
valid_sources[0x28]	112	1		T40	2		T70	1		T12	1
valid_sources[0x29]	72	1		T200	1		T64	7		T49	4
valid_sources[0x2a]	84	1		T38	1		T65	2		T49	11
valid_sources[0x2b]	127	1		T111	1		T198	1		T84	1
valid_sources[0x2c]	120	1		T217	1		T164	1		T65	4
valid_sources[0x2d]	95	1		T216	2		T208	1		T99	1
valid_sources[0x2e]	237	1		T79	1		T65	4		T49	6
valid_sources[0x2f]	102	1		T110	1		T206	1		T65	2
valid_sources[0x30]	67	1		T18	2		T19	1		T218	1
valid_sources[0x31]	100	1		T167	1		T65	4		T49	3
valid_sources[0x32]	176	1		T45	5		T200	1		T208	1
valid_sources[0x33]	103	1		T200	1		T64	3		T65	3
valid_sources[0x34]	78	1		T149	4		T65	1		T49	5
valid_sources[0x35]	138	1		T110	1		T219	1		T65	7
valid_sources[0x36]	228	1		T210	1		T173	1		T65	5
valid_sources[0x37]	125	1		T53	2		T31	11		T67	1
valid_sources[0x38]	100	1		T65	5		T49	3		T92	1
valid_sources[0x39]	72	1		T61	1		T35	1		T220	1
valid_sources[0x3a]	142	1		T221	1		T49	5		T93	1
valid_sources[0x3b]	102	1		T110	1		T222	3		T223	1
valid_sources[0x3c]	85	1		T1	1		T153	2		T201	1
valid_sources[0x3d]	68	1		T217	1		T65	4		T49	7
valid_sources[0x3e]	96	1		T12	1		T49	8		T92	2
valid_sources[0x3f]	91	1		T110	1		T98	8		T63	10
valid_sources[0x40]	142	1		T65	9		T49	3		T102	3
valid_sources[0x41]	98	1		T36	1		T224	1		T211	3
valid_sources[0x42]	144	1		T213	1		T225	11		T201	1
valid_sources[0x43]	100	1		T4	1		T35	1		T67	2
valid_sources[0x44]	102	1		T220	1		T206	1		T65	4
valid_sources[0x45]	95	1		T3	1		T110	1		T64	4
valid_sources[0x46]	115	1		T8	1		T86	1		T111	1
valid_sources[0x47]	77	1		T35	1		T200	1		T67	1
valid_sources[0x48]	118	1		T38	5		T35	1		T210	1
valid_sources[0x49]	113	1		T208	1		T153	1		T206	2
valid_sources[0x4a]	124	1		T143	4		T209	2		T13	9
valid_sources[0x4b]	82	1		T226	1		T99	1		T65	2
valid_sources[0x4c]	110	1		T65	6		T49	6		T92	3
valid_sources[0x4d]	118	1		T65	3		T49	1		T92	5
valid_sources[0x4e]	113	1		T109	1		T65	3		T49	9
valid_sources[0x4f]	76	1		T84	1		T99	1		T65	2
valid_sources[0x50]	158	1		T65	2		T49	8		T93	3
valid_sources[0x51]	75	1		T151	1		T219	1		T99	1
valid_sources[0x52]	106	1		T227	1		T228	1		T201	1
valid_sources[0x53]	75	1		T217	1		T229	1		T230	1
valid_sources[0x54]	100	1		T71	7		T231	12		T208	1
valid_sources[0x55]	82	1		T148	1		T85	1		T230	1
valid_sources[0x56]	93	1		T176	3		T232	14		T65	1
valid_sources[0x57]	63	1		T18	1		T16	6		T23	1
valid_sources[0x58]	131	1		T65	5		T49	3		T92	1
valid_sources[0x59]	118	1		T198	1		T217	1		T171	1
valid_sources[0x5a]	104	1		T209	1		T65	1		T49	3
valid_sources[0x5b]	66	1		T157	1		T65	1		T49	7
valid_sources[0x5c]	142	1		T198	1		T158	1		T167	1
valid_sources[0x5d]	99	1		T198	1		T18	2		T148	1
valid_sources[0x5e]	103	1		T111	1		T23	1		T65	12
valid_sources[0x5f]	90	1		T5	1		T35	1		T198	2
valid_sources[0x60]	104	1		T198	1		T233	1		T219	1
valid_sources[0x61]	118	1		T167	1		T64	6		T65	5
valid_sources[0x62]	283	1		T234	1		T65	1		T49	12
valid_sources[0x63]	226	1		T54	1		T85	1		T65	2
valid_sources[0x64]	102	1		T216	1		T235	4		T65	5
valid_sources[0x65]	74	1		T4	1		T236	9		T237	1
valid_sources[0x66]	178	1		T204	1		T238	2		T22	1
valid_sources[0x67]	145	1		T67	2		T65	3		T49	4
valid_sources[0x68]	60	1		T65	1		T49	5		T95	1
valid_sources[0x69]	49	1		T27	1		T65	2		T49	5
valid_sources[0x6a]	133	1		T152	1		T151	1		T65	1
valid_sources[0x6b]	97	1		T65	2		T49	7		T92	2
valid_sources[0x6c]	104	1		T64	7		T65	6		T49	2
valid_sources[0x6d]	87	1		T173	1		T65	2		T49	7
valid_sources[0x6e]	103	1		T203	2		T239	17		T65	2
valid_sources[0x6f]	124	1		T214	1		T240	1		T63	7
valid_sources[0x70]	89	1		T10	1		T230	1		T168	2
valid_sources[0x71]	98	1		T241	1		T33	1		T169	7
valid_sources[0x72]	61	1		T242	1		T208	1		T65	2
valid_sources[0x73]	105	1		T199	5		T243	8		T65	4
valid_sources[0x74]	105	1		T83	3		T65	5		T49	3
valid_sources[0x75]	93	1		T72	1		T195	1		T63	2
valid_sources[0x76]	269	1		T22	1		T168	1		T244	9
valid_sources[0x77]	99	1		T7	1		T18	1		T83	2
valid_sources[0x78]	79	1		T234	2		T235	1		T65	2
valid_sources[0x79]	65	1		T18	1		T24	1		T65	1
valid_sources[0x7a]	210	1		T220	1		T209	1		T245	1
valid_sources[0x7b]	160	1		T110	1		T202	1		T22	1
valid_sources[0x7c]	160	1		T51	5		T17	3		T65	1
valid_sources[0x7d]	74	1		T5	1		T109	2		T65	3
valid_sources[0x7e]	248	1		T246	1		T178	1		T65	4
valid_sources[0x7f]	109	1		T109	1		T210	2		T65	1
valid_sources[0x80]	111	1		T80	1		T170	6		T65	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7188

1

T63

9

T66

4

T67

19

values[0x0]

all_enables

biggest_size

8600

1

T1

1

T26

2

T7

1

values[0x1]

all_enables

biggest_size

8237

1

T2

1

T3

1

T25

1