Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	264394	1		T4	17		T5	18		T6	20
full_word	566385	1		T4	12		T5	8		T6	10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	830449	1		T4	29		T5	26		T6	30
auto[TlIntgErrCmd]	109	1		T63	3		T64	3		T139	6
auto[TlIntgErrData]	113	1		T63	4		T64	3		T139	8
auto[TlIntgErrBoth]	108	1		T63	3		T64	4		T139	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	475097	1		T5	6		T6	1		T29	1
auto[1]	355682	1		T4	29		T5	20		T6	29

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	191342	1		T5	4		T6	1		T35	2
auto[TlIntgErrNone]	partial	auto[1]	72751	1		T4	17		T5	14		T6	19
auto[TlIntgErrNone]	full_word	auto[0]	283605	1		T5	2		T29	1		T35	4
auto[TlIntgErrNone]	full_word	auto[1]	282751	1		T4	12		T5	6		T6	10
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T63	2		T139	1		T181	5
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T63	1		T64	3		T139	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T181	1		T183	1		T185	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T181	1		T185	1		T186	1
auto[TlIntgErrData]	partial	auto[0]	63	1		T63	3		T64	2		T139	4
auto[TlIntgErrData]	partial	auto[1]	43	1		T63	1		T64	1		T139	4
auto[TlIntgErrData]	full_word	auto[0]	4	1		T187	1		T188	1		T184	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T189	1		T183	1		T188	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T64	1		T139	3		T181	3
auto[TlIntgErrBoth]	partial	auto[1]	62	1		T63	3		T64	2		T139	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T64	1		T190	1		T184	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1		T139	1		T181	1		T191	3