Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.12 96.97 59.57 91.58 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 133321598 22212 0 0
late_debug_enable_rd_A 133321598 4319 0 0
late_debug_enable_regwen_rd_A 133321598 3669 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 133321598 22212 0 0
T49 304673 2426 0 0
T50 537450 4201 0 0
T63 111880 3 0 0
T64 91299 1 0 0
T65 7047 652 0 0
T92 16190 430 0 0
T93 16882 47 0 0
T94 8793 18 0 0
T95 16234 771 0 0
T96 660689 86 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 133321598 4319 0 0
T49 304673 783 0 0
T97 14623 42 0 0
T99 22476 25 0 0
T103 27879 23 0 0
T104 8682 10 0 0
T112 157292 29 0 0
T120 8581 18 0 0
T139 96014 87 0 0
T140 134652 10 0 0
T141 20051 85 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 133321598 3669 0 0
T49 304673 699 0 0
T97 14623 23 0 0
T99 22476 19 0 0
T103 27879 21 0 0
T104 8682 4 0 0
T112 157292 18 0 0
T120 8581 6 0 0
T139 96014 94 0 0
T140 134652 18 0 0
T141 20051 51 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%