Module Definition
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Module : prim_mubi8_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.12 96.97 59.57 91.58 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[7].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_mubi8_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 4 4


Assert Coverage for Module : prim_mubi8_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 213 213 0 0
OutputsKnown_A 42500714 42461531 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 42500714 42459752 0 639


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 213 213 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T38 1 1 0 0
T48 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 42500714 42461531 0 0
T1 458014 457949 0 0
T2 37967 37886 0 0
T3 32290 32212 0 0
T7 5292 5232 0 0
T8 2129 2066 0 0
T25 176378 176291 0 0
T26 216618 216381 0 0
T27 271874 271660 0 0
T38 1968 1912 0 0
T48 35262 35211 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 42500714 42459752 0 639
T1 458014 457946 0 3
T2 37967 37883 0 3
T3 32290 32209 0 3
T7 5292 5229 0 3
T8 2129 2063 0 3
T25 176378 176288 0 3
T26 216618 216369 0 3
T27 271874 271651 0 3
T38 1968 1909 0 3
T48 35262 35208 0 3

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