Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	87.50	100.00					75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm_enable_checker

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
36	1	1

---

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	42500714	4785822	0	0
MemTLResponseWithoutDebugIsError_A	42500714	10	0	0
NdmResetAckNeedsDebug_A	42500714	0	0	0
SbaTLRequestNeedsDebug_A	42500714	13371	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42500714	4785822	0	0
T4	273401	180864	0	0
T5	0	187074	0	0
T6	0	98565	0	0
T10	0	145974	0	0
T15	0	102307	0	0
T18	0	481414	0	0
T28	37692	0	0	0
T30	133007	0	0	0
T34	0	7530	0	0
T35	0	197277	0	0
T44	314522	100522	0	0
T45	0	44164	0	0
T54	2587	0	0	0
T55	1369	0	0	0
T62	4994	0	0	0
T69	18007	0	0	0
T86	795407	0	0	0
T87	358620	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42500714	10	0	0
T4	273401	0	0	0
T8	2129	4	0	0
T9	31696	0	0	0
T30	133007	0	0	0
T39	143270	0	0	0
T40	51094	0	0	0
T48	35262	0	0	0
T52	0	6	0	0
T53	204159	0	0	0
T60	750340	0	0	0
T61	40313	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42500714	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42500714	13371	0	0
T1	458014	91	0	0
T2	37967	86	0	0
T3	32290	52	0	0
T7	5292	0	0	0
T8	2129	0	0	0
T25	176378	32	0	0
T26	216618	13	0	0
T27	271874	765	0	0
T38	1968	0	0	0
T39	0	97	0	0
T48	35262	12	0	0
T53	0	4	0	0
T60	0	82	0	0