Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9370128 |
9368844 |
0 |
0 |
selKnown1 |
49147373 |
49146089 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9370128 |
9368844 |
0 |
0 |
T1 |
24973 |
24971 |
0 |
0 |
T2 |
25895 |
25893 |
0 |
0 |
T3 |
18045 |
18043 |
0 |
0 |
T4 |
0 |
16 |
0 |
0 |
T5 |
0 |
8 |
0 |
0 |
T6 |
0 |
28 |
0 |
0 |
T7 |
1762 |
1758 |
0 |
0 |
T8 |
651 |
647 |
0 |
0 |
T25 |
18211 |
18209 |
0 |
0 |
T26 |
22741 |
22737 |
0 |
0 |
T27 |
110146 |
110142 |
0 |
0 |
T31 |
0 |
20 |
0 |
0 |
T38 |
922 |
918 |
0 |
0 |
T39 |
2 |
0 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T44 |
0 |
10 |
0 |
0 |
T48 |
13772 |
13768 |
0 |
0 |
T53 |
4 |
2 |
0 |
0 |
T59 |
0 |
8 |
0 |
0 |
T60 |
2 |
0 |
0 |
0 |
T61 |
2 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49147373 |
49146089 |
0 |
0 |
T1 |
470500 |
470498 |
0 |
0 |
T2 |
50914 |
50912 |
0 |
0 |
T3 |
41312 |
41310 |
0 |
0 |
T4 |
0 |
2 |
0 |
0 |
T5 |
0 |
8 |
0 |
0 |
T6 |
0 |
6 |
0 |
0 |
T7 |
6174 |
6170 |
0 |
0 |
T8 |
2455 |
2451 |
0 |
0 |
T25 |
185483 |
185481 |
0 |
0 |
T26 |
227992 |
227988 |
0 |
0 |
T27 |
326950 |
326946 |
0 |
0 |
T31 |
0 |
20 |
0 |
0 |
T38 |
2430 |
2426 |
0 |
0 |
T39 |
2 |
0 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T44 |
0 |
8 |
0 |
0 |
T48 |
42149 |
42145 |
0 |
0 |
T53 |
4 |
2 |
0 |
0 |
T59 |
0 |
8 |
0 |
0 |
T60 |
2 |
0 |
0 |
0 |
T61 |
2 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2722706 |
2722493 |
0 |
0 |
selKnown1 |
42500714 |
42500501 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2722706 |
2722493 |
0 |
0 |
T1 |
12486 |
12485 |
0 |
0 |
T2 |
12947 |
12946 |
0 |
0 |
T3 |
9022 |
9021 |
0 |
0 |
T7 |
880 |
879 |
0 |
0 |
T8 |
324 |
323 |
0 |
0 |
T25 |
9105 |
9104 |
0 |
0 |
T26 |
11366 |
11365 |
0 |
0 |
T27 |
55070 |
55069 |
0 |
0 |
T38 |
460 |
459 |
0 |
0 |
T48 |
6885 |
6884 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
42500714 |
42500501 |
0 |
0 |
T1 |
458014 |
458013 |
0 |
0 |
T2 |
37967 |
37966 |
0 |
0 |
T3 |
32290 |
32289 |
0 |
0 |
T7 |
5292 |
5291 |
0 |
0 |
T8 |
2129 |
2128 |
0 |
0 |
T25 |
176378 |
176377 |
0 |
0 |
T26 |
216618 |
216617 |
0 |
0 |
T27 |
271874 |
271873 |
0 |
0 |
T38 |
1968 |
1967 |
0 |
0 |
T48 |
35262 |
35261 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
781 |
568 |
0 |
0 |
T4 |
0 |
8 |
0 |
0 |
T5 |
0 |
4 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T26 |
4 |
3 |
0 |
0 |
T27 |
3 |
2 |
0 |
0 |
T31 |
0 |
10 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T44 |
0 |
4 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T53 |
2 |
1 |
0 |
0 |
T59 |
0 |
4 |
0 |
0 |
T60 |
1 |
0 |
0 |
0 |
T61 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
593 |
380 |
0 |
0 |
T4 |
0 |
1 |
0 |
0 |
T5 |
0 |
4 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T26 |
4 |
3 |
0 |
0 |
T27 |
3 |
2 |
0 |
0 |
T31 |
0 |
10 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T44 |
0 |
4 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T53 |
2 |
1 |
0 |
0 |
T59 |
0 |
4 |
0 |
0 |
T60 |
1 |
0 |
0 |
0 |
T61 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6644575 |
6644146 |
0 |
0 |
selKnown1 |
6644377 |
6643948 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6644575 |
6644146 |
0 |
0 |
T1 |
12487 |
12486 |
0 |
0 |
T2 |
12948 |
12947 |
0 |
0 |
T3 |
9023 |
9022 |
0 |
0 |
T7 |
880 |
879 |
0 |
0 |
T8 |
325 |
324 |
0 |
0 |
T25 |
9106 |
9105 |
0 |
0 |
T26 |
11367 |
11366 |
0 |
0 |
T27 |
55070 |
55069 |
0 |
0 |
T38 |
460 |
459 |
0 |
0 |
T48 |
6885 |
6884 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6644377 |
6643948 |
0 |
0 |
T1 |
12486 |
12485 |
0 |
0 |
T2 |
12947 |
12946 |
0 |
0 |
T3 |
9022 |
9021 |
0 |
0 |
T7 |
880 |
879 |
0 |
0 |
T8 |
324 |
323 |
0 |
0 |
T25 |
9105 |
9104 |
0 |
0 |
T26 |
11366 |
11365 |
0 |
0 |
T27 |
55070 |
55069 |
0 |
0 |
T38 |
460 |
459 |
0 |
0 |
T48 |
6885 |
6884 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2066 |
1637 |
0 |
0 |
selKnown1 |
1689 |
1260 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2066 |
1637 |
0 |
0 |
T4 |
0 |
8 |
0 |
0 |
T5 |
0 |
4 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T26 |
4 |
3 |
0 |
0 |
T27 |
3 |
2 |
0 |
0 |
T31 |
0 |
10 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T44 |
0 |
6 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T53 |
2 |
1 |
0 |
0 |
T59 |
0 |
4 |
0 |
0 |
T60 |
1 |
0 |
0 |
0 |
T61 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1689 |
1260 |
0 |
0 |
T4 |
0 |
1 |
0 |
0 |
T5 |
0 |
4 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T26 |
4 |
3 |
0 |
0 |
T27 |
3 |
2 |
0 |
0 |
T31 |
0 |
10 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T44 |
0 |
4 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T53 |
2 |
1 |
0 |
0 |
T59 |
0 |
4 |
0 |
0 |
T60 |
1 |
0 |
0 |
0 |
T61 |
1 |
0 |
0 |
0 |