SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 213 | 213 | 0 | 0 |
OutputsKnown_A | 42500714 | 42461531 | 0 | 0 |
gen_no_flops.OutputDelay_A | 42500714 | 42461531 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 213 | 213 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42500714 | 42461531 | 0 | 0 |
T1 | 458014 | 457949 | 0 | 0 |
T2 | 37967 | 37886 | 0 | 0 |
T3 | 32290 | 32212 | 0 | 0 |
T7 | 5292 | 5232 | 0 | 0 |
T8 | 2129 | 2066 | 0 | 0 |
T25 | 176378 | 176291 | 0 | 0 |
T26 | 216618 | 216381 | 0 | 0 |
T27 | 271874 | 271660 | 0 | 0 |
T38 | 1968 | 1912 | 0 | 0 |
T48 | 35262 | 35211 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42500714 | 42461531 | 0 | 0 |
T1 | 458014 | 457949 | 0 | 0 |
T2 | 37967 | 37886 | 0 | 0 |
T3 | 32290 | 32212 | 0 | 0 |
T7 | 5292 | 5232 | 0 | 0 |
T8 | 2129 | 2066 | 0 | 0 |
T25 | 176378 | 176291 | 0 | 0 |
T26 | 216618 | 216381 | 0 | 0 |
T27 | 271874 | 271660 | 0 | 0 |
T38 | 1968 | 1912 | 0 | 0 |
T48 | 35262 | 35211 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |