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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.53 95.32 80.00 89.42 74.36 85.67 98.42 54.56


Total test records in report: 431
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T303 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3069864118 Jul 05 05:25:55 PM PDT 24 Jul 05 05:25:59 PM PDT 24 2498203774 ps
T115 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3794041531 Jul 05 05:26:08 PM PDT 24 Jul 05 05:26:10 PM PDT 24 57052905 ps
T93 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3801475673 Jul 05 05:26:20 PM PDT 24 Jul 05 05:26:30 PM PDT 24 1775043274 ps
T304 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.479291519 Jul 05 05:26:28 PM PDT 24 Jul 05 05:26:31 PM PDT 24 2479802147 ps
T94 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2709635201 Jul 05 05:26:36 PM PDT 24 Jul 05 05:26:56 PM PDT 24 1656119629 ps
T95 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1870773108 Jul 05 05:25:38 PM PDT 24 Jul 05 05:25:43 PM PDT 24 314957736 ps
T305 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3860237100 Jul 05 05:25:55 PM PDT 24 Jul 05 05:25:57 PM PDT 24 414948016 ps
T96 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1761524888 Jul 05 05:26:03 PM PDT 24 Jul 05 05:26:06 PM PDT 24 93749431 ps
T176 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2435839743 Jul 05 05:25:40 PM PDT 24 Jul 05 05:25:52 PM PDT 24 1164419524 ps
T306 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2900821304 Jul 05 05:26:22 PM PDT 24 Jul 05 05:27:14 PM PDT 24 19328909714 ps
T137 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3815140217 Jul 05 05:25:55 PM PDT 24 Jul 05 05:25:59 PM PDT 24 133427093 ps
T116 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.933500695 Jul 05 05:25:36 PM PDT 24 Jul 05 05:26:55 PM PDT 24 3961003864 ps
T307 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1645798328 Jul 05 05:25:57 PM PDT 24 Jul 05 05:26:06 PM PDT 24 2762242255 ps
T308 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2932775338 Jul 05 05:26:37 PM PDT 24 Jul 05 05:26:53 PM PDT 24 5062094211 ps
T108 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3240488195 Jul 05 05:25:36 PM PDT 24 Jul 05 05:25:46 PM PDT 24 5665389953 ps
T309 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.463049485 Jul 05 05:26:24 PM PDT 24 Jul 05 05:26:26 PM PDT 24 375658223 ps
T310 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3036615190 Jul 05 05:25:49 PM PDT 24 Jul 05 05:26:20 PM PDT 24 39378473410 ps
T311 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.266646682 Jul 05 05:25:39 PM PDT 24 Jul 05 05:25:41 PM PDT 24 377794383 ps
T109 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1571423886 Jul 05 05:26:00 PM PDT 24 Jul 05 05:26:10 PM PDT 24 3149664163 ps
T110 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1329672100 Jul 05 05:26:29 PM PDT 24 Jul 05 05:26:33 PM PDT 24 295201646 ps
T312 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4248875294 Jul 05 05:26:29 PM PDT 24 Jul 05 05:26:34 PM PDT 24 4378286194 ps
T313 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3486497099 Jul 05 05:26:34 PM PDT 24 Jul 05 05:26:39 PM PDT 24 3091693642 ps
T117 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.666336393 Jul 05 05:26:14 PM PDT 24 Jul 05 05:26:23 PM PDT 24 1153790070 ps
T111 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.901793307 Jul 05 05:26:47 PM PDT 24 Jul 05 05:26:58 PM PDT 24 4462521497 ps
T174 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1730523274 Jul 05 05:26:36 PM PDT 24 Jul 05 05:26:47 PM PDT 24 1916219473 ps
T314 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2516291484 Jul 05 05:25:54 PM PDT 24 Jul 05 05:25:56 PM PDT 24 134007357 ps
T118 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2663644329 Jul 05 05:26:03 PM PDT 24 Jul 05 05:27:16 PM PDT 24 3855071081 ps
T315 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1466989985 Jul 05 05:26:21 PM PDT 24 Jul 05 05:26:26 PM PDT 24 5152133250 ps
T316 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3390513426 Jul 05 05:26:30 PM PDT 24 Jul 05 05:26:32 PM PDT 24 465858957 ps
T317 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2025018929 Jul 05 05:26:15 PM PDT 24 Jul 05 05:26:16 PM PDT 24 143547296 ps
T318 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.36119963 Jul 05 05:26:27 PM PDT 24 Jul 05 05:26:29 PM PDT 24 1219747208 ps
T319 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1575533986 Jul 05 05:26:29 PM PDT 24 Jul 05 05:28:57 PM PDT 24 56505641232 ps
T320 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2017384800 Jul 05 05:26:35 PM PDT 24 Jul 05 05:26:39 PM PDT 24 119616878 ps
T321 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.307845088 Jul 05 05:25:44 PM PDT 24 Jul 05 05:25:47 PM PDT 24 268762743 ps
T322 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1286869783 Jul 05 05:26:31 PM PDT 24 Jul 05 05:26:35 PM PDT 24 365876176 ps
T323 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.788092228 Jul 05 05:26:04 PM PDT 24 Jul 05 05:26:06 PM PDT 24 268425959 ps
T141 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.825057843 Jul 05 05:26:23 PM PDT 24 Jul 05 05:26:26 PM PDT 24 137917841 ps
T324 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.710497959 Jul 05 05:26:30 PM PDT 24 Jul 05 05:26:46 PM PDT 24 4779518828 ps
T325 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1350889879 Jul 05 05:25:56 PM PDT 24 Jul 05 05:26:07 PM PDT 24 1154929470 ps
T126 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3566822427 Jul 05 05:26:19 PM PDT 24 Jul 05 05:26:22 PM PDT 24 191575713 ps
T326 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.506279307 Jul 05 05:26:00 PM PDT 24 Jul 05 05:26:08 PM PDT 24 13770835912 ps
T327 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.4234294043 Jul 05 05:26:02 PM PDT 24 Jul 05 05:26:13 PM PDT 24 7517834778 ps
T172 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3524377847 Jul 05 05:26:23 PM PDT 24 Jul 05 05:26:28 PM PDT 24 618081898 ps
T328 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2342432463 Jul 05 05:26:39 PM PDT 24 Jul 05 05:26:52 PM PDT 24 9006641977 ps
T329 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3352389532 Jul 05 05:26:14 PM PDT 24 Jul 05 05:26:17 PM PDT 24 200880674 ps
T330 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4244532194 Jul 05 05:25:43 PM PDT 24 Jul 05 05:26:18 PM PDT 24 2579398878 ps
T142 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1784738575 Jul 05 05:26:22 PM PDT 24 Jul 05 05:26:29 PM PDT 24 3970339662 ps
T331 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.456211319 Jul 05 05:26:36 PM PDT 24 Jul 05 05:26:38 PM PDT 24 562984280 ps
T332 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2655983851 Jul 05 05:26:00 PM PDT 24 Jul 05 05:26:01 PM PDT 24 60619325 ps
T333 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1785161221 Jul 05 05:25:59 PM PDT 24 Jul 05 05:26:00 PM PDT 24 38400018 ps
T334 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3453761160 Jul 05 05:26:28 PM PDT 24 Jul 05 05:26:31 PM PDT 24 133646808 ps
T335 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.618232839 Jul 05 05:26:10 PM PDT 24 Jul 05 05:26:16 PM PDT 24 222626355 ps
T336 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1080626696 Jul 05 05:26:18 PM PDT 24 Jul 05 05:26:23 PM PDT 24 1686055525 ps
T337 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2350270699 Jul 05 05:26:35 PM PDT 24 Jul 05 05:26:44 PM PDT 24 13157252287 ps
T338 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.987058125 Jul 05 05:26:43 PM PDT 24 Jul 05 05:26:45 PM PDT 24 248902865 ps
T339 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.778274978 Jul 05 05:26:33 PM PDT 24 Jul 05 05:26:36 PM PDT 24 3620464441 ps
T340 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1976433288 Jul 05 05:25:45 PM PDT 24 Jul 05 05:29:03 PM PDT 24 221577578095 ps
T53 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.800197655 Jul 05 05:25:36 PM PDT 24 Jul 05 05:26:20 PM PDT 24 39729488670 ps
T341 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.923803078 Jul 05 05:26:47 PM PDT 24 Jul 05 05:27:13 PM PDT 24 20533334411 ps
T342 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3947043639 Jul 05 05:26:35 PM PDT 24 Jul 05 05:26:37 PM PDT 24 426697257 ps
T343 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3762830294 Jul 05 05:26:01 PM PDT 24 Jul 05 05:26:07 PM PDT 24 313912041 ps
T344 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2885229059 Jul 05 05:26:14 PM PDT 24 Jul 05 05:26:17 PM PDT 24 1257000986 ps
T345 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3135183376 Jul 05 05:26:07 PM PDT 24 Jul 05 05:26:10 PM PDT 24 907132792 ps
T178 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1263762609 Jul 05 05:26:18 PM PDT 24 Jul 05 05:26:28 PM PDT 24 786459892 ps
T346 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1193110815 Jul 05 05:25:48 PM PDT 24 Jul 05 05:25:50 PM PDT 24 162841312 ps
T347 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2498356588 Jul 05 05:26:20 PM PDT 24 Jul 05 05:26:27 PM PDT 24 2074893565 ps
T348 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.447965543 Jul 05 05:26:37 PM PDT 24 Jul 05 05:26:43 PM PDT 24 388806584 ps
T349 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3298160349 Jul 05 05:25:50 PM PDT 24 Jul 05 05:25:52 PM PDT 24 685408679 ps
T350 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.376617426 Jul 05 05:25:40 PM PDT 24 Jul 05 05:25:42 PM PDT 24 185326244 ps
T54 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3807638293 Jul 05 05:26:20 PM PDT 24 Jul 05 05:27:27 PM PDT 24 64543763973 ps
T351 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1161248517 Jul 05 05:25:41 PM PDT 24 Jul 05 05:26:59 PM PDT 24 46992158821 ps
T352 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1206095147 Jul 05 05:25:57 PM PDT 24 Jul 05 05:26:35 PM PDT 24 26246413085 ps
T353 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1064945546 Jul 05 05:26:45 PM PDT 24 Jul 05 05:27:08 PM PDT 24 8592580073 ps
T354 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.799349246 Jul 05 05:26:34 PM PDT 24 Jul 05 05:26:40 PM PDT 24 244529212 ps
T355 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.288448333 Jul 05 05:25:55 PM PDT 24 Jul 05 05:26:23 PM PDT 24 10080443580 ps
T119 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2329531999 Jul 05 05:26:28 PM PDT 24 Jul 05 05:26:31 PM PDT 24 1111905165 ps
T173 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1789750133 Jul 05 05:26:15 PM PDT 24 Jul 05 05:27:24 PM PDT 24 24464550626 ps
T138 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.650312303 Jul 05 05:26:21 PM PDT 24 Jul 05 05:26:26 PM PDT 24 531925106 ps
T139 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3862912780 Jul 05 05:26:28 PM PDT 24 Jul 05 05:26:34 PM PDT 24 407933850 ps
T356 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.493759704 Jul 05 05:26:30 PM PDT 24 Jul 05 05:26:35 PM PDT 24 297661332 ps
T120 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2521649322 Jul 05 05:26:10 PM PDT 24 Jul 05 05:26:12 PM PDT 24 338223581 ps
T357 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1630612550 Jul 05 05:26:13 PM PDT 24 Jul 05 05:26:17 PM PDT 24 129053492 ps
T127 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4186198803 Jul 05 05:26:42 PM PDT 24 Jul 05 05:26:45 PM PDT 24 1362421614 ps
T358 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3606247833 Jul 05 05:25:41 PM PDT 24 Jul 05 05:25:42 PM PDT 24 49219085 ps
T359 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1909568300 Jul 05 05:26:05 PM PDT 24 Jul 05 05:26:12 PM PDT 24 2221141356 ps
T360 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1458204773 Jul 05 05:26:21 PM PDT 24 Jul 05 05:26:24 PM PDT 24 234286174 ps
T361 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3843450569 Jul 05 05:26:04 PM PDT 24 Jul 05 05:26:05 PM PDT 24 97825900 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3861180477 Jul 05 05:25:43 PM PDT 24 Jul 05 05:26:16 PM PDT 24 2364077545 ps
T363 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1788638657 Jul 05 05:26:10 PM PDT 24 Jul 05 05:26:14 PM PDT 24 874549088 ps
T121 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2921305939 Jul 05 05:27:10 PM PDT 24 Jul 05 05:27:15 PM PDT 24 837603804 ps
T364 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4137286407 Jul 05 05:25:40 PM PDT 24 Jul 05 05:25:43 PM PDT 24 2628206551 ps
T365 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1811776862 Jul 05 05:26:21 PM PDT 24 Jul 05 05:26:25 PM PDT 24 225456411 ps
T366 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.4144065572 Jul 05 05:26:21 PM PDT 24 Jul 05 05:27:41 PM PDT 24 55256555067 ps
T367 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.981056678 Jul 05 05:26:36 PM PDT 24 Jul 05 05:26:42 PM PDT 24 339616488 ps
T368 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.614741613 Jul 05 05:26:18 PM PDT 24 Jul 05 05:26:24 PM PDT 24 248407978 ps
T369 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1762345134 Jul 05 05:26:36 PM PDT 24 Jul 05 05:26:38 PM PDT 24 157641917 ps
T185 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1128475017 Jul 05 05:26:01 PM PDT 24 Jul 05 05:26:26 PM PDT 24 24929854997 ps
T370 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.48182768 Jul 05 05:26:44 PM PDT 24 Jul 05 05:26:47 PM PDT 24 84002400 ps
T371 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1141193724 Jul 05 05:25:40 PM PDT 24 Jul 05 05:25:41 PM PDT 24 290898917 ps
T372 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3316963623 Jul 05 05:25:57 PM PDT 24 Jul 05 05:26:24 PM PDT 24 843536813 ps
T373 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2134960549 Jul 05 05:25:43 PM PDT 24 Jul 05 05:25:46 PM PDT 24 910596626 ps
T182 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3586958154 Jul 05 05:26:28 PM PDT 24 Jul 05 05:26:39 PM PDT 24 2505935606 ps
T179 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.622502377 Jul 05 05:26:18 PM PDT 24 Jul 05 05:26:41 PM PDT 24 3124566729 ps
T374 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2082477974 Jul 05 05:26:43 PM PDT 24 Jul 05 05:26:47 PM PDT 24 338915966 ps
T375 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1675101466 Jul 05 05:25:36 PM PDT 24 Jul 05 05:25:37 PM PDT 24 153339572 ps
T376 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.407548708 Jul 05 05:25:40 PM PDT 24 Jul 05 05:25:42 PM PDT 24 97868253 ps
T186 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.746065284 Jul 05 05:26:27 PM PDT 24 Jul 05 05:28:01 PM PDT 24 62338585883 ps
T377 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.648836940 Jul 05 05:26:35 PM PDT 24 Jul 05 05:26:43 PM PDT 24 1838615378 ps
T378 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1701977513 Jul 05 05:26:36 PM PDT 24 Jul 05 05:26:46 PM PDT 24 3640101286 ps
T379 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1970879127 Jul 05 05:26:44 PM PDT 24 Jul 05 05:26:56 PM PDT 24 3720906796 ps
T380 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2357984031 Jul 05 05:26:34 PM PDT 24 Jul 05 05:26:39 PM PDT 24 1787500939 ps
T381 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1133770431 Jul 05 05:25:55 PM PDT 24 Jul 05 05:27:55 PM PDT 24 87261805207 ps
T128 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.381873287 Jul 05 05:25:46 PM PDT 24 Jul 05 05:26:14 PM PDT 24 1507002595 ps
T180 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2482570261 Jul 05 05:26:36 PM PDT 24 Jul 05 05:26:58 PM PDT 24 1512567420 ps
T382 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1448793878 Jul 05 05:25:36 PM PDT 24 Jul 05 05:25:41 PM PDT 24 8230390503 ps
T383 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.518688557 Jul 05 05:26:36 PM PDT 24 Jul 05 05:26:53 PM PDT 24 9782324893 ps
T384 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2104563161 Jul 05 05:26:11 PM PDT 24 Jul 05 05:26:13 PM PDT 24 343341200 ps
T183 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2271504112 Jul 05 05:26:29 PM PDT 24 Jul 05 05:26:50 PM PDT 24 4766374478 ps
T184 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3591967147 Jul 05 05:26:15 PM PDT 24 Jul 05 05:26:30 PM PDT 24 3124696702 ps
T385 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.634074900 Jul 05 05:26:20 PM PDT 24 Jul 05 05:26:23 PM PDT 24 60334139 ps
T386 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.336379876 Jul 05 05:26:16 PM PDT 24 Jul 05 05:26:22 PM PDT 24 3276218710 ps
T387 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1290824665 Jul 05 05:25:36 PM PDT 24 Jul 05 05:25:48 PM PDT 24 9051399113 ps
T388 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2611270141 Jul 05 05:26:15 PM PDT 24 Jul 05 05:26:20 PM PDT 24 1941763725 ps
T389 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2988870246 Jul 05 05:26:29 PM PDT 24 Jul 05 05:26:33 PM PDT 24 724778822 ps
T122 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.749136050 Jul 05 05:25:47 PM PDT 24 Jul 05 05:26:21 PM PDT 24 18922290086 ps
T129 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1689521709 Jul 05 05:25:40 PM PDT 24 Jul 05 05:25:43 PM PDT 24 498329739 ps
T132 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3516199492 Jul 05 05:26:27 PM PDT 24 Jul 05 05:26:29 PM PDT 24 115317354 ps
T390 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2360551887 Jul 05 05:26:30 PM PDT 24 Jul 05 05:26:32 PM PDT 24 149864506 ps
T391 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3191799766 Jul 05 05:25:39 PM PDT 24 Jul 05 05:25:47 PM PDT 24 720950068 ps
T392 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2202360845 Jul 05 05:25:57 PM PDT 24 Jul 05 05:25:58 PM PDT 24 174360684 ps
T133 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1805349560 Jul 05 05:25:55 PM PDT 24 Jul 05 05:25:57 PM PDT 24 274717530 ps
T393 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2395756766 Jul 05 05:25:35 PM PDT 24 Jul 05 05:26:44 PM PDT 24 28999462317 ps
T394 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.793355332 Jul 05 05:26:42 PM PDT 24 Jul 05 05:26:47 PM PDT 24 100859055 ps
T395 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3495849946 Jul 05 05:26:37 PM PDT 24 Jul 05 05:26:47 PM PDT 24 4329657187 ps
T396 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4002665418 Jul 05 05:25:55 PM PDT 24 Jul 05 05:26:00 PM PDT 24 232452303 ps
T397 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4007734493 Jul 05 05:26:44 PM PDT 24 Jul 05 05:26:48 PM PDT 24 599070066 ps
T398 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1392410795 Jul 05 05:25:58 PM PDT 24 Jul 05 05:27:42 PM PDT 24 37406907121 ps
T123 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2569256032 Jul 05 05:26:38 PM PDT 24 Jul 05 05:26:43 PM PDT 24 309536468 ps
T399 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3946280326 Jul 05 05:25:37 PM PDT 24 Jul 05 05:25:42 PM PDT 24 1345449654 ps
T400 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2426433298 Jul 05 05:26:22 PM PDT 24 Jul 05 05:26:31 PM PDT 24 5952993567 ps
T124 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3860131154 Jul 05 05:26:21 PM PDT 24 Jul 05 05:26:28 PM PDT 24 291632775 ps
T113 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3331674826 Jul 05 05:26:02 PM PDT 24 Jul 05 05:26:11 PM PDT 24 10128643803 ps
T401 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2619590107 Jul 05 05:25:40 PM PDT 24 Jul 05 05:25:42 PM PDT 24 306214775 ps
T402 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2349183282 Jul 05 05:25:57 PM PDT 24 Jul 05 05:25:58 PM PDT 24 80428580 ps
T403 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.4170965372 Jul 05 05:26:36 PM PDT 24 Jul 05 05:26:39 PM PDT 24 764667817 ps
T404 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1572066955 Jul 05 05:25:42 PM PDT 24 Jul 05 05:25:48 PM PDT 24 5786522243 ps
T405 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.211561206 Jul 05 05:25:59 PM PDT 24 Jul 05 05:26:13 PM PDT 24 8954613528 ps
T406 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1452263310 Jul 05 05:25:39 PM PDT 24 Jul 05 05:26:34 PM PDT 24 33769313939 ps
T407 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3415505237 Jul 05 05:25:56 PM PDT 24 Jul 05 05:25:58 PM PDT 24 112942412 ps
T125 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3981544177 Jul 05 05:26:39 PM PDT 24 Jul 05 05:26:43 PM PDT 24 214692761 ps
T408 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1881177435 Jul 05 05:26:29 PM PDT 24 Jul 05 05:26:37 PM PDT 24 334623129 ps
T409 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1128233269 Jul 05 05:26:29 PM PDT 24 Jul 05 05:26:31 PM PDT 24 149068603 ps
T410 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4077712046 Jul 05 05:25:39 PM PDT 24 Jul 05 05:26:33 PM PDT 24 59218138981 ps
T411 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1212512698 Jul 05 05:26:16 PM PDT 24 Jul 05 05:27:30 PM PDT 24 28040585019 ps
T181 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2887754396 Jul 05 05:26:09 PM PDT 24 Jul 05 05:26:20 PM PDT 24 2476151119 ps
T412 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.250924486 Jul 05 05:26:15 PM PDT 24 Jul 05 05:26:17 PM PDT 24 961220088 ps
T413 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.914922414 Jul 05 05:26:43 PM PDT 24 Jul 05 05:26:46 PM PDT 24 46562170 ps
T177 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3495575355 Jul 05 05:25:56 PM PDT 24 Jul 05 05:26:09 PM PDT 24 1452207436 ps
T414 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2383094996 Jul 05 05:26:13 PM PDT 24 Jul 05 05:26:37 PM PDT 24 16842671486 ps
T134 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1529990204 Jul 05 05:26:00 PM PDT 24 Jul 05 05:26:03 PM PDT 24 321439545 ps
T415 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.992351321 Jul 05 05:26:35 PM PDT 24 Jul 05 05:26:38 PM PDT 24 120375053 ps
T416 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2620422815 Jul 05 05:25:33 PM PDT 24 Jul 05 05:25:35 PM PDT 24 360513245 ps
T417 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4211882774 Jul 05 05:26:03 PM PDT 24 Jul 05 05:27:36 PM PDT 24 43824501177 ps
T418 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2477759969 Jul 05 05:26:23 PM PDT 24 Jul 05 05:26:39 PM PDT 24 5871162401 ps
T419 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.245906640 Jul 05 05:25:41 PM PDT 24 Jul 05 05:25:43 PM PDT 24 568826501 ps
T420 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3891707380 Jul 05 05:26:31 PM PDT 24 Jul 05 05:26:36 PM PDT 24 326204055 ps
T421 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3937442376 Jul 05 05:26:12 PM PDT 24 Jul 05 05:26:14 PM PDT 24 255401303 ps
T130 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4267614386 Jul 05 05:25:54 PM PDT 24 Jul 05 05:26:26 PM PDT 24 6621869985 ps
T422 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2878129260 Jul 05 05:26:28 PM PDT 24 Jul 05 05:26:34 PM PDT 24 4651437362 ps
T175 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.221232710 Jul 05 05:26:23 PM PDT 24 Jul 05 05:26:43 PM PDT 24 2991952456 ps
T423 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1495614988 Jul 05 05:25:56 PM PDT 24 Jul 05 05:25:59 PM PDT 24 210716764 ps
T424 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2433163687 Jul 05 05:26:48 PM PDT 24 Jul 05 05:26:50 PM PDT 24 316816643 ps
T135 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2631732254 Jul 05 05:26:13 PM PDT 24 Jul 05 05:26:16 PM PDT 24 237540492 ps
T425 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1585887422 Jul 05 05:25:36 PM PDT 24 Jul 05 05:25:53 PM PDT 24 6241231345 ps
T426 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3673653755 Jul 05 05:25:43 PM PDT 24 Jul 05 05:25:45 PM PDT 24 183765793 ps
T427 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2444485308 Jul 05 05:26:20 PM PDT 24 Jul 05 05:26:21 PM PDT 24 129639747 ps
T428 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3195580761 Jul 05 05:26:10 PM PDT 24 Jul 05 05:27:03 PM PDT 24 51070625771 ps
T131 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.665281011 Jul 05 05:26:02 PM PDT 24 Jul 05 05:26:05 PM PDT 24 206635046 ps
T429 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1967395676 Jul 05 05:26:05 PM PDT 24 Jul 05 05:26:09 PM PDT 24 353638186 ps
T430 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1271274084 Jul 05 05:26:14 PM PDT 24 Jul 05 05:27:07 PM PDT 24 1700179304 ps
T431 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3983587003 Jul 05 05:26:46 PM PDT 24 Jul 05 05:26:56 PM PDT 24 1087897098 ps

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1937255937
Short name T2
Test name
Test status
Simulation time 2327591013 ps
CPU time 3.68 seconds
Started Jul 05 05:27:19 PM PDT 24
Finished Jul 05 05:27:24 PM PDT 24
Peak memory 214504 kb
Host smart-688d946a-f5e6-4d54-9062-cd7ab5e9d9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937255937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1937255937
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.3637020850
Short name T9
Test name
Test status
Simulation time 2735093846 ps
CPU time 2.8 seconds
Started Jul 05 05:27:26 PM PDT 24
Finished Jul 05 05:27:31 PM PDT 24
Peak memory 213484 kb
Host smart-5d5a6df2-815d-478f-a951-fb03da365980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637020850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.3637020850
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2284542824
Short name T63
Test name
Test status
Simulation time 433846998 ps
CPU time 5.22 seconds
Started Jul 05 05:26:38 PM PDT 24
Finished Jul 05 05:26:44 PM PDT 24
Peak memory 213348 kb
Host smart-ee00f668-0fbf-4e88-9a90-284a736ae17b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284542824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2284542824
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.1143350529
Short name T7
Test name
Test status
Simulation time 7279547524 ps
CPU time 10.84 seconds
Started Jul 05 05:27:24 PM PDT 24
Finished Jul 05 05:27:35 PM PDT 24
Peak memory 214340 kb
Host smart-8e20a914-b04a-4bb0-8593-3f16965991d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143350529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1143350529
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.2886766437
Short name T57
Test name
Test status
Simulation time 60676999 ps
CPU time 0.7 seconds
Started Jul 05 05:27:26 PM PDT 24
Finished Jul 05 05:27:28 PM PDT 24
Peak memory 205064 kb
Host smart-1cf273aa-6903-4b5a-bdba-7e13a538f013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886766437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2886766437
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.115818141
Short name T60
Test name
Test status
Simulation time 974265731 ps
CPU time 11.18 seconds
Started Jul 05 05:26:22 PM PDT 24
Finished Jul 05 05:26:34 PM PDT 24
Peak memory 213384 kb
Host smart-ab230983-92f4-4ba8-95b4-47a7e18fc0db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115818141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.115818141
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1452263310
Short name T406
Test name
Test status
Simulation time 33769313939 ps
CPU time 54.17 seconds
Started Jul 05 05:25:39 PM PDT 24
Finished Jul 05 05:26:34 PM PDT 24
Peak memory 221256 kb
Host smart-b48a5cc4-b9de-4a2a-a109-bf373cd300df
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452263310 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.1452263310
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.4236861760
Short name T27
Test name
Test status
Simulation time 15170850398 ps
CPU time 9.89 seconds
Started Jul 05 05:27:11 PM PDT 24
Finished Jul 05 05:27:22 PM PDT 24
Peak memory 213604 kb
Host smart-0708d6bd-d4ca-4cd8-bceb-da4e1f5c57d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236861760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.4236861760
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.3249741686
Short name T8
Test name
Test status
Simulation time 12722457569 ps
CPU time 10.06 seconds
Started Jul 05 05:27:21 PM PDT 24
Finished Jul 05 05:27:32 PM PDT 24
Peak memory 213492 kb
Host smart-1ae3ebfe-e3ba-4cb8-893a-108883226730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249741686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.3249741686
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.933500695
Short name T116
Test name
Test status
Simulation time 3961003864 ps
CPU time 78.66 seconds
Started Jul 05 05:25:36 PM PDT 24
Finished Jul 05 05:26:55 PM PDT 24
Peak memory 213484 kb
Host smart-b93a5602-f55d-4532-8a86-2546d6b99c52
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933500695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.933500695
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.1568746138
Short name T47
Test name
Test status
Simulation time 72493991 ps
CPU time 0.99 seconds
Started Jul 05 05:26:54 PM PDT 24
Finished Jul 05 05:26:56 PM PDT 24
Peak memory 215660 kb
Host smart-9c507937-712c-4fad-b5f3-d155a113b31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568746138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1568746138
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3924397703
Short name T55
Test name
Test status
Simulation time 2571522691 ps
CPU time 1.58 seconds
Started Jul 05 05:26:58 PM PDT 24
Finished Jul 05 05:27:01 PM PDT 24
Peak memory 213548 kb
Host smart-3b3a9c49-5d97-45cf-8a34-0bd4fe6869a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924397703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3924397703
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2888194153
Short name T19
Test name
Test status
Simulation time 782411707 ps
CPU time 1.9 seconds
Started Jul 05 05:26:49 PM PDT 24
Finished Jul 05 05:26:52 PM PDT 24
Peak memory 205052 kb
Host smart-cca5236b-9141-4aa1-837d-9f59c827d73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888194153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2888194153
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.581239173
Short name T42
Test name
Test status
Simulation time 318223577 ps
CPU time 1.45 seconds
Started Jul 05 05:26:52 PM PDT 24
Finished Jul 05 05:26:55 PM PDT 24
Peak memory 205008 kb
Host smart-f5971e0d-ab89-4b90-a08b-eb813cf30dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581239173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.581239173
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.2038246934
Short name T16
Test name
Test status
Simulation time 1923272018 ps
CPU time 2.44 seconds
Started Jul 05 05:27:04 PM PDT 24
Finished Jul 05 05:27:08 PM PDT 24
Peak memory 205236 kb
Host smart-c631f07c-92e4-4317-9b60-c123e1e64c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038246934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2038246934
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2774877872
Short name T143
Test name
Test status
Simulation time 4517345672 ps
CPU time 13.98 seconds
Started Jul 05 05:27:06 PM PDT 24
Finished Jul 05 05:27:21 PM PDT 24
Peak memory 213584 kb
Host smart-c074a331-924e-4ff9-96ae-96f70ce31ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774877872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2774877872
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1076815242
Short name T49
Test name
Test status
Simulation time 3050730487 ps
CPU time 2.85 seconds
Started Jul 05 05:26:57 PM PDT 24
Finished Jul 05 05:27:01 PM PDT 24
Peak memory 229356 kb
Host smart-df913111-b226-4c62-b4d2-8c415315c671
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076815242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1076815242
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.327769128
Short name T20
Test name
Test status
Simulation time 882860197 ps
CPU time 1.54 seconds
Started Jul 05 05:26:51 PM PDT 24
Finished Jul 05 05:26:53 PM PDT 24
Peak memory 205056 kb
Host smart-047347b2-2dfc-40df-8758-04df3160e660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327769128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.327769128
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3077655161
Short name T236
Test name
Test status
Simulation time 13700190121 ps
CPU time 14.31 seconds
Started Jul 05 05:26:56 PM PDT 24
Finished Jul 05 05:27:11 PM PDT 24
Peak memory 213616 kb
Host smart-e6f48b0a-2063-41f3-9a82-60c3c317cc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077655161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3077655161
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1803484299
Short name T100
Test name
Test status
Simulation time 1925263145 ps
CPU time 7.5 seconds
Started Jul 05 05:26:18 PM PDT 24
Finished Jul 05 05:26:26 PM PDT 24
Peak memory 205168 kb
Host smart-237b62ae-1519-4345-b206-33adf77f1fab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803484299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1803484299
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3482871799
Short name T35
Test name
Test status
Simulation time 142152016 ps
CPU time 1 seconds
Started Jul 05 05:26:50 PM PDT 24
Finished Jul 05 05:26:52 PM PDT 24
Peak memory 213288 kb
Host smart-f6a0d0a3-0d41-47f6-834d-bc897ec64e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482871799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3482871799
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3676551627
Short name T23
Test name
Test status
Simulation time 9935509658 ps
CPU time 7.08 seconds
Started Jul 05 05:27:19 PM PDT 24
Finished Jul 05 05:27:27 PM PDT 24
Peak memory 205360 kb
Host smart-1be48721-5b0b-4308-90c1-8f7a8db2f4cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676551627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3676551627
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.1298954928
Short name T13
Test name
Test status
Simulation time 10257527580 ps
CPU time 8.86 seconds
Started Jul 05 05:27:12 PM PDT 24
Finished Jul 05 05:27:22 PM PDT 24
Peak memory 213512 kb
Host smart-21342fcc-bd63-4941-a289-a6292120fbe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298954928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1298954928
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.1541246613
Short name T15
Test name
Test status
Simulation time 4668384344 ps
CPU time 11.78 seconds
Started Jul 05 05:27:26 PM PDT 24
Finished Jul 05 05:27:39 PM PDT 24
Peak memory 213556 kb
Host smart-b68c0ae2-ed6c-45bb-a4d0-11b9ca45d0d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541246613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1541246613
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3240488195
Short name T108
Test name
Test status
Simulation time 5665389953 ps
CPU time 9.91 seconds
Started Jul 05 05:25:36 PM PDT 24
Finished Jul 05 05:25:46 PM PDT 24
Peak memory 213420 kb
Host smart-0a2ffab6-0249-47b9-ac1c-730a59fb6f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240488195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3240488195
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2329531999
Short name T119
Test name
Test status
Simulation time 1111905165 ps
CPU time 2.73 seconds
Started Jul 05 05:26:28 PM PDT 24
Finished Jul 05 05:26:31 PM PDT 24
Peak memory 213384 kb
Host smart-708557fc-dc4b-4101-9f8a-c4be37ba5a5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329531999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2329531999
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.1370245926
Short name T17
Test name
Test status
Simulation time 8434605011 ps
CPU time 9.28 seconds
Started Jul 05 05:26:58 PM PDT 24
Finished Jul 05 05:27:09 PM PDT 24
Peak memory 205320 kb
Host smart-6994ea15-5ccb-48df-a684-c49bf501ce03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370245926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1370245926
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2709635201
Short name T94
Test name
Test status
Simulation time 1656119629 ps
CPU time 18.93 seconds
Started Jul 05 05:26:36 PM PDT 24
Finished Jul 05 05:26:56 PM PDT 24
Peak memory 213356 kb
Host smart-9bb8cecd-1a91-403d-a5fd-46b950554319
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709635201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
709635201
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.157819617
Short name T169
Test name
Test status
Simulation time 2122832048 ps
CPU time 2.04 seconds
Started Jul 05 05:27:12 PM PDT 24
Finished Jul 05 05:27:15 PM PDT 24
Peak memory 213592 kb
Host smart-4c1c2e45-485c-4f45-8d36-35f3bcd2f1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157819617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.157819617
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.266646682
Short name T311
Test name
Test status
Simulation time 377794383 ps
CPU time 1.65 seconds
Started Jul 05 05:25:39 PM PDT 24
Finished Jul 05 05:25:41 PM PDT 24
Peak memory 204780 kb
Host smart-b58eaacb-4da8-47f9-9fd7-44435c4844fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266646682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.266646682
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1812499602
Short name T41
Test name
Test status
Simulation time 255978565 ps
CPU time 1.41 seconds
Started Jul 05 05:26:52 PM PDT 24
Finished Jul 05 05:26:55 PM PDT 24
Peak memory 204984 kb
Host smart-e63643d2-9d43-4a31-a474-8d2b1e1c20e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812499602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1812499602
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2458965643
Short name T56
Test name
Test status
Simulation time 1737571021 ps
CPU time 3.07 seconds
Started Jul 05 05:27:12 PM PDT 24
Finished Jul 05 05:27:16 PM PDT 24
Peak memory 213616 kb
Host smart-fb5c6d9d-4022-45df-a573-b8a3833c92ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458965643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2458965643
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2758907214
Short name T1
Test name
Test status
Simulation time 5545410204 ps
CPU time 8.52 seconds
Started Jul 05 05:27:14 PM PDT 24
Finished Jul 05 05:27:23 PM PDT 24
Peak memory 213628 kb
Host smart-9dadabd8-6246-4755-be8b-59529864a3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758907214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2758907214
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.2300104539
Short name T4
Test name
Test status
Simulation time 8819803202 ps
CPU time 23.3 seconds
Started Jul 05 05:27:19 PM PDT 24
Finished Jul 05 05:27:44 PM PDT 24
Peak memory 213492 kb
Host smart-979690f7-ad91-41a4-8350-2cfc9eb55ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300104539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2300104539
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1212512698
Short name T411
Test name
Test status
Simulation time 28040585019 ps
CPU time 73.37 seconds
Started Jul 05 05:26:16 PM PDT 24
Finished Jul 05 05:27:30 PM PDT 24
Peak memory 220200 kb
Host smart-31b24982-7908-40bb-b45d-a6e86d52893b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212512698 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1212512698
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.622502377
Short name T179
Test name
Test status
Simulation time 3124566729 ps
CPU time 22.37 seconds
Started Jul 05 05:26:18 PM PDT 24
Finished Jul 05 05:26:41 PM PDT 24
Peak memory 213376 kb
Host smart-d6a7262a-e545-4ea3-bbd3-493026a10d82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622502377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.622502377
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3871925557
Short name T29
Test name
Test status
Simulation time 18020563515 ps
CPU time 17.66 seconds
Started Jul 05 05:27:06 PM PDT 24
Finished Jul 05 05:27:25 PM PDT 24
Peak memory 213628 kb
Host smart-51da12a0-b9d4-4602-9ffb-2414d64cc3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871925557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3871925557
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3728706578
Short name T154
Test name
Test status
Simulation time 3298796552 ps
CPU time 5.41 seconds
Started Jul 05 05:27:02 PM PDT 24
Finished Jul 05 05:27:08 PM PDT 24
Peak memory 205388 kb
Host smart-9eb909bd-c9b6-4a43-a804-575c8f4be321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728706578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3728706578
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.3793793465
Short name T39
Test name
Test status
Simulation time 7132853154 ps
CPU time 7.64 seconds
Started Jul 05 05:27:04 PM PDT 24
Finished Jul 05 05:27:13 PM PDT 24
Peak memory 213532 kb
Host smart-06a8840d-f88d-4d0f-8e95-4742215b7dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793793465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3793793465
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.911546935
Short name T112
Test name
Test status
Simulation time 4014848855 ps
CPU time 6.7 seconds
Started Jul 05 05:25:40 PM PDT 24
Finished Jul 05 05:25:47 PM PDT 24
Peak memory 205216 kb
Host smart-5c243f2c-f70a-48eb-a4f1-90935706a747
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911546935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.911546935
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1971073174
Short name T25
Test name
Test status
Simulation time 4487649154 ps
CPU time 12.68 seconds
Started Jul 05 05:26:44 PM PDT 24
Finished Jul 05 05:26:59 PM PDT 24
Peak memory 213528 kb
Host smart-e72cc810-967c-4d3a-b26c-44e4b1adb507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971073174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1971073174
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2298768233
Short name T33
Test name
Test status
Simulation time 238738964 ps
CPU time 1.34 seconds
Started Jul 05 05:26:46 PM PDT 24
Finished Jul 05 05:26:48 PM PDT 24
Peak memory 205080 kb
Host smart-0515118c-4278-4d10-9c41-c06f6533a0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298768233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2298768233
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.221232710
Short name T175
Test name
Test status
Simulation time 2991952456 ps
CPU time 20.28 seconds
Started Jul 05 05:26:23 PM PDT 24
Finished Jul 05 05:26:43 PM PDT 24
Peak memory 221600 kb
Host smart-7051e3b6-358c-4db2-98ec-717badfa7676
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221232710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.221232710
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2533035571
Short name T91
Test name
Test status
Simulation time 3098146337 ps
CPU time 15.02 seconds
Started Jul 05 05:26:01 PM PDT 24
Finished Jul 05 05:26:16 PM PDT 24
Peak memory 213496 kb
Host smart-e0c7d206-478e-4fef-bc82-1eb8f979c6ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533035571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2533035571
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1032526014
Short name T149
Test name
Test status
Simulation time 431404071 ps
CPU time 1 seconds
Started Jul 05 05:26:48 PM PDT 24
Finished Jul 05 05:26:50 PM PDT 24
Peak memory 205076 kb
Host smart-6b88da0b-3613-4922-b475-0ad991a5d8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032526014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1032526014
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.254258128
Short name T160
Test name
Test status
Simulation time 11699018023 ps
CPU time 11.48 seconds
Started Jul 05 05:26:49 PM PDT 24
Finished Jul 05 05:27:02 PM PDT 24
Peak memory 205276 kb
Host smart-7cbe6e35-f72f-4e0b-a34c-d6f58b75c331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254258128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.254258128
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3581197417
Short name T52
Test name
Test status
Simulation time 8496103171 ps
CPU time 20.42 seconds
Started Jul 05 05:26:46 PM PDT 24
Finished Jul 05 05:27:08 PM PDT 24
Peak memory 205256 kb
Host smart-590c0164-8d9f-4a24-861c-8a1400ce4052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581197417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3581197417
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1791403510
Short name T144
Test name
Test status
Simulation time 1222539397 ps
CPU time 2.77 seconds
Started Jul 05 05:26:55 PM PDT 24
Finished Jul 05 05:26:59 PM PDT 24
Peak memory 205308 kb
Host smart-b2a4b3f2-ab97-4b79-9c72-d882e380db32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791403510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1791403510
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1492928054
Short name T18
Test name
Test status
Simulation time 5771711749 ps
CPU time 5.8 seconds
Started Jul 05 05:26:53 PM PDT 24
Finished Jul 05 05:27:00 PM PDT 24
Peak memory 205280 kb
Host smart-e9b81026-b4cd-4aa0-a276-daa16ce01b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492928054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1492928054
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.4183925214
Short name T148
Test name
Test status
Simulation time 215206307 ps
CPU time 1.31 seconds
Started Jul 05 05:26:49 PM PDT 24
Finished Jul 05 05:26:50 PM PDT 24
Peak memory 205044 kb
Host smart-584350d0-0403-4b27-8613-2bb0036fefb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183925214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.4183925214
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3246410901
Short name T155
Test name
Test status
Simulation time 3561182185 ps
CPU time 3.25 seconds
Started Jul 05 05:27:04 PM PDT 24
Finished Jul 05 05:27:09 PM PDT 24
Peak memory 213592 kb
Host smart-a5e96fd7-efad-4011-95ef-8fa35fc0e0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246410901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3246410901
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.4035117515
Short name T166
Test name
Test status
Simulation time 5013792212 ps
CPU time 14.23 seconds
Started Jul 05 05:27:10 PM PDT 24
Finished Jul 05 05:27:25 PM PDT 24
Peak memory 214184 kb
Host smart-e454cde2-cd08-4be6-bab5-7befc12923eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035117515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.4035117515
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.324089015
Short name T153
Test name
Test status
Simulation time 3450373246 ps
CPU time 9.97 seconds
Started Jul 05 05:27:14 PM PDT 24
Finished Jul 05 05:27:25 PM PDT 24
Peak memory 205592 kb
Host smart-67cf4198-3f3c-41b9-a28f-5c451a0f62c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324089015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.324089015
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.328119950
Short name T146
Test name
Test status
Simulation time 4994207231 ps
CPU time 7.51 seconds
Started Jul 05 05:26:57 PM PDT 24
Finished Jul 05 05:27:06 PM PDT 24
Peak memory 205316 kb
Host smart-6281011b-cf27-42d6-8ec5-b16594ce63a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328119950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.328119950
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2423852920
Short name T157
Test name
Test status
Simulation time 1364414259 ps
CPU time 4.37 seconds
Started Jul 05 05:26:57 PM PDT 24
Finished Jul 05 05:27:03 PM PDT 24
Peak memory 205404 kb
Host smart-e410c484-e048-4cea-9fb0-d0d403830935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423852920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2423852920
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.3486403573
Short name T150
Test name
Test status
Simulation time 5119870051 ps
CPU time 14 seconds
Started Jul 05 05:26:57 PM PDT 24
Finished Jul 05 05:27:12 PM PDT 24
Peak memory 213600 kb
Host smart-98939052-d4ae-4a28-b894-69cfff99d672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486403573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3486403573
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3287836491
Short name T156
Test name
Test status
Simulation time 4642009805 ps
CPU time 12.08 seconds
Started Jul 05 05:27:09 PM PDT 24
Finished Jul 05 05:27:22 PM PDT 24
Peak memory 205456 kb
Host smart-4307ea27-6767-45d3-8638-761e3bf607e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287836491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3287836491
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4267614386
Short name T130
Test name
Test status
Simulation time 6621869985 ps
CPU time 30.97 seconds
Started Jul 05 05:25:54 PM PDT 24
Finished Jul 05 05:26:26 PM PDT 24
Peak memory 205112 kb
Host smart-ea965e46-b09a-4979-be32-367cf8c8db42
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267614386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.4267614386
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.665281011
Short name T131
Test name
Test status
Simulation time 206635046 ps
CPU time 2.33 seconds
Started Jul 05 05:26:02 PM PDT 24
Finished Jul 05 05:26:05 PM PDT 24
Peak memory 213296 kb
Host smart-f0f6c352-8415-40eb-b681-5b03f3454e7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665281011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.665281011
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4244532194
Short name T330
Test name
Test status
Simulation time 2579398878 ps
CPU time 34.29 seconds
Started Jul 05 05:25:43 PM PDT 24
Finished Jul 05 05:26:18 PM PDT 24
Peak memory 205296 kb
Host smart-f8e0ddc9-7946-4d60-9981-e7b5465610e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244532194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.4244532194
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1689521709
Short name T129
Test name
Test status
Simulation time 498329739 ps
CPU time 2.5 seconds
Started Jul 05 05:25:40 PM PDT 24
Finished Jul 05 05:25:43 PM PDT 24
Peak memory 213416 kb
Host smart-b8758fab-adf8-4cbc-96a9-2ea4b17c98f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689521709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1689521709
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1572066955
Short name T404
Test name
Test status
Simulation time 5786522243 ps
CPU time 6.34 seconds
Started Jul 05 05:25:42 PM PDT 24
Finished Jul 05 05:25:48 PM PDT 24
Peak memory 220148 kb
Host smart-7052b1f3-d75e-4765-91ca-5cc8deb19b91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572066955 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1572066955
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.376617426
Short name T350
Test name
Test status
Simulation time 185326244 ps
CPU time 1.54 seconds
Started Jul 05 05:25:40 PM PDT 24
Finished Jul 05 05:25:42 PM PDT 24
Peak memory 213364 kb
Host smart-37ba871e-7f36-4f20-acb7-e01d10c287f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376617426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.376617426
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1161248517
Short name T351
Test name
Test status
Simulation time 46992158821 ps
CPU time 77.33 seconds
Started Jul 05 05:25:41 PM PDT 24
Finished Jul 05 05:26:59 PM PDT 24
Peak memory 205140 kb
Host smart-0f24fa95-a4ec-4899-833f-6a263dd95374
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161248517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1161248517
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1290824665
Short name T387
Test name
Test status
Simulation time 9051399113 ps
CPU time 11.51 seconds
Started Jul 05 05:25:36 PM PDT 24
Finished Jul 05 05:25:48 PM PDT 24
Peak memory 205052 kb
Host smart-929db1ca-67f1-4b3d-9c29-187459563601
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290824665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.1290824665
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1585887422
Short name T425
Test name
Test status
Simulation time 6241231345 ps
CPU time 16.4 seconds
Started Jul 05 05:25:36 PM PDT 24
Finished Jul 05 05:25:53 PM PDT 24
Peak memory 205100 kb
Host smart-7a49c242-1f90-4428-9531-1a99786b7410
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585887422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1585887422
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1448793878
Short name T382
Test name
Test status
Simulation time 8230390503 ps
CPU time 5.26 seconds
Started Jul 05 05:25:36 PM PDT 24
Finished Jul 05 05:25:41 PM PDT 24
Peak memory 205032 kb
Host smart-219964f4-e913-485f-9f7c-f3a697c32d82
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448793878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
448793878
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.245906640
Short name T419
Test name
Test status
Simulation time 568826501 ps
CPU time 1.47 seconds
Started Jul 05 05:25:41 PM PDT 24
Finished Jul 05 05:25:43 PM PDT 24
Peak memory 204832 kb
Host smart-89531a4b-9e03-41c5-890f-ed0776893c79
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245906640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.245906640
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2395756766
Short name T393
Test name
Test status
Simulation time 28999462317 ps
CPU time 69 seconds
Started Jul 05 05:25:35 PM PDT 24
Finished Jul 05 05:26:44 PM PDT 24
Peak memory 205040 kb
Host smart-a1ecd548-f606-45c1-9522-533558f23ec4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395756766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2395756766
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2620422815
Short name T416
Test name
Test status
Simulation time 360513245 ps
CPU time 0.94 seconds
Started Jul 05 05:25:33 PM PDT 24
Finished Jul 05 05:25:35 PM PDT 24
Peak memory 204860 kb
Host smart-e6c5818d-4730-4452-80e4-99ac0c9466c0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620422815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2620422815
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1675101466
Short name T375
Test name
Test status
Simulation time 153339572 ps
CPU time 0.79 seconds
Started Jul 05 05:25:36 PM PDT 24
Finished Jul 05 05:25:37 PM PDT 24
Peak memory 204796 kb
Host smart-c62cc3f0-7e14-4cf6-8bcc-6448805e3f9f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675101466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
675101466
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3606247833
Short name T358
Test name
Test status
Simulation time 49219085 ps
CPU time 0.79 seconds
Started Jul 05 05:25:41 PM PDT 24
Finished Jul 05 05:25:42 PM PDT 24
Peak memory 204728 kb
Host smart-dadcb38a-28b2-4371-9d66-a1f4322be517
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606247833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3606247833
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.407548708
Short name T376
Test name
Test status
Simulation time 97868253 ps
CPU time 0.78 seconds
Started Jul 05 05:25:40 PM PDT 24
Finished Jul 05 05:25:42 PM PDT 24
Peak memory 204852 kb
Host smart-61b76be2-cc64-452e-8549-7dcff25e9559
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407548708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.407548708
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3191799766
Short name T391
Test name
Test status
Simulation time 720950068 ps
CPU time 7.86 seconds
Started Jul 05 05:25:39 PM PDT 24
Finished Jul 05 05:25:47 PM PDT 24
Peak memory 205128 kb
Host smart-62c47fc3-4f04-46df-bec5-4b7950811f18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191799766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3191799766
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.800197655
Short name T53
Test name
Test status
Simulation time 39729488670 ps
CPU time 44.47 seconds
Started Jul 05 05:25:36 PM PDT 24
Finished Jul 05 05:26:20 PM PDT 24
Peak memory 221648 kb
Host smart-a4a1b8c0-581f-48f4-adf8-d666e0798fc0
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800197655 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.800197655
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1870773108
Short name T95
Test name
Test status
Simulation time 314957736 ps
CPU time 5.14 seconds
Started Jul 05 05:25:38 PM PDT 24
Finished Jul 05 05:25:43 PM PDT 24
Peak memory 213312 kb
Host smart-6444ce0f-f2d8-4378-a4f7-92b8008d616e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870773108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1870773108
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3861180477
Short name T362
Test name
Test status
Simulation time 2364077545 ps
CPU time 33.02 seconds
Started Jul 05 05:25:43 PM PDT 24
Finished Jul 05 05:26:16 PM PDT 24
Peak memory 205172 kb
Host smart-badb1607-99fe-46e3-b855-f05a437aae2e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861180477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3861180477
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.381873287
Short name T128
Test name
Test status
Simulation time 1507002595 ps
CPU time 27.18 seconds
Started Jul 05 05:25:46 PM PDT 24
Finished Jul 05 05:26:14 PM PDT 24
Peak memory 213336 kb
Host smart-4dd4d640-7c78-4fba-8b28-e9eb1b52d23a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381873287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.381873287
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2619590107
Short name T401
Test name
Test status
Simulation time 306214775 ps
CPU time 1.65 seconds
Started Jul 05 05:25:40 PM PDT 24
Finished Jul 05 05:25:42 PM PDT 24
Peak memory 213408 kb
Host smart-19114cc5-4074-4b2e-9a9b-2c6524690b97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619590107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2619590107
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2287001622
Short name T92
Test name
Test status
Simulation time 226139694 ps
CPU time 2.78 seconds
Started Jul 05 05:25:47 PM PDT 24
Finished Jul 05 05:25:51 PM PDT 24
Peak memory 213412 kb
Host smart-6ebfb8f8-19dd-4901-9207-9739dd6bf1e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287001622 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2287001622
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1176537807
Short name T103
Test name
Test status
Simulation time 103480411 ps
CPU time 1.63 seconds
Started Jul 05 05:25:49 PM PDT 24
Finished Jul 05 05:25:51 PM PDT 24
Peak memory 213300 kb
Host smart-b6128bc4-db2a-4068-8b2d-74a20e5c29c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176537807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1176537807
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1976433288
Short name T340
Test name
Test status
Simulation time 221577578095 ps
CPU time 198.11 seconds
Started Jul 05 05:25:45 PM PDT 24
Finished Jul 05 05:29:03 PM PDT 24
Peak memory 210876 kb
Host smart-66d036d3-3309-4bfa-a901-a99e0bc17eea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976433288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1976433288
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4077712046
Short name T410
Test name
Test status
Simulation time 59218138981 ps
CPU time 53.87 seconds
Started Jul 05 05:25:39 PM PDT 24
Finished Jul 05 05:26:33 PM PDT 24
Peak memory 204972 kb
Host smart-d1dc2894-e80e-4b31-b211-6dbfb6fd3599
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077712046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.4077712046
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3946280326
Short name T399
Test name
Test status
Simulation time 1345449654 ps
CPU time 4.51 seconds
Started Jul 05 05:25:37 PM PDT 24
Finished Jul 05 05:25:42 PM PDT 24
Peak memory 204928 kb
Host smart-ca5c103b-dacf-4853-8de7-863d99feb432
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946280326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
946280326
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4137286407
Short name T364
Test name
Test status
Simulation time 2628206551 ps
CPU time 2.04 seconds
Started Jul 05 05:25:40 PM PDT 24
Finished Jul 05 05:25:43 PM PDT 24
Peak memory 205044 kb
Host smart-465838a3-c1ca-485f-a2da-ff81f970898e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137286407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.4137286407
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2134960549
Short name T373
Test name
Test status
Simulation time 910596626 ps
CPU time 3.16 seconds
Started Jul 05 05:25:43 PM PDT 24
Finished Jul 05 05:25:46 PM PDT 24
Peak memory 204860 kb
Host smart-78ab17fd-4f9f-4d49-9491-03c17794cb47
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134960549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2134960549
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1141193724
Short name T371
Test name
Test status
Simulation time 290898917 ps
CPU time 1.03 seconds
Started Jul 05 05:25:40 PM PDT 24
Finished Jul 05 05:25:41 PM PDT 24
Peak memory 204784 kb
Host smart-aad63b19-d65e-4e3a-bfdc-3d05f05b5efa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141193724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
141193724
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.400117088
Short name T297
Test name
Test status
Simulation time 39050503 ps
CPU time 0.71 seconds
Started Jul 05 05:25:43 PM PDT 24
Finished Jul 05 05:25:44 PM PDT 24
Peak memory 204764 kb
Host smart-4bf0f52e-6d49-4072-a536-5dc2da498d61
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400117088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part
ial_access.400117088
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3673653755
Short name T426
Test name
Test status
Simulation time 183765793 ps
CPU time 0.76 seconds
Started Jul 05 05:25:43 PM PDT 24
Finished Jul 05 05:25:45 PM PDT 24
Peak memory 204740 kb
Host smart-007cfe84-ae93-4cdf-93ec-1e6a446ba813
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673653755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3673653755
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1546513665
Short name T114
Test name
Test status
Simulation time 715224437 ps
CPU time 6.92 seconds
Started Jul 05 05:25:47 PM PDT 24
Finished Jul 05 05:25:54 PM PDT 24
Peak memory 205244 kb
Host smart-17c00bf1-ce0b-4812-a638-611db679cf29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546513665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1546513665
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.307845088
Short name T321
Test name
Test status
Simulation time 268762743 ps
CPU time 2.94 seconds
Started Jul 05 05:25:44 PM PDT 24
Finished Jul 05 05:25:47 PM PDT 24
Peak memory 213344 kb
Host smart-5de9bdc3-7373-4813-b2c6-81a58f45bd8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307845088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.307845088
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2435839743
Short name T176
Test name
Test status
Simulation time 1164419524 ps
CPU time 11.19 seconds
Started Jul 05 05:25:40 PM PDT 24
Finished Jul 05 05:25:52 PM PDT 24
Peak memory 213424 kb
Host smart-76533e0d-3f44-4996-9ae4-8779a5226a35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435839743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2435839743
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2498356588
Short name T347
Test name
Test status
Simulation time 2074893565 ps
CPU time 6.44 seconds
Started Jul 05 05:26:20 PM PDT 24
Finished Jul 05 05:26:27 PM PDT 24
Peak memory 221484 kb
Host smart-792515d0-2104-451b-a4b1-d3e2dfef36f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498356588 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2498356588
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3516199492
Short name T132
Test name
Test status
Simulation time 115317354 ps
CPU time 1.49 seconds
Started Jul 05 05:26:27 PM PDT 24
Finished Jul 05 05:26:29 PM PDT 24
Peak memory 213400 kb
Host smart-78c6da5d-c624-4949-b4c2-62bbba66c4f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516199492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3516199492
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2426433298
Short name T400
Test name
Test status
Simulation time 5952993567 ps
CPU time 9.15 seconds
Started Jul 05 05:26:22 PM PDT 24
Finished Jul 05 05:26:31 PM PDT 24
Peak memory 205284 kb
Host smart-1d09ad65-79de-4c47-8bce-3d160fd80dcc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426433298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.2426433298
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2477759969
Short name T418
Test name
Test status
Simulation time 5871162401 ps
CPU time 14.87 seconds
Started Jul 05 05:26:23 PM PDT 24
Finished Jul 05 05:26:39 PM PDT 24
Peak memory 205024 kb
Host smart-cd782284-1301-48d0-9b5d-0b0dbca45fcf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477759969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2477759969
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2444485308
Short name T427
Test name
Test status
Simulation time 129639747 ps
CPU time 0.99 seconds
Started Jul 05 05:26:20 PM PDT 24
Finished Jul 05 05:26:21 PM PDT 24
Peak memory 204792 kb
Host smart-f30721ca-6009-4a94-9648-5a66771d0c23
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444485308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2444485308
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3860131154
Short name T124
Test name
Test status
Simulation time 291632775 ps
CPU time 6.13 seconds
Started Jul 05 05:26:21 PM PDT 24
Finished Jul 05 05:26:28 PM PDT 24
Peak memory 205140 kb
Host smart-e92a1a7c-d4a3-419a-930e-2c2727287ebb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860131154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3860131154
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1811776862
Short name T365
Test name
Test status
Simulation time 225456411 ps
CPU time 3.65 seconds
Started Jul 05 05:26:21 PM PDT 24
Finished Jul 05 05:26:25 PM PDT 24
Peak memory 213268 kb
Host smart-e1e9fdf5-2ee1-4d36-9328-c54c797dbb9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811776862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1811776862
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1286869783
Short name T322
Test name
Test status
Simulation time 365876176 ps
CPU time 2.98 seconds
Started Jul 05 05:26:31 PM PDT 24
Finished Jul 05 05:26:35 PM PDT 24
Peak memory 219264 kb
Host smart-954f2aae-0c28-4fb7-880b-9e0dcb3f36d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286869783 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1286869783
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2688784060
Short name T105
Test name
Test status
Simulation time 72893132 ps
CPU time 2.17 seconds
Started Jul 05 05:26:30 PM PDT 24
Finished Jul 05 05:26:33 PM PDT 24
Peak memory 213444 kb
Host smart-f7f6c857-a1a8-4902-a4f3-889a3890cf22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688784060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2688784060
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1466989985
Short name T315
Test name
Test status
Simulation time 5152133250 ps
CPU time 4.63 seconds
Started Jul 05 05:26:21 PM PDT 24
Finished Jul 05 05:26:26 PM PDT 24
Peak memory 205056 kb
Host smart-09126c86-9e7b-496f-9298-e17ee0126ecb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466989985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.1466989985
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4177738764
Short name T302
Test name
Test status
Simulation time 2912684546 ps
CPU time 3.09 seconds
Started Jul 05 05:26:23 PM PDT 24
Finished Jul 05 05:26:27 PM PDT 24
Peak memory 205004 kb
Host smart-cd878c5a-36ad-4038-9e6c-8e75b0cd58d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177738764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
4177738764
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.36119963
Short name T318
Test name
Test status
Simulation time 1219747208 ps
CPU time 1.23 seconds
Started Jul 05 05:26:27 PM PDT 24
Finished Jul 05 05:26:29 PM PDT 24
Peak memory 204784 kb
Host smart-0e50e82e-c891-4955-9719-f0498343dc66
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36119963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.36119963
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.493759704
Short name T356
Test name
Test status
Simulation time 297661332 ps
CPU time 4.18 seconds
Started Jul 05 05:26:30 PM PDT 24
Finished Jul 05 05:26:35 PM PDT 24
Peak memory 205144 kb
Host smart-221a3532-b859-4cbb-8380-6eb8e71a6af0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493759704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.493759704
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.825057843
Short name T141
Test name
Test status
Simulation time 137917841 ps
CPU time 2.55 seconds
Started Jul 05 05:26:23 PM PDT 24
Finished Jul 05 05:26:26 PM PDT 24
Peak memory 213432 kb
Host smart-09938c47-ac1e-46cf-a919-cef9d6eb3968
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825057843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.825057843
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1329672100
Short name T110
Test name
Test status
Simulation time 295201646 ps
CPU time 2.53 seconds
Started Jul 05 05:26:29 PM PDT 24
Finished Jul 05 05:26:33 PM PDT 24
Peak memory 217224 kb
Host smart-6653cf64-44f8-49c5-9be1-24639606a23a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329672100 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1329672100
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1575533986
Short name T319
Test name
Test status
Simulation time 56505641232 ps
CPU time 146.24 seconds
Started Jul 05 05:26:29 PM PDT 24
Finished Jul 05 05:28:57 PM PDT 24
Peak memory 205064 kb
Host smart-413623ed-4511-43e0-83c8-b1c1253fba1f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575533986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.1575533986
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.479291519
Short name T304
Test name
Test status
Simulation time 2479802147 ps
CPU time 2.93 seconds
Started Jul 05 05:26:28 PM PDT 24
Finished Jul 05 05:26:31 PM PDT 24
Peak memory 205028 kb
Host smart-5c42bffd-0292-4c3b-8559-bf391f19f111
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479291519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.479291519
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3390513426
Short name T316
Test name
Test status
Simulation time 465858957 ps
CPU time 0.82 seconds
Started Jul 05 05:26:30 PM PDT 24
Finished Jul 05 05:26:32 PM PDT 24
Peak memory 204716 kb
Host smart-10e8bef0-c6d9-4ae0-81eb-693095dae563
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390513426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3390513426
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1881177435
Short name T408
Test name
Test status
Simulation time 334623129 ps
CPU time 6.83 seconds
Started Jul 05 05:26:29 PM PDT 24
Finished Jul 05 05:26:37 PM PDT 24
Peak memory 205216 kb
Host smart-9e4086c4-f269-462d-b12e-3d76fb584aea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881177435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1881177435
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3891707380
Short name T420
Test name
Test status
Simulation time 326204055 ps
CPU time 4.45 seconds
Started Jul 05 05:26:31 PM PDT 24
Finished Jul 05 05:26:36 PM PDT 24
Peak memory 213356 kb
Host smart-6095735b-0a7b-4ff8-9671-58e94e629e31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891707380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3891707380
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3586958154
Short name T182
Test name
Test status
Simulation time 2505935606 ps
CPU time 10.44 seconds
Started Jul 05 05:26:28 PM PDT 24
Finished Jul 05 05:26:39 PM PDT 24
Peak memory 213456 kb
Host smart-d15924ac-68dc-42ad-98bd-0101bc955b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586958154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
586958154
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2988870246
Short name T389
Test name
Test status
Simulation time 724778822 ps
CPU time 2.37 seconds
Started Jul 05 05:26:29 PM PDT 24
Finished Jul 05 05:26:33 PM PDT 24
Peak memory 216776 kb
Host smart-be43a587-502b-4306-9481-3a5bbee6815b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988870246 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2988870246
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2360551887
Short name T390
Test name
Test status
Simulation time 149864506 ps
CPU time 1.46 seconds
Started Jul 05 05:26:30 PM PDT 24
Finished Jul 05 05:26:32 PM PDT 24
Peak memory 213312 kb
Host smart-2ff3a0d5-8a2f-42c7-8494-efa7d39c6ff0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360551887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2360551887
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.710497959
Short name T324
Test name
Test status
Simulation time 4779518828 ps
CPU time 14.78 seconds
Started Jul 05 05:26:30 PM PDT 24
Finished Jul 05 05:26:46 PM PDT 24
Peak memory 205064 kb
Host smart-3c7b2c75-9e99-405f-8d20-6718a76c2a1f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710497959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
rv_dm_jtag_dmi_csr_bit_bash.710497959
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.778274978
Short name T339
Test name
Test status
Simulation time 3620464441 ps
CPU time 2.29 seconds
Started Jul 05 05:26:33 PM PDT 24
Finished Jul 05 05:26:36 PM PDT 24
Peak memory 205052 kb
Host smart-94778f86-e164-40c1-a4a2-d01d46cb7c4c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778274978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.778274978
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1128233269
Short name T409
Test name
Test status
Simulation time 149068603 ps
CPU time 0.75 seconds
Started Jul 05 05:26:29 PM PDT 24
Finished Jul 05 05:26:31 PM PDT 24
Peak memory 204820 kb
Host smart-873f3a6a-40e6-490c-81a1-1d6a81f773df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128233269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1128233269
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3862912780
Short name T139
Test name
Test status
Simulation time 407933850 ps
CPU time 4.04 seconds
Started Jul 05 05:26:28 PM PDT 24
Finished Jul 05 05:26:34 PM PDT 24
Peak memory 205072 kb
Host smart-9a485ab5-9796-4733-8971-1b4d7d8e0138
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862912780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3862912780
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3149459398
Short name T90
Test name
Test status
Simulation time 262174746 ps
CPU time 3.87 seconds
Started Jul 05 05:26:31 PM PDT 24
Finished Jul 05 05:26:36 PM PDT 24
Peak memory 213408 kb
Host smart-44d0b558-8133-4b32-8716-996fc6b51761
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149459398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3149459398
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2271504112
Short name T183
Test name
Test status
Simulation time 4766374478 ps
CPU time 19.2 seconds
Started Jul 05 05:26:29 PM PDT 24
Finished Jul 05 05:26:50 PM PDT 24
Peak memory 213420 kb
Host smart-63ec7f80-42d7-4429-943c-2f5357ef3768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271504112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
271504112
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.992351321
Short name T415
Test name
Test status
Simulation time 120375053 ps
CPU time 2.4 seconds
Started Jul 05 05:26:35 PM PDT 24
Finished Jul 05 05:26:38 PM PDT 24
Peak memory 218648 kb
Host smart-0cd42bc7-4904-4d10-b5fa-77caf2af8ef3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992351321 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.992351321
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4186198803
Short name T127
Test name
Test status
Simulation time 1362421614 ps
CPU time 2.5 seconds
Started Jul 05 05:26:42 PM PDT 24
Finished Jul 05 05:26:45 PM PDT 24
Peak memory 213300 kb
Host smart-bb3b7440-934b-4498-90b9-c597b9c0016b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186198803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.4186198803
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2350270699
Short name T337
Test name
Test status
Simulation time 13157252287 ps
CPU time 7.68 seconds
Started Jul 05 05:26:35 PM PDT 24
Finished Jul 05 05:26:44 PM PDT 24
Peak memory 205036 kb
Host smart-537f6a9c-92b9-4013-85d4-796bee461b2f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350270699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.2350270699
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4248875294
Short name T312
Test name
Test status
Simulation time 4378286194 ps
CPU time 4.13 seconds
Started Jul 05 05:26:29 PM PDT 24
Finished Jul 05 05:26:34 PM PDT 24
Peak memory 205028 kb
Host smart-00d53f65-ac37-4a34-a2ec-3900d9b214df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248875294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
4248875294
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3453761160
Short name T334
Test name
Test status
Simulation time 133646808 ps
CPU time 0.79 seconds
Started Jul 05 05:26:28 PM PDT 24
Finished Jul 05 05:26:31 PM PDT 24
Peak memory 204788 kb
Host smart-450eb3ea-cc32-4426-aac5-d950d5d70ad6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453761160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
3453761160
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3981544177
Short name T125
Test name
Test status
Simulation time 214692761 ps
CPU time 3.55 seconds
Started Jul 05 05:26:39 PM PDT 24
Finished Jul 05 05:26:43 PM PDT 24
Peak memory 205172 kb
Host smart-1c5e2d84-acf6-4d4c-9910-b9e919e83931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981544177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3981544177
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.799349246
Short name T354
Test name
Test status
Simulation time 244529212 ps
CPU time 5.12 seconds
Started Jul 05 05:26:34 PM PDT 24
Finished Jul 05 05:26:40 PM PDT 24
Peak memory 213284 kb
Host smart-787eb6d7-4701-4f04-8788-42b7a95dc45f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799349246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.799349246
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1730523274
Short name T174
Test name
Test status
Simulation time 1916219473 ps
CPU time 10.07 seconds
Started Jul 05 05:26:36 PM PDT 24
Finished Jul 05 05:26:47 PM PDT 24
Peak memory 213388 kb
Host smart-6f5a9391-9337-42d0-bede-355e08f64273
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730523274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
730523274
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3152593599
Short name T61
Test name
Test status
Simulation time 282453364 ps
CPU time 2.62 seconds
Started Jul 05 05:26:38 PM PDT 24
Finished Jul 05 05:26:41 PM PDT 24
Peak memory 213400 kb
Host smart-47959866-d8b5-447f-9def-acb25cbd9d14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152593599 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3152593599
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.4170965372
Short name T403
Test name
Test status
Simulation time 764667817 ps
CPU time 2.71 seconds
Started Jul 05 05:26:36 PM PDT 24
Finished Jul 05 05:26:39 PM PDT 24
Peak memory 213380 kb
Host smart-76c8fb83-9d3d-40f4-83b3-058b25cad2cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170965372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.4170965372
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2342432463
Short name T328
Test name
Test status
Simulation time 9006641977 ps
CPU time 12.29 seconds
Started Jul 05 05:26:39 PM PDT 24
Finished Jul 05 05:26:52 PM PDT 24
Peak memory 205048 kb
Host smart-0e8b956f-7a22-42c9-8bfa-4beb83d52fec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342432463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.2342432463
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3486497099
Short name T313
Test name
Test status
Simulation time 3091693642 ps
CPU time 3.46 seconds
Started Jul 05 05:26:34 PM PDT 24
Finished Jul 05 05:26:39 PM PDT 24
Peak memory 205052 kb
Host smart-ec84b097-6b68-423f-a6b5-a3a05fdd02b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486497099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3486497099
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.547337164
Short name T87
Test name
Test status
Simulation time 175945716 ps
CPU time 0.77 seconds
Started Jul 05 05:26:37 PM PDT 24
Finished Jul 05 05:26:39 PM PDT 24
Peak memory 204820 kb
Host smart-343d0b74-29ab-46b2-ae54-1cd02a8ead10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547337164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.547337164
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.652425079
Short name T65
Test name
Test status
Simulation time 3923227511 ps
CPU time 5.06 seconds
Started Jul 05 05:26:34 PM PDT 24
Finished Jul 05 05:26:40 PM PDT 24
Peak memory 205220 kb
Host smart-4ae4fc34-35eb-4686-a118-bf7fffe872fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652425079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_
csr_outstanding.652425079
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2017384800
Short name T320
Test name
Test status
Simulation time 119616878 ps
CPU time 3.15 seconds
Started Jul 05 05:26:35 PM PDT 24
Finished Jul 05 05:26:39 PM PDT 24
Peak memory 213388 kb
Host smart-c1c1bf37-77df-4638-ac2a-207c5f00fda0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017384800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2017384800
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2482570261
Short name T180
Test name
Test status
Simulation time 1512567420 ps
CPU time 21.13 seconds
Started Jul 05 05:26:36 PM PDT 24
Finished Jul 05 05:26:58 PM PDT 24
Peak memory 213288 kb
Host smart-4e602a28-b88c-4cd8-8684-90ad3a06a641
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482570261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
482570261
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1701977513
Short name T378
Test name
Test status
Simulation time 3640101286 ps
CPU time 9.52 seconds
Started Jul 05 05:26:36 PM PDT 24
Finished Jul 05 05:26:46 PM PDT 24
Peak memory 220472 kb
Host smart-e34a5e85-7159-4957-a214-1dc2a92fa347
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701977513 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1701977513
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2503665353
Short name T66
Test name
Test status
Simulation time 131119399 ps
CPU time 2.26 seconds
Started Jul 05 05:26:32 PM PDT 24
Finished Jul 05 05:26:35 PM PDT 24
Peak memory 213300 kb
Host smart-612c66ff-a612-4387-a919-c64b7d29978e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503665353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2503665353
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1451274444
Short name T293
Test name
Test status
Simulation time 17540913299 ps
CPU time 16.21 seconds
Started Jul 05 05:26:36 PM PDT 24
Finished Jul 05 05:26:52 PM PDT 24
Peak memory 205056 kb
Host smart-8651040d-7d1b-4170-8105-9f8c1d89307c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451274444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.1451274444
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2357984031
Short name T380
Test name
Test status
Simulation time 1787500939 ps
CPU time 4.4 seconds
Started Jul 05 05:26:34 PM PDT 24
Finished Jul 05 05:26:39 PM PDT 24
Peak memory 204964 kb
Host smart-9732c930-f7a2-4b5a-b236-8898164a4543
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357984031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2357984031
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3947043639
Short name T342
Test name
Test status
Simulation time 426697257 ps
CPU time 1.18 seconds
Started Jul 05 05:26:35 PM PDT 24
Finished Jul 05 05:26:37 PM PDT 24
Peak memory 204784 kb
Host smart-a8f01ff8-22cc-45d9-85c1-acdcb3f47a66
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947043639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3947043639
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.648836940
Short name T377
Test name
Test status
Simulation time 1838615378 ps
CPU time 7.49 seconds
Started Jul 05 05:26:35 PM PDT 24
Finished Jul 05 05:26:43 PM PDT 24
Peak memory 205172 kb
Host smart-540fd8c0-4ffa-4168-8bee-e18b373c8249
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648836940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.648836940
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.447965543
Short name T348
Test name
Test status
Simulation time 388806584 ps
CPU time 5.06 seconds
Started Jul 05 05:26:37 PM PDT 24
Finished Jul 05 05:26:43 PM PDT 24
Peak memory 213340 kb
Host smart-0e7e7745-da3f-432e-9ecb-d36fa02bb615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447965543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.447965543
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3495849946
Short name T395
Test name
Test status
Simulation time 4329657187 ps
CPU time 8.78 seconds
Started Jul 05 05:26:37 PM PDT 24
Finished Jul 05 05:26:47 PM PDT 24
Peak memory 213428 kb
Host smart-1747764e-6494-4828-bd5c-ee9b25ceeb7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495849946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
495849946
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.981056678
Short name T367
Test name
Test status
Simulation time 339616488 ps
CPU time 4.49 seconds
Started Jul 05 05:26:36 PM PDT 24
Finished Jul 05 05:26:42 PM PDT 24
Peak memory 218432 kb
Host smart-0ca912e9-96be-4ce8-a8fd-0f9b6506e4d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981056678 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.981056678
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4146136246
Short name T104
Test name
Test status
Simulation time 100609726 ps
CPU time 1.48 seconds
Started Jul 05 05:26:35 PM PDT 24
Finished Jul 05 05:26:37 PM PDT 24
Peak memory 213364 kb
Host smart-518da588-ab23-44aa-8a27-6af9f9c10b21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146136246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.4146136246
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.518688557
Short name T383
Test name
Test status
Simulation time 9782324893 ps
CPU time 15.74 seconds
Started Jul 05 05:26:36 PM PDT 24
Finished Jul 05 05:26:53 PM PDT 24
Peak memory 205024 kb
Host smart-e2c4a4a4-17b4-41c4-9a48-50fd9478cbec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518688557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.518688557
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2932775338
Short name T308
Test name
Test status
Simulation time 5062094211 ps
CPU time 15.01 seconds
Started Jul 05 05:26:37 PM PDT 24
Finished Jul 05 05:26:53 PM PDT 24
Peak memory 204976 kb
Host smart-76211afa-1e5f-4766-a200-ac48b3d1e36b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932775338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2932775338
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.456211319
Short name T331
Test name
Test status
Simulation time 562984280 ps
CPU time 1.22 seconds
Started Jul 05 05:26:36 PM PDT 24
Finished Jul 05 05:26:38 PM PDT 24
Peak memory 204744 kb
Host smart-87fa26a9-5735-4ded-9566-56c71378c31d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456211319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.456211319
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2569256032
Short name T123
Test name
Test status
Simulation time 309536468 ps
CPU time 4.43 seconds
Started Jul 05 05:26:38 PM PDT 24
Finished Jul 05 05:26:43 PM PDT 24
Peak memory 205108 kb
Host smart-3ea1066f-863c-49ab-8599-05a3719f90a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569256032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2569256032
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.901793307
Short name T111
Test name
Test status
Simulation time 4462521497 ps
CPU time 10.52 seconds
Started Jul 05 05:26:47 PM PDT 24
Finished Jul 05 05:26:58 PM PDT 24
Peak memory 221540 kb
Host smart-c522edf7-f0a2-457b-80c8-30f43a8f8c5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901793307 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.901793307
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2433163687
Short name T424
Test name
Test status
Simulation time 316816643 ps
CPU time 1.78 seconds
Started Jul 05 05:26:48 PM PDT 24
Finished Jul 05 05:26:50 PM PDT 24
Peak memory 213392 kb
Host smart-9a92d300-8a32-4f49-a63c-0d9dd62d5b06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433163687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2433163687
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1064945546
Short name T353
Test name
Test status
Simulation time 8592580073 ps
CPU time 21.53 seconds
Started Jul 05 05:26:45 PM PDT 24
Finished Jul 05 05:27:08 PM PDT 24
Peak memory 204956 kb
Host smart-0d5a23a6-ff76-4665-82c1-5b39b16a65ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064945546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.1064945546
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1970879127
Short name T379
Test name
Test status
Simulation time 3720906796 ps
CPU time 10.89 seconds
Started Jul 05 05:26:44 PM PDT 24
Finished Jul 05 05:26:56 PM PDT 24
Peak memory 205048 kb
Host smart-9e13174a-3f79-4cc4-842d-b5ff80047b3b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970879127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1970879127
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1762345134
Short name T369
Test name
Test status
Simulation time 157641917 ps
CPU time 0.99 seconds
Started Jul 05 05:26:36 PM PDT 24
Finished Jul 05 05:26:38 PM PDT 24
Peak memory 204772 kb
Host smart-ccc1b430-6120-4377-96b9-7e4bf66852e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762345134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1762345134
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2921305939
Short name T121
Test name
Test status
Simulation time 837603804 ps
CPU time 4 seconds
Started Jul 05 05:27:10 PM PDT 24
Finished Jul 05 05:27:15 PM PDT 24
Peak memory 205208 kb
Host smart-a11eb340-cbb0-46e5-bfd4-7d801f5ae699
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921305939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2921305939
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2082477974
Short name T374
Test name
Test status
Simulation time 338915966 ps
CPU time 2.3 seconds
Started Jul 05 05:26:43 PM PDT 24
Finished Jul 05 05:26:47 PM PDT 24
Peak memory 213356 kb
Host smart-b44242db-dfec-4871-9915-41d656a37f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082477974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2082477974
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4004580932
Short name T62
Test name
Test status
Simulation time 8089986595 ps
CPU time 22.5 seconds
Started Jul 05 05:26:44 PM PDT 24
Finished Jul 05 05:27:07 PM PDT 24
Peak memory 213440 kb
Host smart-99c32edf-4eb1-43b1-9336-7af9f4aee768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004580932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4
004580932
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4007734493
Short name T397
Test name
Test status
Simulation time 599070066 ps
CPU time 2.36 seconds
Started Jul 05 05:26:44 PM PDT 24
Finished Jul 05 05:26:48 PM PDT 24
Peak memory 216912 kb
Host smart-cebfb0d5-fd7c-42a9-bc30-63813827757b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007734493 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.4007734493
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.914922414
Short name T413
Test name
Test status
Simulation time 46562170 ps
CPU time 1.52 seconds
Started Jul 05 05:26:43 PM PDT 24
Finished Jul 05 05:26:46 PM PDT 24
Peak memory 213252 kb
Host smart-d4f5de42-1177-4347-9da8-3ba5f6049f85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914922414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.914922414
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.923803078
Short name T341
Test name
Test status
Simulation time 20533334411 ps
CPU time 25.94 seconds
Started Jul 05 05:26:47 PM PDT 24
Finished Jul 05 05:27:13 PM PDT 24
Peak memory 205032 kb
Host smart-79280c1d-dfe2-42f2-bbdd-20974496ff1b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923803078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rv_dm_jtag_dmi_csr_bit_bash.923803078
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1547317006
Short name T290
Test name
Test status
Simulation time 2716110561 ps
CPU time 3.56 seconds
Started Jul 05 05:26:45 PM PDT 24
Finished Jul 05 05:26:50 PM PDT 24
Peak memory 205048 kb
Host smart-42ae924c-5a69-468b-b18c-2c5ccddc923a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547317006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1547317006
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.987058125
Short name T338
Test name
Test status
Simulation time 248902865 ps
CPU time 0.87 seconds
Started Jul 05 05:26:43 PM PDT 24
Finished Jul 05 05:26:45 PM PDT 24
Peak memory 204792 kb
Host smart-99f02bcf-c3fa-4b15-bd90-fe312a69e78c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987058125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.987058125
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.793355332
Short name T394
Test name
Test status
Simulation time 100859055 ps
CPU time 3.6 seconds
Started Jul 05 05:26:42 PM PDT 24
Finished Jul 05 05:26:47 PM PDT 24
Peak memory 205172 kb
Host smart-de7b1ab8-7db9-477e-ab37-4f5cfbad6110
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793355332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.793355332
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.48182768
Short name T370
Test name
Test status
Simulation time 84002400 ps
CPU time 1.9 seconds
Started Jul 05 05:26:44 PM PDT 24
Finished Jul 05 05:26:47 PM PDT 24
Peak memory 213316 kb
Host smart-fec51a8b-24c5-449d-8f2b-1d33a20b53cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48182768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.48182768
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3983587003
Short name T431
Test name
Test status
Simulation time 1087897098 ps
CPU time 9.37 seconds
Started Jul 05 05:26:46 PM PDT 24
Finished Jul 05 05:26:56 PM PDT 24
Peak memory 213356 kb
Host smart-bf9c2259-8c34-46c7-8f17-98b641a15039
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983587003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
983587003
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.749136050
Short name T122
Test name
Test status
Simulation time 18922290086 ps
CPU time 33.32 seconds
Started Jul 05 05:25:47 PM PDT 24
Finished Jul 05 05:26:21 PM PDT 24
Peak memory 205192 kb
Host smart-916c537f-08b8-49ea-8031-6caa1a8a7836
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749136050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.rv_dm_csr_aliasing.749136050
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3316963623
Short name T372
Test name
Test status
Simulation time 843536813 ps
CPU time 26.59 seconds
Started Jul 05 05:25:57 PM PDT 24
Finished Jul 05 05:26:24 PM PDT 24
Peak memory 213392 kb
Host smart-0f01449e-a00b-45d7-9969-cd418d3bbbcf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316963623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3316963623
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1805349560
Short name T133
Test name
Test status
Simulation time 274717530 ps
CPU time 2.07 seconds
Started Jul 05 05:25:55 PM PDT 24
Finished Jul 05 05:25:57 PM PDT 24
Peak memory 213292 kb
Host smart-46fdf17f-acc6-438f-aee0-903f9e81efb4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805349560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1805349560
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4002665418
Short name T396
Test name
Test status
Simulation time 232452303 ps
CPU time 4.19 seconds
Started Jul 05 05:25:55 PM PDT 24
Finished Jul 05 05:26:00 PM PDT 24
Peak memory 218416 kb
Host smart-ea6efe71-7d47-4868-870b-9dba530811a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002665418 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.4002665418
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1495614988
Short name T423
Test name
Test status
Simulation time 210716764 ps
CPU time 2.36 seconds
Started Jul 05 05:25:56 PM PDT 24
Finished Jul 05 05:25:59 PM PDT 24
Peak memory 213376 kb
Host smart-3ddb8c86-d159-4e96-9919-d647eda32f10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495614988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1495614988
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.506279307
Short name T326
Test name
Test status
Simulation time 13770835912 ps
CPU time 8.59 seconds
Started Jul 05 05:26:00 PM PDT 24
Finished Jul 05 05:26:08 PM PDT 24
Peak memory 205140 kb
Host smart-ef38ebbe-d880-4c55-894f-4467f5c26923
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506279307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.506279307
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1605789503
Short name T292
Test name
Test status
Simulation time 53129616155 ps
CPU time 85.7 seconds
Started Jul 05 05:26:01 PM PDT 24
Finished Jul 05 05:27:28 PM PDT 24
Peak memory 205064 kb
Host smart-646e1c1d-8b3f-42be-8f4d-f7e6bec7448d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605789503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1605789503
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.211561206
Short name T405
Test name
Test status
Simulation time 8954613528 ps
CPU time 13.17 seconds
Started Jul 05 05:25:59 PM PDT 24
Finished Jul 05 05:26:13 PM PDT 24
Peak memory 205036 kb
Host smart-90502bfe-28a1-44cb-926b-b92378b8891f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211561206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.211561206
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3069864118
Short name T303
Test name
Test status
Simulation time 2498203774 ps
CPU time 4.06 seconds
Started Jul 05 05:25:55 PM PDT 24
Finished Jul 05 05:25:59 PM PDT 24
Peak memory 205080 kb
Host smart-835e8b6b-830e-41c1-b940-9fb4984bb9ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069864118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
069864118
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1193110815
Short name T346
Test name
Test status
Simulation time 162841312 ps
CPU time 1.08 seconds
Started Jul 05 05:25:48 PM PDT 24
Finished Jul 05 05:25:50 PM PDT 24
Peak memory 204800 kb
Host smart-fe21d89f-ba5d-421e-a3dd-8cba4335b70c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193110815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.1193110815
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3036615190
Short name T310
Test name
Test status
Simulation time 39378473410 ps
CPU time 29.83 seconds
Started Jul 05 05:25:49 PM PDT 24
Finished Jul 05 05:26:20 PM PDT 24
Peak memory 205084 kb
Host smart-6eaba89e-4a65-40a1-b7a8-51d793f39852
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036615190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.3036615190
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2851689924
Short name T88
Test name
Test status
Simulation time 331407511 ps
CPU time 1.52 seconds
Started Jul 05 05:25:50 PM PDT 24
Finished Jul 05 05:25:52 PM PDT 24
Peak memory 204868 kb
Host smart-11e5e4a0-801f-4740-8e46-cffa02645bac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851689924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2851689924
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3298160349
Short name T349
Test name
Test status
Simulation time 685408679 ps
CPU time 1.14 seconds
Started Jul 05 05:25:50 PM PDT 24
Finished Jul 05 05:25:52 PM PDT 24
Peak memory 204780 kb
Host smart-d5e89295-2676-4976-99b7-949f60ea4b8e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298160349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
298160349
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2349183282
Short name T402
Test name
Test status
Simulation time 80428580 ps
CPU time 0.71 seconds
Started Jul 05 05:25:57 PM PDT 24
Finished Jul 05 05:25:58 PM PDT 24
Peak memory 204684 kb
Host smart-945ca973-dc9b-4f99-9028-f715e9658bc5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349183282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2349183282
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1785161221
Short name T333
Test name
Test status
Simulation time 38400018 ps
CPU time 0.75 seconds
Started Jul 05 05:25:59 PM PDT 24
Finished Jul 05 05:26:00 PM PDT 24
Peak memory 204812 kb
Host smart-ed7fcdb8-6a33-440f-a148-c63987b8968e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785161221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1785161221
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3815140217
Short name T137
Test name
Test status
Simulation time 133427093 ps
CPU time 3.46 seconds
Started Jul 05 05:25:55 PM PDT 24
Finished Jul 05 05:25:59 PM PDT 24
Peak memory 205172 kb
Host smart-2b047245-e3eb-484b-9d04-1257d67a7651
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815140217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3815140217
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.568938694
Short name T64
Test name
Test status
Simulation time 207986242 ps
CPU time 4.83 seconds
Started Jul 05 05:25:57 PM PDT 24
Finished Jul 05 05:26:03 PM PDT 24
Peak memory 213364 kb
Host smart-1be47a79-79e8-4dad-8614-62c9151dd21b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568938694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.568938694
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1350889879
Short name T325
Test name
Test status
Simulation time 1154929470 ps
CPU time 11.21 seconds
Started Jul 05 05:25:56 PM PDT 24
Finished Jul 05 05:26:07 PM PDT 24
Peak memory 213360 kb
Host smart-8cffff9f-8412-4182-8665-eb3c212336e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350889879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1350889879
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.23790485
Short name T99
Test name
Test status
Simulation time 5018237768 ps
CPU time 65.25 seconds
Started Jul 05 05:26:05 PM PDT 24
Finished Jul 05 05:27:11 PM PDT 24
Peak memory 213504 kb
Host smart-9349f774-ad8c-438e-b913-d982ff308ff4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23790485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.23790485
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1529990204
Short name T134
Test name
Test status
Simulation time 321439545 ps
CPU time 2.64 seconds
Started Jul 05 05:26:00 PM PDT 24
Finished Jul 05 05:26:03 PM PDT 24
Peak memory 213412 kb
Host smart-f3da1a9e-d8d7-478b-a9c9-1d20c5ca71f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529990204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1529990204
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1571423886
Short name T109
Test name
Test status
Simulation time 3149664163 ps
CPU time 8.85 seconds
Started Jul 05 05:26:00 PM PDT 24
Finished Jul 05 05:26:10 PM PDT 24
Peak memory 219272 kb
Host smart-9a0f00c1-2a22-4645-b647-89c5002f2aff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571423886 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1571423886
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1133770431
Short name T381
Test name
Test status
Simulation time 87261805207 ps
CPU time 119.4 seconds
Started Jul 05 05:25:55 PM PDT 24
Finished Jul 05 05:27:55 PM PDT 24
Peak memory 204952 kb
Host smart-36a6bd19-01ea-4d99-af05-381bc0029090
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133770431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1133770431
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4145217179
Short name T295
Test name
Test status
Simulation time 29083710170 ps
CPU time 47.11 seconds
Started Jul 05 05:25:53 PM PDT 24
Finished Jul 05 05:26:41 PM PDT 24
Peak memory 205000 kb
Host smart-768f0397-6a81-46a7-bdf4-2578fb50fab1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145217179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.4145217179
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.288448333
Short name T355
Test name
Test status
Simulation time 10080443580 ps
CPU time 27.23 seconds
Started Jul 05 05:25:55 PM PDT 24
Finished Jul 05 05:26:23 PM PDT 24
Peak memory 205092 kb
Host smart-010e8296-842a-4d7c-8d8f-82d5768e4666
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288448333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.288448333
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1645798328
Short name T307
Test name
Test status
Simulation time 2762242255 ps
CPU time 7.79 seconds
Started Jul 05 05:25:57 PM PDT 24
Finished Jul 05 05:26:06 PM PDT 24
Peak memory 205028 kb
Host smart-766114e7-9127-4fdb-9593-d56af7daa614
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645798328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
645798328
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3860237100
Short name T305
Test name
Test status
Simulation time 414948016 ps
CPU time 1.35 seconds
Started Jul 05 05:25:55 PM PDT 24
Finished Jul 05 05:25:57 PM PDT 24
Peak memory 204792 kb
Host smart-ee217e1b-e552-4e28-97a3-618d8633b8aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860237100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3860237100
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4098200956
Short name T301
Test name
Test status
Simulation time 19208868473 ps
CPU time 46.63 seconds
Started Jul 05 05:25:59 PM PDT 24
Finished Jul 05 05:26:46 PM PDT 24
Peak memory 205036 kb
Host smart-ea1de4c1-29de-41f6-850f-09b69fa54355
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098200956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.4098200956
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3415505237
Short name T407
Test name
Test status
Simulation time 112942412 ps
CPU time 0.83 seconds
Started Jul 05 05:25:56 PM PDT 24
Finished Jul 05 05:25:58 PM PDT 24
Peak memory 204860 kb
Host smart-70a39c36-aef5-47d0-9a05-d2b9122a77fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415505237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3415505237
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2202360845
Short name T392
Test name
Test status
Simulation time 174360684 ps
CPU time 0.8 seconds
Started Jul 05 05:25:57 PM PDT 24
Finished Jul 05 05:25:58 PM PDT 24
Peak memory 204800 kb
Host smart-64fb50ce-f4a2-4456-838c-6a2546ef15fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202360845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
202360845
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2516291484
Short name T314
Test name
Test status
Simulation time 134007357 ps
CPU time 0.93 seconds
Started Jul 05 05:25:54 PM PDT 24
Finished Jul 05 05:25:56 PM PDT 24
Peak memory 204648 kb
Host smart-2dda5d7d-6012-4a92-a180-8aa037367625
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516291484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2516291484
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2655983851
Short name T332
Test name
Test status
Simulation time 60619325 ps
CPU time 0.69 seconds
Started Jul 05 05:26:00 PM PDT 24
Finished Jul 05 05:26:01 PM PDT 24
Peak memory 204812 kb
Host smart-11279d15-f8ba-4eed-ab8f-1f4cda673693
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655983851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2655983851
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1967395676
Short name T429
Test name
Test status
Simulation time 353638186 ps
CPU time 3.62 seconds
Started Jul 05 05:26:05 PM PDT 24
Finished Jul 05 05:26:09 PM PDT 24
Peak memory 205104 kb
Host smart-e65f3780-9995-47fb-94ed-47951ef64a16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967395676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1967395676
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1206095147
Short name T352
Test name
Test status
Simulation time 26246413085 ps
CPU time 38.29 seconds
Started Jul 05 05:25:57 PM PDT 24
Finished Jul 05 05:26:35 PM PDT 24
Peak memory 221576 kb
Host smart-10b8eb00-bcea-4356-9b5a-aab4043be0be
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206095147 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.1206095147
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3762830294
Short name T343
Test name
Test status
Simulation time 313912041 ps
CPU time 4.77 seconds
Started Jul 05 05:26:01 PM PDT 24
Finished Jul 05 05:26:07 PM PDT 24
Peak memory 216048 kb
Host smart-18a33a1b-6cb5-4e57-8f93-94f3f8ffd137
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762830294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3762830294
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3495575355
Short name T177
Test name
Test status
Simulation time 1452207436 ps
CPU time 12.1 seconds
Started Jul 05 05:25:56 PM PDT 24
Finished Jul 05 05:26:09 PM PDT 24
Peak memory 213332 kb
Host smart-4fb0f730-38ae-4bb5-b0db-28ab7f157fb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495575355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3495575355
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2663644329
Short name T118
Test name
Test status
Simulation time 3855071081 ps
CPU time 73.37 seconds
Started Jul 05 05:26:03 PM PDT 24
Finished Jul 05 05:27:16 PM PDT 24
Peak memory 205236 kb
Host smart-bd937629-ab19-449a-89b1-525593869b8d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663644329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2663644329
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1271274084
Short name T430
Test name
Test status
Simulation time 1700179304 ps
CPU time 52.77 seconds
Started Jul 05 05:26:14 PM PDT 24
Finished Jul 05 05:27:07 PM PDT 24
Peak memory 213368 kb
Host smart-ba24d99c-b2b2-4da4-a81e-9d3b95af9c5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271274084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1271274084
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2521649322
Short name T120
Test name
Test status
Simulation time 338223581 ps
CPU time 1.61 seconds
Started Jul 05 05:26:10 PM PDT 24
Finished Jul 05 05:26:12 PM PDT 24
Peak memory 213360 kb
Host smart-ea643eed-2352-4845-ace4-de6ccca8e23f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521649322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2521649322
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1788638657
Short name T363
Test name
Test status
Simulation time 874549088 ps
CPU time 4.09 seconds
Started Jul 05 05:26:10 PM PDT 24
Finished Jul 05 05:26:14 PM PDT 24
Peak memory 219308 kb
Host smart-94858ce8-6c85-4e65-9c6c-16acbed9381d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788638657 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1788638657
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3794041531
Short name T115
Test name
Test status
Simulation time 57052905 ps
CPU time 2.22 seconds
Started Jul 05 05:26:08 PM PDT 24
Finished Jul 05 05:26:10 PM PDT 24
Peak memory 213400 kb
Host smart-1e64e2b7-ef13-48ee-af3b-c06e40a467f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794041531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3794041531
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1392410795
Short name T398
Test name
Test status
Simulation time 37406907121 ps
CPU time 103.9 seconds
Started Jul 05 05:25:58 PM PDT 24
Finished Jul 05 05:27:42 PM PDT 24
Peak memory 205088 kb
Host smart-36e5e0fc-6712-42c4-83f0-20cce36aa0f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392410795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1392410795
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4211882774
Short name T417
Test name
Test status
Simulation time 43824501177 ps
CPU time 91.58 seconds
Started Jul 05 05:26:03 PM PDT 24
Finished Jul 05 05:27:36 PM PDT 24
Peak memory 205044 kb
Host smart-de4d2d16-45a4-4d9f-bc03-1ef754236913
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211882774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.4211882774
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3331674826
Short name T113
Test name
Test status
Simulation time 10128643803 ps
CPU time 7.8 seconds
Started Jul 05 05:26:02 PM PDT 24
Finished Jul 05 05:26:11 PM PDT 24
Peak memory 205172 kb
Host smart-819ff42f-df17-4c5f-b373-6cc0edf56cd7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331674826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3331674826
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1909568300
Short name T359
Test name
Test status
Simulation time 2221141356 ps
CPU time 6.93 seconds
Started Jul 05 05:26:05 PM PDT 24
Finished Jul 05 05:26:12 PM PDT 24
Peak memory 205048 kb
Host smart-2d0a9480-8b7e-432d-ae77-3b10509cc26e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909568300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
909568300
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.788092228
Short name T323
Test name
Test status
Simulation time 268425959 ps
CPU time 1.34 seconds
Started Jul 05 05:26:04 PM PDT 24
Finished Jul 05 05:26:06 PM PDT 24
Peak memory 204732 kb
Host smart-a2d0a307-1cac-4932-9582-1d8daa5a1fd1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788092228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.788092228
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.4234294043
Short name T327
Test name
Test status
Simulation time 7517834778 ps
CPU time 10.44 seconds
Started Jul 05 05:26:02 PM PDT 24
Finished Jul 05 05:26:13 PM PDT 24
Peak memory 205012 kb
Host smart-c729ecc7-4bd6-4f75-a7fe-c64f1b7b8a56
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234294043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.4234294043
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3843450569
Short name T361
Test name
Test status
Simulation time 97825900 ps
CPU time 0.89 seconds
Started Jul 05 05:26:04 PM PDT 24
Finished Jul 05 05:26:05 PM PDT 24
Peak memory 204864 kb
Host smart-ab96e685-3839-4994-beb2-224759ac4b18
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843450569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3843450569
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2600203886
Short name T291
Test name
Test status
Simulation time 85186380 ps
CPU time 0.69 seconds
Started Jul 05 05:26:13 PM PDT 24
Finished Jul 05 05:26:14 PM PDT 24
Peak memory 204716 kb
Host smart-864068cc-543e-48cc-921e-a0b14c46cee9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600203886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2600203886
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.14344286
Short name T300
Test name
Test status
Simulation time 27232176 ps
CPU time 0.71 seconds
Started Jul 05 05:25:59 PM PDT 24
Finished Jul 05 05:26:00 PM PDT 24
Peak memory 204832 kb
Host smart-fd2aa095-7966-4204-afa9-6134a67fd761
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14344286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.14344286
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1728034705
Short name T102
Test name
Test status
Simulation time 498720818 ps
CPU time 3.58 seconds
Started Jul 05 05:26:08 PM PDT 24
Finished Jul 05 05:26:12 PM PDT 24
Peak memory 205256 kb
Host smart-8c85e543-ce10-4710-bd3a-bb3f578e04ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728034705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1728034705
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1128475017
Short name T185
Test name
Test status
Simulation time 24929854997 ps
CPU time 24.75 seconds
Started Jul 05 05:26:01 PM PDT 24
Finished Jul 05 05:26:26 PM PDT 24
Peak memory 221584 kb
Host smart-cf0be95d-540b-437d-9ab8-d937b02d0ef7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128475017 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1128475017
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1761524888
Short name T96
Test name
Test status
Simulation time 93749431 ps
CPU time 2.35 seconds
Started Jul 05 05:26:03 PM PDT 24
Finished Jul 05 05:26:06 PM PDT 24
Peak memory 213356 kb
Host smart-0d66fd11-92ff-4591-a00d-9071e942a722
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761524888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1761524888
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3352389532
Short name T329
Test name
Test status
Simulation time 200880674 ps
CPU time 3.14 seconds
Started Jul 05 05:26:14 PM PDT 24
Finished Jul 05 05:26:17 PM PDT 24
Peak memory 219748 kb
Host smart-3eaa1958-1675-4311-a254-015dcb5c753e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352389532 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3352389532
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1710010165
Short name T101
Test name
Test status
Simulation time 82629709 ps
CPU time 1.7 seconds
Started Jul 05 05:26:08 PM PDT 24
Finished Jul 05 05:26:10 PM PDT 24
Peak memory 213236 kb
Host smart-6d3dcd16-d5a4-4364-826d-077e95878acc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710010165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1710010165
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2383094996
Short name T414
Test name
Test status
Simulation time 16842671486 ps
CPU time 23.83 seconds
Started Jul 05 05:26:13 PM PDT 24
Finished Jul 05 05:26:37 PM PDT 24
Peak memory 205056 kb
Host smart-afe917f6-9a14-412f-b204-d3935e3951eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383094996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.2383094996
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3135183376
Short name T345
Test name
Test status
Simulation time 907132792 ps
CPU time 2 seconds
Started Jul 05 05:26:07 PM PDT 24
Finished Jul 05 05:26:10 PM PDT 24
Peak memory 204940 kb
Host smart-c3dd99b3-ea69-4135-a382-bf4dfafe4b5f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135183376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
135183376
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2104563161
Short name T384
Test name
Test status
Simulation time 343341200 ps
CPU time 1.54 seconds
Started Jul 05 05:26:11 PM PDT 24
Finished Jul 05 05:26:13 PM PDT 24
Peak memory 204792 kb
Host smart-dbf7257c-59dd-4630-9219-5dbca10aaba8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104563161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2
104563161
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.238693734
Short name T136
Test name
Test status
Simulation time 2772096809 ps
CPU time 6.8 seconds
Started Jul 05 05:26:06 PM PDT 24
Finished Jul 05 05:26:13 PM PDT 24
Peak memory 205232 kb
Host smart-1601f6ad-6cee-45ec-8c83-1050894c16f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238693734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.238693734
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3195580761
Short name T428
Test name
Test status
Simulation time 51070625771 ps
CPU time 52.67 seconds
Started Jul 05 05:26:10 PM PDT 24
Finished Jul 05 05:27:03 PM PDT 24
Peak memory 222124 kb
Host smart-dd254e60-5440-4579-970e-ddf88edf509c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195580761 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3195580761
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.618232839
Short name T335
Test name
Test status
Simulation time 222626355 ps
CPU time 4.68 seconds
Started Jul 05 05:26:10 PM PDT 24
Finished Jul 05 05:26:16 PM PDT 24
Peak memory 213328 kb
Host smart-7ba69230-afd2-482a-b5ac-2d8713c730f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618232839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.618232839
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2887754396
Short name T181
Test name
Test status
Simulation time 2476151119 ps
CPU time 10.59 seconds
Started Jul 05 05:26:09 PM PDT 24
Finished Jul 05 05:26:20 PM PDT 24
Peak memory 213444 kb
Host smart-94c23f95-e9af-4e21-b4c6-548a521bd5ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887754396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2887754396
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.336379876
Short name T386
Test name
Test status
Simulation time 3276218710 ps
CPU time 5.57 seconds
Started Jul 05 05:26:16 PM PDT 24
Finished Jul 05 05:26:22 PM PDT 24
Peak memory 220484 kb
Host smart-05b41866-e2a4-4df8-a06d-62e6591ece49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336379876 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.336379876
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2631732254
Short name T135
Test name
Test status
Simulation time 237540492 ps
CPU time 2.3 seconds
Started Jul 05 05:26:13 PM PDT 24
Finished Jul 05 05:26:16 PM PDT 24
Peak memory 213436 kb
Host smart-86aa13c3-0253-4532-9aa7-67c28858bfe8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631732254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2631732254
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3658343524
Short name T294
Test name
Test status
Simulation time 5551070679 ps
CPU time 14.29 seconds
Started Jul 05 05:26:15 PM PDT 24
Finished Jul 05 05:26:30 PM PDT 24
Peak memory 205060 kb
Host smart-842bcd7a-817f-4cc8-8d4f-7fdd342c27d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658343524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.3658343524
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.250924486
Short name T412
Test name
Test status
Simulation time 961220088 ps
CPU time 1.49 seconds
Started Jul 05 05:26:15 PM PDT 24
Finished Jul 05 05:26:17 PM PDT 24
Peak memory 204988 kb
Host smart-42a675e2-dda1-4828-ab35-2702808f84d9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250924486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.250924486
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2025018929
Short name T317
Test name
Test status
Simulation time 143547296 ps
CPU time 0.8 seconds
Started Jul 05 05:26:15 PM PDT 24
Finished Jul 05 05:26:16 PM PDT 24
Peak memory 204792 kb
Host smart-3f84646d-3bcc-45ce-9baf-0c272339b02b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025018929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
025018929
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.666336393
Short name T117
Test name
Test status
Simulation time 1153790070 ps
CPU time 7.85 seconds
Started Jul 05 05:26:14 PM PDT 24
Finished Jul 05 05:26:23 PM PDT 24
Peak memory 205172 kb
Host smart-92a1003c-b0d3-4112-ab7d-ecd5e653c976
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666336393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c
sr_outstanding.666336393
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1789750133
Short name T173
Test name
Test status
Simulation time 24464550626 ps
CPU time 67.81 seconds
Started Jul 05 05:26:15 PM PDT 24
Finished Jul 05 05:27:24 PM PDT 24
Peak memory 221676 kb
Host smart-74b1cb12-c212-4eab-b934-4f615f5ab890
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789750133 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.1789750133
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1630612550
Short name T357
Test name
Test status
Simulation time 129053492 ps
CPU time 3 seconds
Started Jul 05 05:26:13 PM PDT 24
Finished Jul 05 05:26:17 PM PDT 24
Peak memory 213384 kb
Host smart-6bf72df8-758e-4e4a-832e-19823e90557b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630612550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1630612550
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3591967147
Short name T184
Test name
Test status
Simulation time 3124696702 ps
CPU time 14.29 seconds
Started Jul 05 05:26:15 PM PDT 24
Finished Jul 05 05:26:30 PM PDT 24
Peak memory 213404 kb
Host smart-f458b5ad-d325-426e-8c0d-7976ed9e4219
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591967147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3591967147
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2611270141
Short name T388
Test name
Test status
Simulation time 1941763725 ps
CPU time 5.04 seconds
Started Jul 05 05:26:15 PM PDT 24
Finished Jul 05 05:26:20 PM PDT 24
Peak memory 215460 kb
Host smart-855330a4-9236-4955-ac17-3e18e69f4560
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611270141 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2611270141
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3566822427
Short name T126
Test name
Test status
Simulation time 191575713 ps
CPU time 2.52 seconds
Started Jul 05 05:26:19 PM PDT 24
Finished Jul 05 05:26:22 PM PDT 24
Peak memory 213420 kb
Host smart-b3e17744-710b-4b46-ad71-5202b4d0b4eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566822427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3566822427
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2208999326
Short name T299
Test name
Test status
Simulation time 4738662239 ps
CPU time 5.19 seconds
Started Jul 05 05:26:12 PM PDT 24
Finished Jul 05 05:26:18 PM PDT 24
Peak memory 205084 kb
Host smart-849ea577-44d3-4b1b-8ec9-b22b871fe035
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208999326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2208999326
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2885229059
Short name T344
Test name
Test status
Simulation time 1257000986 ps
CPU time 2.87 seconds
Started Jul 05 05:26:14 PM PDT 24
Finished Jul 05 05:26:17 PM PDT 24
Peak memory 204872 kb
Host smart-18c63eed-5bbb-4470-9ea4-256c450e050e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885229059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
885229059
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3937442376
Short name T421
Test name
Test status
Simulation time 255401303 ps
CPU time 1.39 seconds
Started Jul 05 05:26:12 PM PDT 24
Finished Jul 05 05:26:14 PM PDT 24
Peak memory 204792 kb
Host smart-56d93042-6cd0-4947-bb70-ca0f23c55224
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937442376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
937442376
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.614741613
Short name T368
Test name
Test status
Simulation time 248407978 ps
CPU time 5.29 seconds
Started Jul 05 05:26:18 PM PDT 24
Finished Jul 05 05:26:24 PM PDT 24
Peak memory 213268 kb
Host smart-40cb67da-704f-4500-a75e-efc57efd84d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614741613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.614741613
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1263762609
Short name T178
Test name
Test status
Simulation time 786459892 ps
CPU time 9.59 seconds
Started Jul 05 05:26:18 PM PDT 24
Finished Jul 05 05:26:28 PM PDT 24
Peak memory 213380 kb
Host smart-6b3d4c6c-d854-4f60-adc7-12661718c9b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263762609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1263762609
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2878129260
Short name T422
Test name
Test status
Simulation time 4651437362 ps
CPU time 5.89 seconds
Started Jul 05 05:26:28 PM PDT 24
Finished Jul 05 05:26:34 PM PDT 24
Peak memory 219736 kb
Host smart-179900ac-c00f-4eaf-9861-2067c4f9f9ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878129260 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2878129260
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.463049485
Short name T309
Test name
Test status
Simulation time 375658223 ps
CPU time 1.61 seconds
Started Jul 05 05:26:24 PM PDT 24
Finished Jul 05 05:26:26 PM PDT 24
Peak memory 213372 kb
Host smart-15baa0be-55fc-465d-8a51-d97cc5f0c217
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463049485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.463049485
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.4144065572
Short name T366
Test name
Test status
Simulation time 55256555067 ps
CPU time 79.04 seconds
Started Jul 05 05:26:21 PM PDT 24
Finished Jul 05 05:27:41 PM PDT 24
Peak memory 205072 kb
Host smart-04e9c8a8-46fb-44aa-ab53-698505bd097d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144065572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.4144065572
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1080626696
Short name T336
Test name
Test status
Simulation time 1686055525 ps
CPU time 4.72 seconds
Started Jul 05 05:26:18 PM PDT 24
Finished Jul 05 05:26:23 PM PDT 24
Peak memory 204968 kb
Host smart-73bfad88-6220-4c18-971f-0eaa744f0aa1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080626696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
080626696
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.231159679
Short name T89
Test name
Test status
Simulation time 198404751 ps
CPU time 0.93 seconds
Started Jul 05 05:26:14 PM PDT 24
Finished Jul 05 05:26:16 PM PDT 24
Peak memory 204740 kb
Host smart-0cb84e66-b327-4a2a-804d-bc8feeae4511
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231159679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.231159679
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.650312303
Short name T138
Test name
Test status
Simulation time 531925106 ps
CPU time 4.43 seconds
Started Jul 05 05:26:21 PM PDT 24
Finished Jul 05 05:26:26 PM PDT 24
Peak memory 205152 kb
Host smart-58df42c2-822f-4d2f-bb8b-0223ea97477d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650312303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.650312303
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3807638293
Short name T54
Test name
Test status
Simulation time 64543763973 ps
CPU time 65.76 seconds
Started Jul 05 05:26:20 PM PDT 24
Finished Jul 05 05:27:27 PM PDT 24
Peak memory 223136 kb
Host smart-44e85481-8c93-4d07-bd95-2056f8797057
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807638293 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3807638293
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3524377847
Short name T172
Test name
Test status
Simulation time 618081898 ps
CPU time 4.26 seconds
Started Jul 05 05:26:23 PM PDT 24
Finished Jul 05 05:26:28 PM PDT 24
Peak memory 213444 kb
Host smart-66e13319-a25f-4063-9fdd-64d3a9396f2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524377847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3524377847
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3801475673
Short name T93
Test name
Test status
Simulation time 1775043274 ps
CPU time 9.24 seconds
Started Jul 05 05:26:20 PM PDT 24
Finished Jul 05 05:26:30 PM PDT 24
Peak memory 213372 kb
Host smart-7a809ab9-09f4-4387-835d-92fb868e3776
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801475673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3801475673
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1784738575
Short name T142
Test name
Test status
Simulation time 3970339662 ps
CPU time 6.95 seconds
Started Jul 05 05:26:22 PM PDT 24
Finished Jul 05 05:26:29 PM PDT 24
Peak memory 216228 kb
Host smart-22490feb-7888-41c9-8c2c-5a594abcfced
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784738575 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1784738575
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1458204773
Short name T360
Test name
Test status
Simulation time 234286174 ps
CPU time 2.13 seconds
Started Jul 05 05:26:21 PM PDT 24
Finished Jul 05 05:26:24 PM PDT 24
Peak memory 213228 kb
Host smart-3e33db13-8a20-4562-8fc5-4b7aa2e73afd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458204773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1458204773
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2900821304
Short name T306
Test name
Test status
Simulation time 19328909714 ps
CPU time 51.34 seconds
Started Jul 05 05:26:22 PM PDT 24
Finished Jul 05 05:27:14 PM PDT 24
Peak memory 205076 kb
Host smart-09b9636a-f9c5-4c4f-b6c7-d9aede54ddd4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900821304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.2900821304
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2323755837
Short name T298
Test name
Test status
Simulation time 2025253195 ps
CPU time 6.18 seconds
Started Jul 05 05:26:27 PM PDT 24
Finished Jul 05 05:26:34 PM PDT 24
Peak memory 204940 kb
Host smart-d4f0bcda-853a-4fe5-9beb-0ebcb2c74837
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323755837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
323755837
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1128955543
Short name T296
Test name
Test status
Simulation time 192830494 ps
CPU time 0.81 seconds
Started Jul 05 05:26:21 PM PDT 24
Finished Jul 05 05:26:23 PM PDT 24
Peak memory 204776 kb
Host smart-45dc1970-7ca4-40ba-b537-7698cccba87b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128955543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
128955543
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1712577140
Short name T67
Test name
Test status
Simulation time 180887965 ps
CPU time 3.82 seconds
Started Jul 05 05:26:22 PM PDT 24
Finished Jul 05 05:26:26 PM PDT 24
Peak memory 205244 kb
Host smart-8098c312-63a3-406e-b984-86aa86b253b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712577140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1712577140
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.746065284
Short name T186
Test name
Test status
Simulation time 62338585883 ps
CPU time 93.25 seconds
Started Jul 05 05:26:27 PM PDT 24
Finished Jul 05 05:28:01 PM PDT 24
Peak memory 224180 kb
Host smart-c3f6b78b-bbd2-458f-95a1-41d26986580b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746065284 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.746065284
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.634074900
Short name T385
Test name
Test status
Simulation time 60334139 ps
CPU time 2.58 seconds
Started Jul 05 05:26:20 PM PDT 24
Finished Jul 05 05:26:23 PM PDT 24
Peak memory 213464 kb
Host smart-ff2e6dc5-bb82-4acd-a33c-1435ee5ad109
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634074900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.634074900
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2208737765
Short name T36
Test name
Test status
Simulation time 104890902 ps
CPU time 1 seconds
Started Jul 05 05:26:48 PM PDT 24
Finished Jul 05 05:26:49 PM PDT 24
Peak memory 205088 kb
Host smart-cc18bac8-75d3-4c4f-96e4-c3dfd37976c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208737765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2208737765
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3185554723
Short name T28
Test name
Test status
Simulation time 21239817035 ps
CPU time 63.22 seconds
Started Jul 05 05:26:46 PM PDT 24
Finished Jul 05 05:27:50 PM PDT 24
Peak memory 213704 kb
Host smart-47de12e1-c99e-42ab-ba11-31aa5f6342c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185554723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3185554723
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2883118666
Short name T14
Test name
Test status
Simulation time 576955916 ps
CPU time 2.27 seconds
Started Jul 05 05:26:43 PM PDT 24
Finished Jul 05 05:26:47 PM PDT 24
Peak memory 205092 kb
Host smart-0819d452-88f7-4563-b37b-49b3f8deed39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883118666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2883118666
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2509379760
Short name T147
Test name
Test status
Simulation time 131759025 ps
CPU time 0.81 seconds
Started Jul 05 05:26:44 PM PDT 24
Finished Jul 05 05:26:47 PM PDT 24
Peak memory 205080 kb
Host smart-42b161b9-31cb-402e-a459-3450cdf0d74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509379760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2509379760
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.2253104208
Short name T48
Test name
Test status
Simulation time 39947929 ps
CPU time 0.9 seconds
Started Jul 05 05:26:49 PM PDT 24
Finished Jul 05 05:26:50 PM PDT 24
Peak memory 215596 kb
Host smart-e8296e49-7ded-44ff-a885-9b148b005066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253104208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2253104208
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.588597767
Short name T208
Test name
Test status
Simulation time 3719478722 ps
CPU time 10.62 seconds
Started Jul 05 05:26:45 PM PDT 24
Finished Jul 05 05:26:57 PM PDT 24
Peak memory 213628 kb
Host smart-46cfa3bf-fe63-436c-bc44-151a69f2db6c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=588597767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.588597767
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2352439160
Short name T190
Test name
Test status
Simulation time 1655307645 ps
CPU time 2.29 seconds
Started Jul 05 05:26:48 PM PDT 24
Finished Jul 05 05:26:51 PM PDT 24
Peak memory 205068 kb
Host smart-c1bf7156-ea12-4584-8a5c-7a0fb3b22900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352439160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2352439160
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1526521739
Short name T158
Test name
Test status
Simulation time 86668880 ps
CPU time 0.83 seconds
Started Jul 05 05:26:49 PM PDT 24
Finished Jul 05 05:26:50 PM PDT 24
Peak memory 205044 kb
Host smart-cffffa46-ffd5-4801-875b-7b226f581017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526521739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1526521739
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3749670734
Short name T77
Test name
Test status
Simulation time 234066683 ps
CPU time 0.78 seconds
Started Jul 05 05:26:53 PM PDT 24
Finished Jul 05 05:26:55 PM PDT 24
Peak memory 205032 kb
Host smart-9f8d675a-1c15-40ff-9cc0-9fc52e55094c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749670734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3749670734
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1756142112
Short name T285
Test name
Test status
Simulation time 2558401156 ps
CPU time 2.38 seconds
Started Jul 05 05:26:46 PM PDT 24
Finished Jul 05 05:26:50 PM PDT 24
Peak memory 204988 kb
Host smart-bde9fc61-da02-45e3-ac45-86a900371849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756142112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1756142112
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3076939216
Short name T196
Test name
Test status
Simulation time 283117084 ps
CPU time 1.02 seconds
Started Jul 05 05:26:50 PM PDT 24
Finished Jul 05 05:26:52 PM PDT 24
Peak memory 205104 kb
Host smart-7c61b994-0313-4cfe-9312-26bf2817b437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076939216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3076939216
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2251927870
Short name T82
Test name
Test status
Simulation time 185679693 ps
CPU time 1.13 seconds
Started Jul 05 05:26:49 PM PDT 24
Finished Jul 05 05:26:50 PM PDT 24
Peak memory 205004 kb
Host smart-6029b9a4-fe34-4218-a087-cf5ab8d092ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251927870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2251927870
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.880787655
Short name T74
Test name
Test status
Simulation time 548253128 ps
CPU time 1.53 seconds
Started Jul 05 05:26:47 PM PDT 24
Finished Jul 05 05:26:49 PM PDT 24
Peak memory 205072 kb
Host smart-82915e85-f372-44f4-b392-ae9c3834d8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880787655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.880787655
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2234023986
Short name T191
Test name
Test status
Simulation time 1025378075 ps
CPU time 2.35 seconds
Started Jul 05 05:26:47 PM PDT 24
Finished Jul 05 05:26:50 PM PDT 24
Peak memory 205324 kb
Host smart-9af7a96c-3ac9-4a64-a3ff-b0f4b643c3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234023986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2234023986
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2807293753
Short name T282
Test name
Test status
Simulation time 143895254 ps
CPU time 0.91 seconds
Started Jul 05 05:26:45 PM PDT 24
Finished Jul 05 05:26:47 PM PDT 24
Peak memory 205080 kb
Host smart-5b2a046a-b8f3-4413-aefb-9ba22a1ea243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807293753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2807293753
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.1211336096
Short name T266
Test name
Test status
Simulation time 1074829914 ps
CPU time 2.16 seconds
Started Jul 05 05:26:45 PM PDT 24
Finished Jul 05 05:26:49 PM PDT 24
Peak memory 205328 kb
Host smart-401a88c0-4d35-42e5-83b4-46bbefd8df63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211336096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1211336096
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2466201031
Short name T70
Test name
Test status
Simulation time 1653425603 ps
CPU time 2.14 seconds
Started Jul 05 05:26:52 PM PDT 24
Finished Jul 05 05:26:56 PM PDT 24
Peak memory 229560 kb
Host smart-88e59461-1ccb-4e6d-96fe-ed728d17f1ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466201031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2466201031
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.153876934
Short name T252
Test name
Test status
Simulation time 2261089408 ps
CPU time 6.75 seconds
Started Jul 05 05:26:46 PM PDT 24
Finished Jul 05 05:26:54 PM PDT 24
Peak memory 205300 kb
Host smart-aeb157e5-7bea-4525-b4bc-dc6e860a43ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153876934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.153876934
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.729192582
Short name T37
Test name
Test status
Simulation time 258796594 ps
CPU time 0.9 seconds
Started Jul 05 05:26:54 PM PDT 24
Finished Jul 05 05:26:56 PM PDT 24
Peak memory 205076 kb
Host smart-efb5108e-4592-4ab0-b320-ec5c4cc9ebcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729192582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.729192582
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2714362876
Short name T75
Test name
Test status
Simulation time 34864243 ps
CPU time 0.74 seconds
Started Jul 05 05:26:56 PM PDT 24
Finished Jul 05 05:26:58 PM PDT 24
Peak memory 204996 kb
Host smart-e415d05a-160d-42ef-a57c-496391709cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714362876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2714362876
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3875330714
Short name T231
Test name
Test status
Simulation time 5901019281 ps
CPU time 4.77 seconds
Started Jul 05 05:26:49 PM PDT 24
Finished Jul 05 05:26:55 PM PDT 24
Peak memory 213656 kb
Host smart-b4788633-4b1a-4742-8985-be339c683d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875330714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3875330714
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1925035536
Short name T203
Test name
Test status
Simulation time 1082325738 ps
CPU time 1.46 seconds
Started Jul 05 05:26:48 PM PDT 24
Finished Jul 05 05:26:51 PM PDT 24
Peak memory 205080 kb
Host smart-267972fa-357a-465a-87f0-1384637cfb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925035536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1925035536
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.219525330
Short name T32
Test name
Test status
Simulation time 893536462 ps
CPU time 1.31 seconds
Started Jul 05 05:26:51 PM PDT 24
Finished Jul 05 05:26:53 PM PDT 24
Peak memory 205012 kb
Host smart-08fe9788-142c-4bb3-9fef-c8b304fe6b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219525330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.219525330
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1631159856
Short name T189
Test name
Test status
Simulation time 625604845 ps
CPU time 1.08 seconds
Started Jul 05 05:26:51 PM PDT 24
Finished Jul 05 05:26:53 PM PDT 24
Peak memory 205028 kb
Host smart-90f462b4-9523-44bd-aaa5-4d727fc51738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631159856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1631159856
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1534759058
Short name T250
Test name
Test status
Simulation time 271776572 ps
CPU time 0.86 seconds
Started Jul 05 05:26:48 PM PDT 24
Finished Jul 05 05:26:50 PM PDT 24
Peak memory 205100 kb
Host smart-93894045-63ee-45e7-91dd-a189452853f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534759058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1534759058
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1910421499
Short name T207
Test name
Test status
Simulation time 4046573422 ps
CPU time 11.65 seconds
Started Jul 05 05:26:52 PM PDT 24
Finished Jul 05 05:27:05 PM PDT 24
Peak memory 205140 kb
Host smart-6da89986-2d35-40ae-bf3c-e70881d0e30c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1910421499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.1910421499
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3903770669
Short name T263
Test name
Test status
Simulation time 1973005931 ps
CPU time 1.9 seconds
Started Jul 05 05:26:52 PM PDT 24
Finished Jul 05 05:26:55 PM PDT 24
Peak memory 205104 kb
Host smart-24583590-d3f1-42be-9816-c738c95500e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903770669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3903770669
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2253343138
Short name T209
Test name
Test status
Simulation time 131044230 ps
CPU time 0.99 seconds
Started Jul 05 05:26:54 PM PDT 24
Finished Jul 05 05:26:56 PM PDT 24
Peak memory 205080 kb
Host smart-4a2d2313-2567-4ea3-a6a6-125d20ae2838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253343138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2253343138
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.355138402
Short name T256
Test name
Test status
Simulation time 673058979 ps
CPU time 2.44 seconds
Started Jul 05 05:26:54 PM PDT 24
Finished Jul 05 05:26:58 PM PDT 24
Peak memory 205076 kb
Host smart-317b0170-11ae-420e-9dc1-0a7b008b1542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355138402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.355138402
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.914047173
Short name T275
Test name
Test status
Simulation time 516218899 ps
CPU time 1.07 seconds
Started Jul 05 05:26:52 PM PDT 24
Finished Jul 05 05:26:55 PM PDT 24
Peak memory 204984 kb
Host smart-c1616a26-cf08-4ff0-82e7-67fbe72336e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914047173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.914047173
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.716017568
Short name T233
Test name
Test status
Simulation time 145157762 ps
CPU time 0.93 seconds
Started Jul 05 05:26:55 PM PDT 24
Finished Jul 05 05:26:57 PM PDT 24
Peak memory 204968 kb
Host smart-c48e3f18-261b-4f18-897b-7f5ee17c8c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716017568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.716017568
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2739041035
Short name T265
Test name
Test status
Simulation time 327161712 ps
CPU time 1.6 seconds
Started Jul 05 05:26:50 PM PDT 24
Finished Jul 05 05:26:53 PM PDT 24
Peak memory 205080 kb
Host smart-7173545a-3da9-47a4-81c8-f7ffc6f13c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739041035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2739041035
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1642271240
Short name T187
Test name
Test status
Simulation time 1675687078 ps
CPU time 2.2 seconds
Started Jul 05 05:26:50 PM PDT 24
Finished Jul 05 05:26:53 PM PDT 24
Peak memory 205308 kb
Host smart-34a1659e-3a8b-4898-8b4e-6265fb767509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642271240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1642271240
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1429860872
Short name T24
Test name
Test status
Simulation time 377287154 ps
CPU time 0.9 seconds
Started Jul 05 05:26:54 PM PDT 24
Finished Jul 05 05:26:56 PM PDT 24
Peak memory 205080 kb
Host smart-9f8580dc-5ef9-4227-9ca0-82e29dcba5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429860872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1429860872
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.4068885926
Short name T40
Test name
Test status
Simulation time 549863292 ps
CPU time 2.14 seconds
Started Jul 05 05:26:49 PM PDT 24
Finished Jul 05 05:26:52 PM PDT 24
Peak memory 205060 kb
Host smart-42f698e0-1858-4afa-8667-a915c9ed3c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068885926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.4068885926
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.958539236
Short name T34
Test name
Test status
Simulation time 50779610 ps
CPU time 0.85 seconds
Started Jul 05 05:26:50 PM PDT 24
Finished Jul 05 05:26:51 PM PDT 24
Peak memory 213332 kb
Host smart-3cad6de0-7963-4657-8985-ea3c0504c8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958539236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.958539236
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1496705609
Short name T286
Test name
Test status
Simulation time 6451637982 ps
CPU time 16.87 seconds
Started Jul 05 05:26:49 PM PDT 24
Finished Jul 05 05:27:07 PM PDT 24
Peak memory 205356 kb
Host smart-ce2c657b-f187-44db-8d84-e42c3ec6433e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496705609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1496705609
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3453998965
Short name T51
Test name
Test status
Simulation time 685480208 ps
CPU time 2.29 seconds
Started Jul 05 05:26:59 PM PDT 24
Finished Jul 05 05:27:02 PM PDT 24
Peak memory 229208 kb
Host smart-25dfaf89-f42a-4d4d-8e35-5532366950cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453998965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3453998965
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3997635508
Short name T78
Test name
Test status
Simulation time 1353609686 ps
CPU time 1.31 seconds
Started Jul 05 05:26:52 PM PDT 24
Finished Jul 05 05:26:55 PM PDT 24
Peak memory 205284 kb
Host smart-12cb0f45-deb6-4add-8cd3-8ab2c06007a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997635508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3997635508
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2999389809
Short name T220
Test name
Test status
Simulation time 38853989 ps
CPU time 0.76 seconds
Started Jul 05 05:27:05 PM PDT 24
Finished Jul 05 05:27:07 PM PDT 24
Peak memory 205056 kb
Host smart-5adb32fc-d1df-483f-b480-8b3d0aeb3577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999389809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2999389809
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2501727697
Short name T254
Test name
Test status
Simulation time 1099696286 ps
CPU time 1.56 seconds
Started Jul 05 05:27:03 PM PDT 24
Finished Jul 05 05:27:06 PM PDT 24
Peak memory 205352 kb
Host smart-6d54c6f5-af9b-493f-b527-2db7bc58f39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501727697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2501727697
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1042806430
Short name T261
Test name
Test status
Simulation time 1415037530 ps
CPU time 3.24 seconds
Started Jul 05 05:27:01 PM PDT 24
Finished Jul 05 05:27:05 PM PDT 24
Peak memory 205292 kb
Host smart-165febe8-375c-40ce-9814-eb3392958bed
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1042806430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1042806430
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2266223968
Short name T229
Test name
Test status
Simulation time 62319255 ps
CPU time 0.81 seconds
Started Jul 05 05:27:10 PM PDT 24
Finished Jul 05 05:27:11 PM PDT 24
Peak memory 205064 kb
Host smart-695b7a26-7d68-42de-a34c-24997157566d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266223968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2266223968
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1354991284
Short name T269
Test name
Test status
Simulation time 1772000392 ps
CPU time 1.29 seconds
Started Jul 05 05:27:03 PM PDT 24
Finished Jul 05 05:27:06 PM PDT 24
Peak memory 205356 kb
Host smart-4eee2af3-8bec-4939-a333-c958bbd1c030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354991284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1354991284
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1637623768
Short name T278
Test name
Test status
Simulation time 2661440630 ps
CPU time 4.66 seconds
Started Jul 05 05:27:04 PM PDT 24
Finished Jul 05 05:27:09 PM PDT 24
Peak memory 205324 kb
Host smart-094e4237-f740-4067-92af-aff2493944a4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1637623768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.1637623768
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.309251482
Short name T270
Test name
Test status
Simulation time 2547380751 ps
CPU time 6.35 seconds
Started Jul 05 05:27:08 PM PDT 24
Finished Jul 05 05:27:15 PM PDT 24
Peak memory 213536 kb
Host smart-d68c5ed8-2016-4e6b-bb87-1db2aaddbf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309251482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.309251482
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2213460122
Short name T140
Test name
Test status
Simulation time 155049924 ps
CPU time 0.8 seconds
Started Jul 05 05:27:12 PM PDT 24
Finished Jul 05 05:27:14 PM PDT 24
Peak memory 205124 kb
Host smart-06cae823-a0a2-4cbb-9f09-65d38316f5df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213460122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2213460122
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.673700582
Short name T216
Test name
Test status
Simulation time 28449139730 ps
CPU time 24.36 seconds
Started Jul 05 05:27:03 PM PDT 24
Finished Jul 05 05:27:29 PM PDT 24
Peak memory 213512 kb
Host smart-1ea5db0d-7566-4673-8481-68f1a38f5393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673700582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.673700582
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1659369879
Short name T253
Test name
Test status
Simulation time 4973082432 ps
CPU time 2.38 seconds
Started Jul 05 05:27:06 PM PDT 24
Finished Jul 05 05:27:09 PM PDT 24
Peak memory 213648 kb
Host smart-09424fa3-04d0-41a4-b366-d86cc3186b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659369879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1659369879
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.472959337
Short name T288
Test name
Test status
Simulation time 2546610896 ps
CPU time 6.67 seconds
Started Jul 05 05:27:06 PM PDT 24
Finished Jul 05 05:27:14 PM PDT 24
Peak memory 213568 kb
Host smart-f10d6db3-5ba7-4387-b02d-36a1b23412d3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=472959337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.472959337
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3150999694
Short name T163
Test name
Test status
Simulation time 13825576285 ps
CPU time 36.98 seconds
Started Jul 05 05:27:02 PM PDT 24
Finished Jul 05 05:27:40 PM PDT 24
Peak memory 213552 kb
Host smart-c4320ca7-5430-427d-91b2-7d0405f5ae79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150999694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3150999694
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1115678810
Short name T68
Test name
Test status
Simulation time 69349312 ps
CPU time 0.87 seconds
Started Jul 05 05:27:10 PM PDT 24
Finished Jul 05 05:27:12 PM PDT 24
Peak memory 205116 kb
Host smart-6a7779c1-8e83-47e1-a94d-6db2c6eb289d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115678810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1115678810
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1782706239
Short name T80
Test name
Test status
Simulation time 3463891389 ps
CPU time 3.63 seconds
Started Jul 05 05:27:14 PM PDT 24
Finished Jul 05 05:27:19 PM PDT 24
Peak memory 213604 kb
Host smart-a7d1a23a-3ef1-45a8-8077-eb848ee2f43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782706239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1782706239
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.949702887
Short name T170
Test name
Test status
Simulation time 3394329395 ps
CPU time 4.43 seconds
Started Jul 05 05:27:15 PM PDT 24
Finished Jul 05 05:27:20 PM PDT 24
Peak memory 205428 kb
Host smart-be27568c-cec1-4858-9b10-7883987f2032
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=949702887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.949702887
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1287449948
Short name T152
Test name
Test status
Simulation time 1383832913 ps
CPU time 2.14 seconds
Started Jul 05 05:27:14 PM PDT 24
Finished Jul 05 05:27:17 PM PDT 24
Peak memory 205352 kb
Host smart-609d2ee8-616e-455d-ad3e-08b19b06eec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287449948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1287449948
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1210327083
Short name T83
Test name
Test status
Simulation time 270238698 ps
CPU time 0.78 seconds
Started Jul 05 05:27:15 PM PDT 24
Finished Jul 05 05:27:17 PM PDT 24
Peak memory 204980 kb
Host smart-e70ac72d-a79a-4dbd-b76f-5711066249e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210327083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1210327083
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2285949685
Short name T228
Test name
Test status
Simulation time 48907138589 ps
CPU time 117.08 seconds
Started Jul 05 05:27:13 PM PDT 24
Finished Jul 05 05:29:12 PM PDT 24
Peak memory 213596 kb
Host smart-2d71f639-5a44-4ae5-b4b0-4181215e19e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285949685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2285949685
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.114989564
Short name T251
Test name
Test status
Simulation time 3489862863 ps
CPU time 10.15 seconds
Started Jul 05 05:27:13 PM PDT 24
Finished Jul 05 05:27:25 PM PDT 24
Peak memory 213632 kb
Host smart-1909ac72-2af0-4a3a-810a-bc72da7bfa00
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114989564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.114989564
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.3905852947
Short name T267
Test name
Test status
Simulation time 3421256800 ps
CPU time 3.97 seconds
Started Jul 05 05:27:17 PM PDT 24
Finished Jul 05 05:27:22 PM PDT 24
Peak memory 205024 kb
Host smart-e3f0cc30-53f5-4391-a57c-f11004e4a362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905852947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3905852947
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.964956666
Short name T167
Test name
Test status
Simulation time 5363975831 ps
CPU time 2.26 seconds
Started Jul 05 05:27:11 PM PDT 24
Finished Jul 05 05:27:14 PM PDT 24
Peak memory 205308 kb
Host smart-f33a85fb-3059-4120-b7be-6caf316c056a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964956666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.964956666
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.103213793
Short name T243
Test name
Test status
Simulation time 91857011 ps
CPU time 0.81 seconds
Started Jul 05 05:27:12 PM PDT 24
Finished Jul 05 05:27:14 PM PDT 24
Peak memory 205084 kb
Host smart-21ea6a38-bb5b-40ca-8c50-42b146d8c43f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103213793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.103213793
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3532414645
Short name T205
Test name
Test status
Simulation time 16807067764 ps
CPU time 42.81 seconds
Started Jul 05 05:27:17 PM PDT 24
Finished Jul 05 05:28:02 PM PDT 24
Peak memory 213604 kb
Host smart-ba738c85-e954-4904-84f7-099dcf7f9021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532414645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3532414645
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3449380107
Short name T249
Test name
Test status
Simulation time 1091192935 ps
CPU time 1.23 seconds
Started Jul 05 05:27:13 PM PDT 24
Finished Jul 05 05:27:16 PM PDT 24
Peak memory 213508 kb
Host smart-91c792fe-7ca9-492d-9bd3-ab68ac73ec4b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449380107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3449380107
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.835814492
Short name T262
Test name
Test status
Simulation time 2438093668 ps
CPU time 3.04 seconds
Started Jul 05 05:27:14 PM PDT 24
Finished Jul 05 05:27:18 PM PDT 24
Peak memory 205488 kb
Host smart-4de2ba39-cf14-44fd-922d-1a57a2c8ed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835814492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.835814492
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2296843160
Short name T235
Test name
Test status
Simulation time 80411034 ps
CPU time 0.73 seconds
Started Jul 05 05:27:11 PM PDT 24
Finished Jul 05 05:27:13 PM PDT 24
Peak memory 205064 kb
Host smart-88aeae5e-5e3b-462c-9ecc-bc4f6e5f7438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296843160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2296843160
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.361489464
Short name T242
Test name
Test status
Simulation time 5870666358 ps
CPU time 11.01 seconds
Started Jul 05 05:27:13 PM PDT 24
Finished Jul 05 05:27:25 PM PDT 24
Peak memory 213588 kb
Host smart-bf83489b-ab96-4796-b589-9e9dfbb78527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361489464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.361489464
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3474130366
Short name T218
Test name
Test status
Simulation time 3444701981 ps
CPU time 9.55 seconds
Started Jul 05 05:27:13 PM PDT 24
Finished Jul 05 05:27:24 PM PDT 24
Peak memory 213676 kb
Host smart-b8bf2e84-3c12-4a3e-b06b-9d17bb2179ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474130366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3474130366
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1202030087
Short name T281
Test name
Test status
Simulation time 3413145055 ps
CPU time 4.41 seconds
Started Jul 05 05:27:11 PM PDT 24
Finished Jul 05 05:27:16 PM PDT 24
Peak memory 205428 kb
Host smart-4e1c4d4e-9610-4f13-933c-7ea98b01d7f2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1202030087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1202030087
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3375919883
Short name T221
Test name
Test status
Simulation time 29058991 ps
CPU time 0.76 seconds
Started Jul 05 05:27:12 PM PDT 24
Finished Jul 05 05:27:14 PM PDT 24
Peak memory 205044 kb
Host smart-4f963345-2fd4-4b61-bcb4-fa74011fdd7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375919883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3375919883
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3605890261
Short name T238
Test name
Test status
Simulation time 5314785334 ps
CPU time 6.36 seconds
Started Jul 05 05:27:11 PM PDT 24
Finished Jul 05 05:27:19 PM PDT 24
Peak memory 213544 kb
Host smart-4c47035e-641f-4ba2-8637-8f8864b68580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605890261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3605890261
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1296287195
Short name T227
Test name
Test status
Simulation time 3004108229 ps
CPU time 1.55 seconds
Started Jul 05 05:27:17 PM PDT 24
Finished Jul 05 05:27:20 PM PDT 24
Peak memory 213652 kb
Host smart-f8742aa8-5f26-41d8-82ef-69bb44e07cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296287195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1296287195
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.804413747
Short name T58
Test name
Test status
Simulation time 1460465132 ps
CPU time 2.79 seconds
Started Jul 05 05:27:13 PM PDT 24
Finished Jul 05 05:27:17 PM PDT 24
Peak memory 213500 kb
Host smart-e91165f3-5ea2-42e9-8ca8-72174a816079
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=804413747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.804413747
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1446293564
Short name T232
Test name
Test status
Simulation time 4734678235 ps
CPU time 12.27 seconds
Started Jul 05 05:27:12 PM PDT 24
Finished Jul 05 05:27:26 PM PDT 24
Peak memory 205424 kb
Host smart-7023e4c0-b5a4-451f-9f08-19039c437716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446293564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1446293564
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3873160278
Short name T59
Test name
Test status
Simulation time 61646186 ps
CPU time 0.84 seconds
Started Jul 05 05:27:17 PM PDT 24
Finished Jul 05 05:27:19 PM PDT 24
Peak memory 204712 kb
Host smart-a6eba862-9e83-4b4e-ba59-fb9af19e0476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873160278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3873160278
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2168497125
Short name T168
Test name
Test status
Simulation time 2891900567 ps
CPU time 2.92 seconds
Started Jul 05 05:27:26 PM PDT 24
Finished Jul 05 05:27:30 PM PDT 24
Peak memory 205388 kb
Host smart-feef93ed-61dc-486f-a8b5-5480403c7ac3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2168497125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2168497125
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.2127261428
Short name T84
Test name
Test status
Simulation time 5826087009 ps
CPU time 3.57 seconds
Started Jul 05 05:27:11 PM PDT 24
Finished Jul 05 05:27:16 PM PDT 24
Peak memory 213628 kb
Host smart-eb73491c-c41b-4d1d-9bc4-6795cc2169e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127261428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2127261428
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.2881022004
Short name T161
Test name
Test status
Simulation time 11248447939 ps
CPU time 8.38 seconds
Started Jul 05 05:27:15 PM PDT 24
Finished Jul 05 05:27:25 PM PDT 24
Peak memory 213480 kb
Host smart-b69b1a57-34f3-4b6d-bafd-06d38847f536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881022004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2881022004
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.655968311
Short name T279
Test name
Test status
Simulation time 66068797 ps
CPU time 0.77 seconds
Started Jul 05 05:27:17 PM PDT 24
Finished Jul 05 05:27:19 PM PDT 24
Peak memory 204992 kb
Host smart-9973a4cf-fbcb-4e22-8cbb-4a42fbae37b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655968311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.655968311
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2745257946
Short name T219
Test name
Test status
Simulation time 2109585198 ps
CPU time 3.19 seconds
Started Jul 05 05:27:18 PM PDT 24
Finished Jul 05 05:27:22 PM PDT 24
Peak memory 205488 kb
Host smart-ae22ef85-e012-48df-a780-46c566737047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745257946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2745257946
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3695246379
Short name T72
Test name
Test status
Simulation time 2316286501 ps
CPU time 2.89 seconds
Started Jul 05 05:27:20 PM PDT 24
Finished Jul 05 05:27:24 PM PDT 24
Peak memory 213580 kb
Host smart-5e0fdc16-bb59-4856-b2a1-cae2ed6205dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695246379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3695246379
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.954154519
Short name T239
Test name
Test status
Simulation time 2827855571 ps
CPU time 5.69 seconds
Started Jul 05 05:27:21 PM PDT 24
Finished Jul 05 05:27:28 PM PDT 24
Peak memory 213588 kb
Host smart-f2b09e99-6675-4092-b52c-c88d15c59d27
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=954154519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.954154519
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3991953987
Short name T204
Test name
Test status
Simulation time 10033269218 ps
CPU time 25.94 seconds
Started Jul 05 05:27:11 PM PDT 24
Finished Jul 05 05:27:38 PM PDT 24
Peak memory 213572 kb
Host smart-8a731117-0756-4ab1-858c-53014d16dadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991953987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3991953987
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.2252866839
Short name T97
Test name
Test status
Simulation time 6746408610 ps
CPU time 9.61 seconds
Started Jul 05 05:27:17 PM PDT 24
Finished Jul 05 05:27:28 PM PDT 24
Peak memory 205388 kb
Host smart-e2b9db55-9db3-4bba-a861-6acfebd3c710
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252866839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2252866839
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3768126568
Short name T274
Test name
Test status
Simulation time 53637120 ps
CPU time 0.83 seconds
Started Jul 05 05:26:57 PM PDT 24
Finished Jul 05 05:26:59 PM PDT 24
Peak memory 205052 kb
Host smart-dcebc59f-3b74-4e93-8f00-ba9a3074c5b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768126568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3768126568
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.2032984136
Short name T264
Test name
Test status
Simulation time 1547083101 ps
CPU time 5.3 seconds
Started Jul 05 05:26:56 PM PDT 24
Finished Jul 05 05:27:02 PM PDT 24
Peak memory 205332 kb
Host smart-c5b40fb9-7f09-41ed-9177-bc6af6c34857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032984136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2032984136
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2680159706
Short name T44
Test name
Test status
Simulation time 2608158029 ps
CPU time 5.85 seconds
Started Jul 05 05:27:00 PM PDT 24
Finished Jul 05 05:27:06 PM PDT 24
Peak memory 213648 kb
Host smart-8c97433a-b367-4d19-af99-05a8958e1a71
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2680159706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2680159706
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1093191892
Short name T26
Test name
Test status
Simulation time 249965606 ps
CPU time 1.28 seconds
Started Jul 05 05:26:58 PM PDT 24
Finished Jul 05 05:27:01 PM PDT 24
Peak memory 205056 kb
Host smart-81bfbc4e-9da1-4dc7-9781-86f898dc5f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093191892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1093191892
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3505617085
Short name T3
Test name
Test status
Simulation time 5891427899 ps
CPU time 8.23 seconds
Started Jul 05 05:27:00 PM PDT 24
Finished Jul 05 05:27:10 PM PDT 24
Peak memory 214324 kb
Host smart-a22111d6-f6d3-41a9-8a96-c51768c15f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505617085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3505617085
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3351487707
Short name T225
Test name
Test status
Simulation time 60488922 ps
CPU time 0.73 seconds
Started Jul 05 05:27:19 PM PDT 24
Finished Jul 05 05:27:21 PM PDT 24
Peak memory 205076 kb
Host smart-8d85dfda-3b9a-4fe6-9477-c631d12504c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351487707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3351487707
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.577429663
Short name T188
Test name
Test status
Simulation time 10806123913 ps
CPU time 30.87 seconds
Started Jul 05 05:27:17 PM PDT 24
Finished Jul 05 05:27:49 PM PDT 24
Peak memory 213488 kb
Host smart-b98ea5b1-dadf-4c46-853f-1ff27078c365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577429663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.577429663
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2061459364
Short name T255
Test name
Test status
Simulation time 63520582 ps
CPU time 0.71 seconds
Started Jul 05 05:27:20 PM PDT 24
Finished Jul 05 05:27:22 PM PDT 24
Peak memory 205088 kb
Host smart-08480299-cef7-4651-9bd5-c5a4f020267f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061459364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2061459364
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.1340235988
Short name T22
Test name
Test status
Simulation time 6606876988 ps
CPU time 5.94 seconds
Started Jul 05 05:27:19 PM PDT 24
Finished Jul 05 05:27:26 PM PDT 24
Peak memory 205316 kb
Host smart-c2633604-4e1c-466e-a825-752030b8ef4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340235988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1340235988
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.930723646
Short name T213
Test name
Test status
Simulation time 31817736 ps
CPU time 0.73 seconds
Started Jul 05 05:27:20 PM PDT 24
Finished Jul 05 05:27:22 PM PDT 24
Peak memory 205080 kb
Host smart-e452b470-9f63-4917-840a-c1538b97bd16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930723646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.930723646
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1871781200
Short name T106
Test name
Test status
Simulation time 160017132 ps
CPU time 0.77 seconds
Started Jul 05 05:27:19 PM PDT 24
Finished Jul 05 05:27:21 PM PDT 24
Peak memory 205056 kb
Host smart-060c3f83-e03b-4a8e-8cf2-b5b7e9152afa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871781200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1871781200
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.1837676592
Short name T159
Test name
Test status
Simulation time 3550842079 ps
CPU time 9.51 seconds
Started Jul 05 05:27:17 PM PDT 24
Finished Jul 05 05:27:28 PM PDT 24
Peak memory 205332 kb
Host smart-e87496be-7641-4a10-b66a-a7c385c7e473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837676592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1837676592
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.996441978
Short name T247
Test name
Test status
Simulation time 58283661 ps
CPU time 0.75 seconds
Started Jul 05 05:27:18 PM PDT 24
Finished Jul 05 05:27:20 PM PDT 24
Peak memory 205120 kb
Host smart-597107a4-0e1c-46b5-bbb9-699dfb77a827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996441978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.996441978
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.3200000561
Short name T165
Test name
Test status
Simulation time 2328051163 ps
CPU time 7.07 seconds
Started Jul 05 05:27:17 PM PDT 24
Finished Jul 05 05:27:25 PM PDT 24
Peak memory 213468 kb
Host smart-ce0dc596-228c-4991-ae74-9c8a3dc2d360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200000561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.3200000561
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3683582757
Short name T248
Test name
Test status
Simulation time 105986851 ps
CPU time 0.95 seconds
Started Jul 05 05:27:17 PM PDT 24
Finished Jul 05 05:27:20 PM PDT 24
Peak memory 205068 kb
Host smart-df4912f3-93cb-4fde-b5b7-1dbe5f4182c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683582757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3683582757
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1747861472
Short name T85
Test name
Test status
Simulation time 106192676 ps
CPU time 0.97 seconds
Started Jul 05 05:27:20 PM PDT 24
Finished Jul 05 05:27:22 PM PDT 24
Peak memory 205088 kb
Host smart-a6e06436-7ada-4f43-aaa5-e030f1d3e472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747861472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1747861472
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.729848398
Short name T200
Test name
Test status
Simulation time 67384694 ps
CPU time 0.79 seconds
Started Jul 05 05:27:18 PM PDT 24
Finished Jul 05 05:27:20 PM PDT 24
Peak memory 205088 kb
Host smart-4294a3fc-1079-4342-b0fc-209afaaee683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729848398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.729848398
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1822068164
Short name T222
Test name
Test status
Simulation time 59359177 ps
CPU time 0.74 seconds
Started Jul 05 05:27:22 PM PDT 24
Finished Jul 05 05:27:24 PM PDT 24
Peak memory 205044 kb
Host smart-d994f0d6-000b-4bd5-abdf-6a58b2b6ad0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822068164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1822068164
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1924496890
Short name T73
Test name
Test status
Simulation time 86701172 ps
CPU time 0.78 seconds
Started Jul 05 05:27:17 PM PDT 24
Finished Jul 05 05:27:19 PM PDT 24
Peak memory 205064 kb
Host smart-c5981383-2e71-46b3-950a-00d3a63d7734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924496890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1924496890
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.3866662342
Short name T6
Test name
Test status
Simulation time 2595040865 ps
CPU time 4.6 seconds
Started Jul 05 05:27:20 PM PDT 24
Finished Jul 05 05:27:26 PM PDT 24
Peak memory 205468 kb
Host smart-6512c7ad-cfa0-4a5a-b33e-19e9639026db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866662342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3866662342
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3681890472
Short name T197
Test name
Test status
Simulation time 36959475 ps
CPU time 0.77 seconds
Started Jul 05 05:26:58 PM PDT 24
Finished Jul 05 05:27:00 PM PDT 24
Peak memory 205088 kb
Host smart-50205f1b-686d-4c2d-b53b-84c697f0c552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681890472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3681890472
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2897385324
Short name T230
Test name
Test status
Simulation time 709418816 ps
CPU time 2.67 seconds
Started Jul 05 05:26:59 PM PDT 24
Finished Jul 05 05:27:03 PM PDT 24
Peak memory 213700 kb
Host smart-99e167dc-5290-4bd2-bc54-75027b78ee98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897385324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2897385324
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2137032329
Short name T46
Test name
Test status
Simulation time 10041969700 ps
CPU time 20.28 seconds
Started Jul 05 05:26:56 PM PDT 24
Finished Jul 05 05:27:17 PM PDT 24
Peak memory 205436 kb
Host smart-82621001-d302-480e-84cf-062b1991141f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137032329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2137032329
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3409462356
Short name T283
Test name
Test status
Simulation time 5039861962 ps
CPU time 14.18 seconds
Started Jul 05 05:27:01 PM PDT 24
Finished Jul 05 05:27:16 PM PDT 24
Peak memory 213632 kb
Host smart-b6ef6407-c5b8-41d1-9cc8-730eadbcceac
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409462356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.3409462356
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1141370998
Short name T206
Test name
Test status
Simulation time 224898734 ps
CPU time 1.2 seconds
Started Jul 05 05:26:55 PM PDT 24
Finished Jul 05 05:26:57 PM PDT 24
Peak memory 205092 kb
Host smart-76e4502a-2cb7-4d97-92a5-071efed93c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141370998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1141370998
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2520865155
Short name T151
Test name
Test status
Simulation time 12531359982 ps
CPU time 30.36 seconds
Started Jul 05 05:26:55 PM PDT 24
Finished Jul 05 05:27:27 PM PDT 24
Peak memory 205452 kb
Host smart-71c9c683-c5d1-4415-a2e8-a58c91963775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520865155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2520865155
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1106835390
Short name T71
Test name
Test status
Simulation time 917474684 ps
CPU time 3.15 seconds
Started Jul 05 05:26:57 PM PDT 24
Finished Jul 05 05:27:02 PM PDT 24
Peak memory 229108 kb
Host smart-6dca16d7-4a6b-4e20-9fee-b0aecc41273d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106835390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1106835390
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.603411478
Short name T226
Test name
Test status
Simulation time 52604418 ps
CPU time 0.78 seconds
Started Jul 05 05:27:21 PM PDT 24
Finished Jul 05 05:27:23 PM PDT 24
Peak memory 205084 kb
Host smart-8dd37078-b7fe-45cf-aded-af1e63960087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603411478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.603411478
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2990582353
Short name T201
Test name
Test status
Simulation time 129260013 ps
CPU time 0.84 seconds
Started Jul 05 05:27:17 PM PDT 24
Finished Jul 05 05:27:19 PM PDT 24
Peak memory 205068 kb
Host smart-a2505fe3-8dbc-40ed-a2d1-8c1b909a36f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990582353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2990582353
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.1461861573
Short name T192
Test name
Test status
Simulation time 11711292524 ps
CPU time 25.42 seconds
Started Jul 05 05:27:20 PM PDT 24
Finished Jul 05 05:27:47 PM PDT 24
Peak memory 205264 kb
Host smart-82dffd7f-bcef-4014-8b90-f62d48a8a9a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461861573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1461861573
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1744224321
Short name T257
Test name
Test status
Simulation time 29321499 ps
CPU time 0.73 seconds
Started Jul 05 05:27:25 PM PDT 24
Finished Jul 05 05:27:28 PM PDT 24
Peak memory 205028 kb
Host smart-b7845f35-bde2-44c6-b757-017cb7d68b4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744224321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1744224321
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2893679873
Short name T212
Test name
Test status
Simulation time 143471496 ps
CPU time 0.89 seconds
Started Jul 05 05:27:23 PM PDT 24
Finished Jul 05 05:27:25 PM PDT 24
Peak memory 205116 kb
Host smart-16e0e3d3-b20c-49db-bdf6-6c1498f07122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893679873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2893679873
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1779980755
Short name T277
Test name
Test status
Simulation time 45346151 ps
CPU time 0.77 seconds
Started Jul 05 05:27:28 PM PDT 24
Finished Jul 05 05:27:30 PM PDT 24
Peak memory 205016 kb
Host smart-76325c7b-9fc7-4ace-8522-ec9a10efa47a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779980755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1779980755
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.3862518187
Short name T10
Test name
Test status
Simulation time 10658160275 ps
CPU time 24.81 seconds
Started Jul 05 05:27:29 PM PDT 24
Finished Jul 05 05:27:55 PM PDT 24
Peak memory 205264 kb
Host smart-ecd73b18-bde1-45a5-b3ec-a83f64abff45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862518187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3862518187
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1969382350
Short name T198
Test name
Test status
Simulation time 69969008 ps
CPU time 0.82 seconds
Started Jul 05 05:27:26 PM PDT 24
Finished Jul 05 05:27:28 PM PDT 24
Peak memory 205124 kb
Host smart-f1beb235-dd45-4094-be36-d99099b88da5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969382350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1969382350
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3274352190
Short name T280
Test name
Test status
Simulation time 43085354 ps
CPU time 0.72 seconds
Started Jul 05 05:27:24 PM PDT 24
Finished Jul 05 05:27:27 PM PDT 24
Peak memory 205004 kb
Host smart-5d727562-ae5b-49b7-b2f5-15fcd6942168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274352190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3274352190
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.3041965628
Short name T79
Test name
Test status
Simulation time 8129585230 ps
CPU time 6.06 seconds
Started Jul 05 05:27:27 PM PDT 24
Finished Jul 05 05:27:35 PM PDT 24
Peak memory 213536 kb
Host smart-cba2fa5b-d454-4fb8-8e07-ac549e3d0b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041965628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3041965628
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1344440232
Short name T211
Test name
Test status
Simulation time 42855435 ps
CPU time 0.73 seconds
Started Jul 05 05:27:28 PM PDT 24
Finished Jul 05 05:27:30 PM PDT 24
Peak memory 205060 kb
Host smart-72b4b80f-26d2-4e79-ac5d-b10ebd849062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344440232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1344440232
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1476879969
Short name T259
Test name
Test status
Simulation time 109523384 ps
CPU time 0.8 seconds
Started Jul 05 05:27:24 PM PDT 24
Finished Jul 05 05:27:25 PM PDT 24
Peak memory 205056 kb
Host smart-ce0f5e61-f172-49d7-bcb8-072b062c9e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476879969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1476879969
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.2377472687
Short name T12
Test name
Test status
Simulation time 14473542713 ps
CPU time 21.79 seconds
Started Jul 05 05:27:27 PM PDT 24
Finished Jul 05 05:27:50 PM PDT 24
Peak memory 213492 kb
Host smart-2a21503e-2ba7-4712-835c-5e1477fcae5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377472687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2377472687
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2951843260
Short name T214
Test name
Test status
Simulation time 99330699 ps
CPU time 0.92 seconds
Started Jul 05 05:27:28 PM PDT 24
Finished Jul 05 05:27:30 PM PDT 24
Peak memory 205012 kb
Host smart-dc0a68c1-dcd6-4f21-99ad-51a67daf63d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951843260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2951843260
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1436146801
Short name T287
Test name
Test status
Simulation time 88105524 ps
CPU time 0.79 seconds
Started Jul 05 05:27:00 PM PDT 24
Finished Jul 05 05:27:01 PM PDT 24
Peak memory 204952 kb
Host smart-d4919550-82a7-420d-ab32-f749ce673f9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436146801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1436146801
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.628942742
Short name T107
Test name
Test status
Simulation time 7579516240 ps
CPU time 6.26 seconds
Started Jul 05 05:26:55 PM PDT 24
Finished Jul 05 05:27:02 PM PDT 24
Peak memory 205384 kb
Host smart-42d3a93d-4aae-4a61-acc0-4fcc09f1e099
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=628942742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl
_access.628942742
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2632593121
Short name T276
Test name
Test status
Simulation time 572843457 ps
CPU time 0.94 seconds
Started Jul 05 05:26:58 PM PDT 24
Finished Jul 05 05:27:01 PM PDT 24
Peak memory 205076 kb
Host smart-06ebf773-7bb1-4198-96fd-6e7d292ce03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632593121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2632593121
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.879144648
Short name T50
Test name
Test status
Simulation time 1522864621 ps
CPU time 5.04 seconds
Started Jul 05 05:26:55 PM PDT 24
Finished Jul 05 05:27:01 PM PDT 24
Peak memory 229184 kb
Host smart-db355789-e760-4a5b-9cd9-58ef74cff685
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879144648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.879144648
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3729201444
Short name T271
Test name
Test status
Simulation time 129763576 ps
CPU time 0.72 seconds
Started Jul 05 05:27:25 PM PDT 24
Finished Jul 05 05:27:27 PM PDT 24
Peak memory 205048 kb
Host smart-52b70c15-f1e6-466a-816f-52aec4a3911e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729201444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3729201444
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.2098082078
Short name T234
Test name
Test status
Simulation time 2043462263 ps
CPU time 5.58 seconds
Started Jul 05 05:27:25 PM PDT 24
Finished Jul 05 05:27:32 PM PDT 24
Peak memory 205256 kb
Host smart-c58addea-501b-4421-9251-b518e16f9fbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098082078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2098082078
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1577177033
Short name T45
Test name
Test status
Simulation time 33031065 ps
CPU time 0.72 seconds
Started Jul 05 05:27:24 PM PDT 24
Finished Jul 05 05:27:26 PM PDT 24
Peak memory 205060 kb
Host smart-0e8a82ba-6b43-4bbd-bb76-7fbd45115ed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577177033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1577177033
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.3373866475
Short name T98
Test name
Test status
Simulation time 3117721635 ps
CPU time 5.01 seconds
Started Jul 05 05:27:24 PM PDT 24
Finished Jul 05 05:27:30 PM PDT 24
Peak memory 205312 kb
Host smart-f7c95e8d-4dda-4f66-9ccf-78cf4b426a08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373866475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3373866475
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.264167655
Short name T223
Test name
Test status
Simulation time 50662874 ps
CPU time 0.82 seconds
Started Jul 05 05:27:24 PM PDT 24
Finished Jul 05 05:27:27 PM PDT 24
Peak memory 205080 kb
Host smart-2c806aca-f6a9-4624-9ab9-5635e8aa8c41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264167655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.264167655
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.375702568
Short name T164
Test name
Test status
Simulation time 7941635699 ps
CPU time 8.19 seconds
Started Jul 05 05:27:25 PM PDT 24
Finished Jul 05 05:27:35 PM PDT 24
Peak memory 205296 kb
Host smart-7b9dd465-88d1-4461-b0d9-f51eefaae27f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375702568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.375702568
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.2147519250
Short name T86
Test name
Test status
Simulation time 5405261377 ps
CPU time 9.18 seconds
Started Jul 05 05:27:26 PM PDT 24
Finished Jul 05 05:27:37 PM PDT 24
Peak memory 213488 kb
Host smart-eff39dca-42f2-4eb6-bf6b-f6a769ca858a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147519250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.2147519250
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.4265566931
Short name T289
Test name
Test status
Simulation time 162602406 ps
CPU time 1.14 seconds
Started Jul 05 05:27:28 PM PDT 24
Finished Jul 05 05:27:31 PM PDT 24
Peak memory 205060 kb
Host smart-9b78aa33-fc92-4946-b209-6aef0a03a593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265566931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.4265566931
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.1969437377
Short name T30
Test name
Test status
Simulation time 3027033925 ps
CPU time 7.96 seconds
Started Jul 05 05:27:25 PM PDT 24
Finished Jul 05 05:27:35 PM PDT 24
Peak memory 205292 kb
Host smart-a0cb5a0d-3c95-48d4-959a-36c40e9c9111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969437377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1969437377
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.687089565
Short name T237
Test name
Test status
Simulation time 140750893 ps
CPU time 0.9 seconds
Started Jul 05 05:27:24 PM PDT 24
Finished Jul 05 05:27:27 PM PDT 24
Peak memory 205084 kb
Host smart-11d4258c-dce9-4f38-9067-926505f30b7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687089565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.687089565
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1574626888
Short name T11
Test name
Test status
Simulation time 7444838679 ps
CPU time 20.16 seconds
Started Jul 05 05:27:27 PM PDT 24
Finished Jul 05 05:27:49 PM PDT 24
Peak memory 205360 kb
Host smart-3b5dd6d2-d952-4b12-9c6b-3236c157558b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574626888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1574626888
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3681860045
Short name T240
Test name
Test status
Simulation time 36575658 ps
CPU time 0.75 seconds
Started Jul 05 05:27:32 PM PDT 24
Finished Jul 05 05:27:34 PM PDT 24
Peak memory 205092 kb
Host smart-82aa63c2-4a77-429d-8559-a97ef91563cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681860045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3681860045
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2245667951
Short name T193
Test name
Test status
Simulation time 48531807 ps
CPU time 0.77 seconds
Started Jul 05 05:27:37 PM PDT 24
Finished Jul 05 05:27:40 PM PDT 24
Peak memory 205080 kb
Host smart-3d1ca02d-788d-4baf-a75d-ce6b4f9c3503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245667951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2245667951
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1964152198
Short name T215
Test name
Test status
Simulation time 170411669 ps
CPU time 0.73 seconds
Started Jul 05 05:27:33 PM PDT 24
Finished Jul 05 05:27:37 PM PDT 24
Peak memory 205088 kb
Host smart-7f087d82-cf08-4f52-a83c-0b5032c0e867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964152198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1964152198
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.1087156011
Short name T38
Test name
Test status
Simulation time 4450003011 ps
CPU time 5.64 seconds
Started Jul 05 05:27:34 PM PDT 24
Finished Jul 05 05:27:43 PM PDT 24
Peak memory 213488 kb
Host smart-87e612ab-634c-493d-90e7-f7a0e2379cdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087156011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1087156011
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.552678537
Short name T246
Test name
Test status
Simulation time 116179936 ps
CPU time 1.05 seconds
Started Jul 05 05:27:31 PM PDT 24
Finished Jul 05 05:27:33 PM PDT 24
Peak memory 205112 kb
Host smart-89ba97e3-b16d-4357-af7d-3c7ca3aae3d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552678537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.552678537
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2123391160
Short name T241
Test name
Test status
Simulation time 74208499 ps
CPU time 0.8 seconds
Started Jul 05 05:26:57 PM PDT 24
Finished Jul 05 05:26:59 PM PDT 24
Peak memory 205092 kb
Host smart-bb7ce7d3-42d4-436d-bfc2-cf9d6dedf904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123391160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2123391160
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.744775475
Short name T210
Test name
Test status
Simulation time 11822298357 ps
CPU time 35.34 seconds
Started Jul 05 05:27:00 PM PDT 24
Finished Jul 05 05:27:36 PM PDT 24
Peak memory 213680 kb
Host smart-8b479ee0-edd4-48c0-bb29-62ac0a8b70c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744775475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.744775475
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3051406062
Short name T145
Test name
Test status
Simulation time 2850595705 ps
CPU time 2.06 seconds
Started Jul 05 05:26:58 PM PDT 24
Finished Jul 05 05:27:01 PM PDT 24
Peak memory 213552 kb
Host smart-f7fcc0ac-1ff1-4531-9a34-b0e076592c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051406062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3051406062
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2523983397
Short name T273
Test name
Test status
Simulation time 4195131107 ps
CPU time 7.22 seconds
Started Jul 05 05:26:56 PM PDT 24
Finished Jul 05 05:27:04 PM PDT 24
Peak memory 205368 kb
Host smart-1e6125cf-bbfc-4a80-aca8-40d138d44199
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523983397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2523983397
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.2196698589
Short name T284
Test name
Test status
Simulation time 4565242421 ps
CPU time 10.74 seconds
Started Jul 05 05:27:00 PM PDT 24
Finished Jul 05 05:27:11 PM PDT 24
Peak memory 205388 kb
Host smart-c938b976-50ed-4279-bcb0-2ccfdbee3ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196698589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2196698589
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.3790582235
Short name T5
Test name
Test status
Simulation time 4085089174 ps
CPU time 4.03 seconds
Started Jul 05 05:26:57 PM PDT 24
Finished Jul 05 05:27:03 PM PDT 24
Peak memory 213988 kb
Host smart-1c2a6ab1-1c67-4974-bc08-0fa9dfd7ede1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790582235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3790582235
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2376885932
Short name T195
Test name
Test status
Simulation time 65366912 ps
CPU time 0.73 seconds
Started Jul 05 05:27:10 PM PDT 24
Finished Jul 05 05:27:12 PM PDT 24
Peak memory 205044 kb
Host smart-2a358bef-0d68-4d12-b156-1b536f0299ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376885932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2376885932
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.4033326751
Short name T260
Test name
Test status
Simulation time 1142873252 ps
CPU time 1.23 seconds
Started Jul 05 05:26:57 PM PDT 24
Finished Jul 05 05:26:59 PM PDT 24
Peak memory 205368 kb
Host smart-f3fa6019-2a85-4d6f-bd0d-7ec65510bf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033326751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.4033326751
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3511820720
Short name T194
Test name
Test status
Simulation time 6994915287 ps
CPU time 20.46 seconds
Started Jul 05 05:26:57 PM PDT 24
Finished Jul 05 05:27:19 PM PDT 24
Peak memory 213664 kb
Host smart-6a040386-4412-4fcc-82fb-a49c3f6e82fa
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3511820720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3511820720
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.417517631
Short name T162
Test name
Test status
Simulation time 6634583390 ps
CPU time 4.4 seconds
Started Jul 05 05:26:57 PM PDT 24
Finished Jul 05 05:27:03 PM PDT 24
Peak memory 205404 kb
Host smart-fe34cb94-9928-418e-9518-aa45352af3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417517631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.417517631
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.4178076528
Short name T31
Test name
Test status
Simulation time 12154925305 ps
CPU time 5.3 seconds
Started Jul 05 05:26:55 PM PDT 24
Finished Jul 05 05:27:01 PM PDT 24
Peak memory 213536 kb
Host smart-6db51d10-8b0a-46ce-a99a-bddfbf1983f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178076528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.4178076528
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2495985406
Short name T76
Test name
Test status
Simulation time 38343788 ps
CPU time 0.75 seconds
Started Jul 05 05:27:06 PM PDT 24
Finished Jul 05 05:27:08 PM PDT 24
Peak memory 205108 kb
Host smart-ca5f0f3b-aad5-4d7a-a2d7-8d36dec97bd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495985406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2495985406
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.706348303
Short name T81
Test name
Test status
Simulation time 1785215469 ps
CPU time 5.55 seconds
Started Jul 05 05:27:09 PM PDT 24
Finished Jul 05 05:27:15 PM PDT 24
Peak memory 205368 kb
Host smart-15cf3d07-d967-4057-9a62-67841f224656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706348303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.706348303
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3043599158
Short name T202
Test name
Test status
Simulation time 1514539825 ps
CPU time 2.03 seconds
Started Jul 05 05:27:04 PM PDT 24
Finished Jul 05 05:27:08 PM PDT 24
Peak memory 213512 kb
Host smart-4e6de5b4-b220-4ee9-ba18-8b966e23c77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043599158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3043599158
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1134349072
Short name T244
Test name
Test status
Simulation time 1176809356 ps
CPU time 2.57 seconds
Started Jul 05 05:27:08 PM PDT 24
Finished Jul 05 05:27:11 PM PDT 24
Peak memory 213464 kb
Host smart-7ce5a910-3b5e-4062-a230-e8142a113473
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1134349072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1134349072
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3619225948
Short name T199
Test name
Test status
Simulation time 3939191722 ps
CPU time 5.45 seconds
Started Jul 05 05:27:03 PM PDT 24
Finished Jul 05 05:27:09 PM PDT 24
Peak memory 213676 kb
Host smart-cefbc35f-9695-4bbb-8cd0-7681c0ae15a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619225948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3619225948
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2936868416
Short name T272
Test name
Test status
Simulation time 68724151 ps
CPU time 0.75 seconds
Started Jul 05 05:27:06 PM PDT 24
Finished Jul 05 05:27:08 PM PDT 24
Peak memory 205084 kb
Host smart-12499704-4caf-409d-b52b-307cc3204ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936868416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2936868416
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.1944724336
Short name T171
Test name
Test status
Simulation time 126824038272 ps
CPU time 352.69 seconds
Started Jul 05 05:27:04 PM PDT 24
Finished Jul 05 05:32:58 PM PDT 24
Peak memory 221816 kb
Host smart-a9adaa34-535a-4a49-b669-dcada0fae6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944724336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1944724336
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.341444224
Short name T217
Test name
Test status
Simulation time 13237695908 ps
CPU time 4.84 seconds
Started Jul 05 05:27:04 PM PDT 24
Finished Jul 05 05:27:10 PM PDT 24
Peak memory 213660 kb
Host smart-35495712-e37e-4e39-a96b-d8b96807a1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341444224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.341444224
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2682071450
Short name T245
Test name
Test status
Simulation time 2376908125 ps
CPU time 7.76 seconds
Started Jul 05 05:27:03 PM PDT 24
Finished Jul 05 05:27:12 PM PDT 24
Peak memory 205388 kb
Host smart-a5736459-66fe-4cf2-8acd-987aea454915
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2682071450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.2682071450
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.2109263914
Short name T21
Test name
Test status
Simulation time 3884108657 ps
CPU time 6.49 seconds
Started Jul 05 05:27:06 PM PDT 24
Finished Jul 05 05:27:14 PM PDT 24
Peak memory 214944 kb
Host smart-94e2cd78-6ca8-4bf2-85a7-1097ded4b716
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109263914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2109263914
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1992837190
Short name T43
Test name
Test status
Simulation time 33907216 ps
CPU time 0.76 seconds
Started Jul 05 05:27:10 PM PDT 24
Finished Jul 05 05:27:11 PM PDT 24
Peak memory 205092 kb
Host smart-23cb205e-aeda-46d6-bf36-01d5b92b5c95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992837190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1992837190
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3646098033
Short name T224
Test name
Test status
Simulation time 2631283283 ps
CPU time 4.68 seconds
Started Jul 05 05:27:05 PM PDT 24
Finished Jul 05 05:27:11 PM PDT 24
Peak memory 213672 kb
Host smart-5a7aef69-a423-407b-9085-1726b72a37ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646098033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3646098033
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2463779245
Short name T258
Test name
Test status
Simulation time 4466297239 ps
CPU time 12.35 seconds
Started Jul 05 05:27:04 PM PDT 24
Finished Jul 05 05:27:18 PM PDT 24
Peak memory 205372 kb
Host smart-e9412b3a-0076-4b2d-967f-6c0865f3084c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463779245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2463779245
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.4083463957
Short name T69
Test name
Test status
Simulation time 9185821561 ps
CPU time 25.48 seconds
Started Jul 05 05:27:04 PM PDT 24
Finished Jul 05 05:27:31 PM PDT 24
Peak memory 213608 kb
Host smart-34aa2952-ba3d-4d98-bd3e-c03cd11fd770
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4083463957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.4083463957
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1466770912
Short name T268
Test name
Test status
Simulation time 626846453 ps
CPU time 1.19 seconds
Started Jul 05 05:27:04 PM PDT 24
Finished Jul 05 05:27:06 PM PDT 24
Peak memory 205344 kb
Host smart-931e7609-44e8-4b68-96f3-47b986641747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466770912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1466770912
Directory /workspace/9.rv_dm_sba_tl_access/latest
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