Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	228926	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	619749	1		T3	2		T4	6		T5	8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	526966	1		T3	1		T4	6		T5	6
values[0x0]	157294	1		T3	1		T4	6		T7	1
values[0x1]	164415	1		T4	2		T5	3		T6	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	173934	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	674741	1		T3	2		T4	7		T5	8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3837	1		T17	1		T36	8		T168	2
valid_sources[0x01]	3378	1		T67	1		T35	1		T173	2
valid_sources[0x02]	2798	1		T22	5		T174	1		T62	14
valid_sources[0x03]	2672	1		T62	24		T61	10		T63	8
valid_sources[0x04]	3430	1		T36	2		T62	36		T63	14
valid_sources[0x05]	3715	1		T62	18		T63	11		T59	14
valid_sources[0x06]	2828	1		T175	1		T62	30		T63	16
valid_sources[0x07]	4089	1		T34	1		T62	19		T63	21
valid_sources[0x08]	2710	1		T4	3		T195	1		T62	23
valid_sources[0x09]	3191	1		T34	1		T22	2		T195	2
valid_sources[0x0a]	3976	1		T39	11		T62	21		T63	7
valid_sources[0x0b]	3512	1		T62	22		T63	5		T59	27
valid_sources[0x0c]	3225	1		T16	1		T62	14		T63	9
valid_sources[0x0d]	2883	1		T5	1		T165	7		T71	9
valid_sources[0x0e]	2911	1		T6	2		T196	2		T175	1
valid_sources[0x0f]	3208	1		T35	1		T169	2		T36	7
valid_sources[0x10]	3614	1		T35	1		T169	1		T62	18
valid_sources[0x11]	3402	1		T35	1		T164	2		T62	28
valid_sources[0x12]	3989	1		T174	1		T170	25		T195	1
valid_sources[0x13]	2943	1		T16	1		T35	1		T62	25
valid_sources[0x14]	4020	1		T34	1		T62	21		T58	105
valid_sources[0x15]	3243	1		T35	1		T158	48		T22	2
valid_sources[0x16]	3010	1		T42	1		T169	1		T195	1
valid_sources[0x17]	3026	1		T168	2		T62	26		T63	4
valid_sources[0x18]	3127	1		T167	1		T166	4		T62	12
valid_sources[0x19]	2926	1		T34	1		T40	2		T62	25
valid_sources[0x1a]	3201	1		T62	24		T58	60		T63	7
valid_sources[0x1b]	3091	1		T16	1		T17	2		T168	1
valid_sources[0x1c]	3168	1		T22	8		T62	22		T63	19
valid_sources[0x1d]	3300	1		T195	1		T62	22		T63	14
valid_sources[0x1e]	2879	1		T34	1		T35	2		T10	2
valid_sources[0x1f]	2843	1		T38	7		T67	1		T174	1
valid_sources[0x20]	3820	1		T5	2		T195	1		T62	20
valid_sources[0x21]	3234	1		T34	1		T164	3		T62	22
valid_sources[0x22]	3413	1		T16	1		T168	1		T62	25
valid_sources[0x23]	3042	1		T35	1		T62	29		T63	12
valid_sources[0x24]	3458	1		T164	1		T165	7		T196	2
valid_sources[0x25]	3547	1		T34	1		T62	28		T63	16
valid_sources[0x26]	3201	1		T35	1		T22	2		T196	1
valid_sources[0x27]	2832	1		T168	2		T62	23		T63	6
valid_sources[0x28]	2926	1		T62	25		T58	11		T63	9
valid_sources[0x29]	2942	1		T35	1		T43	1		T53	1
valid_sources[0x2a]	3477	1		T34	1		T36	1		T62	11
valid_sources[0x2b]	3270	1		T4	2		T162	1		T169	1
valid_sources[0x2c]	3366	1		T173	1		T196	1		T174	1
valid_sources[0x2d]	3333	1		T196	7		T62	33		T58	6
valid_sources[0x2e]	2861	1		T34	1		T195	1		T62	19
valid_sources[0x2f]	3537	1		T16	2		T167	1		T62	16
valid_sources[0x30]	3671	1		T43	1		T62	23		T61	37
valid_sources[0x31]	3042	1		T174	6		T62	31		T58	7
valid_sources[0x32]	3373	1		T35	1		T36	5		T62	20
valid_sources[0x33]	3329	1		T62	26		T63	13		T59	25
valid_sources[0x34]	3213	1		T197	3		T62	18		T63	15
valid_sources[0x35]	2920	1		T5	1		T34	1		T170	3
valid_sources[0x36]	5766	1		T5	1		T18	6		T52	1
valid_sources[0x37]	2634	1		T35	1		T50	2		T164	1
valid_sources[0x38]	3050	1		T42	1		T17	1		T62	21
valid_sources[0x39]	3741	1		T17	1		T35	1		T195	1
valid_sources[0x3a]	7094	1		T35	1		T195	1		T62	27
valid_sources[0x3b]	3469	1		T35	1		T22	5		T169	1
valid_sources[0x3c]	3554	1		T62	26		T61	52		T63	10
valid_sources[0x3d]	3690	1		T6	14		T34	1		T16	1
valid_sources[0x3e]	2762	1		T34	1		T62	34		T63	9
valid_sources[0x3f]	3409	1		T169	1		T62	23		T63	10
valid_sources[0x40]	3078	1		T67	1		T62	20		T63	17
valid_sources[0x41]	3274	1		T15	1		T42	1		T22	1
valid_sources[0x42]	3280	1		T35	1		T24	1		T164	2
valid_sources[0x43]	3972	1		T35	1		T22	2		T169	1
valid_sources[0x44]	3173	1		T35	1		T175	1		T195	1
valid_sources[0x45]	3707	1		T62	33		T58	1		T63	9
valid_sources[0x46]	3128	1		T7	1		T67	1		T35	1
valid_sources[0x47]	3394	1		T35	1		T175	2		T62	28
valid_sources[0x48]	3297	1		T29	36		T35	1		T164	2
valid_sources[0x49]	3342	1		T15	1		T35	1		T22	2
valid_sources[0x4a]	3079	1		T62	22		T63	7		T59	22
valid_sources[0x4b]	3125	1		T67	1		T34	1		T172	1
valid_sources[0x4c]	3286	1		T17	1		T198	1		T199	2
valid_sources[0x4d]	2916	1		T67	1		T17	1		T35	1
valid_sources[0x4e]	3363	1		T62	29		T63	9		T59	20
valid_sources[0x4f]	3232	1		T34	1		T52	1		T62	23
valid_sources[0x50]	4617	1		T175	2		T62	23		T63	4
valid_sources[0x51]	3110	1		T167	1		T62	22		T63	27
valid_sources[0x52]	2794	1		T62	14		T63	8		T59	23
valid_sources[0x53]	2975	1		T169	1		T11	5		T36	7
valid_sources[0x54]	3472	1		T42	1		T24	1		T174	1
valid_sources[0x55]	3478	1		T35	1		T62	23		T63	13
valid_sources[0x56]	2893	1		T62	24		T58	2		T63	4
valid_sources[0x57]	3644	1		T10	3		T62	29		T63	15
valid_sources[0x58]	3361	1		T16	2		T35	1		T174	1
valid_sources[0x59]	3345	1		T35	1		T43	1		T167	1
valid_sources[0x5a]	4705	1		T62	34		T63	15		T59	18
valid_sources[0x5b]	3162	1		T16	1		T17	1		T175	1
valid_sources[0x5c]	2978	1		T22	1		T175	1		T36	3
valid_sources[0x5d]	3219	1		T35	2		T167	1		T62	21
valid_sources[0x5e]	3158	1		T169	1		T174	1		T175	1
valid_sources[0x5f]	3458	1		T4	2		T62	27		T61	31
valid_sources[0x60]	3019	1		T17	1		T43	1		T62	27
valid_sources[0x61]	3271	1		T35	2		T62	21		T63	16
valid_sources[0x62]	3310	1		T43	1		T19	1		T62	18
valid_sources[0x63]	4197	1		T164	1		T62	21		T63	3
valid_sources[0x64]	3128	1		T42	1		T35	1		T169	1
valid_sources[0x65]	3421	1		T22	2		T175	1		T195	1
valid_sources[0x66]	3064	1		T21	3		T173	1		T62	23
valid_sources[0x67]	3203	1		T16	2		T62	21		T63	18
valid_sources[0x68]	3340	1		T24	2		T149	2		T62	15
valid_sources[0x69]	3266	1		T35	2		T169	2		T175	1
valid_sources[0x6a]	3051	1		T168	1		T62	24		T63	13
valid_sources[0x6b]	2966	1		T67	1		T16	1		T168	3
valid_sources[0x6c]	3388	1		T16	1		T17	1		T195	1
valid_sources[0x6d]	2752	1		T22	5		T174	1		T62	18
valid_sources[0x6e]	3068	1		T62	27		T63	6		T59	11
valid_sources[0x6f]	4195	1		T62	35		T63	16		T59	14
valid_sources[0x70]	2877	1		T4	1		T62	33		T63	28
valid_sources[0x71]	2958	1		T35	1		T24	1		T195	1
valid_sources[0x72]	2782	1		T35	1		T169	1		T69	18
valid_sources[0x73]	3111	1		T34	1		T62	26		T63	7
valid_sources[0x74]	3856	1		T42	1		T17	2		T35	1
valid_sources[0x75]	2738	1		T42	2		T164	3		T174	1
valid_sources[0x76]	3617	1		T17	1		T22	3		T62	28
valid_sources[0x77]	3322	1		T169	2		T36	8		T62	27
valid_sources[0x78]	3214	1		T53	1		T62	35		T63	19
valid_sources[0x79]	3253	1		T40	2		T62	28		T63	17
valid_sources[0x7a]	3379	1		T62	18		T63	6		T59	25
valid_sources[0x7b]	2827	1		T35	1		T169	1		T62	23
valid_sources[0x7c]	3067	1		T34	1		T17	1		T35	1
valid_sources[0x7d]	3333	1		T17	1		T174	2		T195	1
valid_sources[0x7e]	4080	1		T16	1		T10	3		T168	1
valid_sources[0x7f]	2901	1		T6	2		T67	1		T34	1
valid_sources[0x80]	3297	1		T164	1		T62	14		T63	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

309646

1

T3

1

T4

3

T5

4

values[0x0]

all_enables

biggest_size

154981

1

T3

1

T4

3

T5

3

values[0x1]

all_enables

biggest_size

155122

1

T5

1

T6

3

T15

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5906	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	26849	1		T1	3		T2	1		T3	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12577	1		T62	33		T58	26		T61	166
values[0x0]	9975	1		T3	1		T44	4		T45	1
values[0x1]	10203	1		T1	3		T2	1		T13	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4487	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	28268	1		T1	3		T2	1		T3	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	244	1		T4	1		T200	1		T175	1
valid_sources[0x01]	90	1		T201	2		T86	1		T96	1
valid_sources[0x02]	104	1		T46	1		T158	1		T202	1
valid_sources[0x03]	102	1		T135	6		T201	1		T62	4
valid_sources[0x04]	122	1		T41	1		T203	3		T204	1
valid_sources[0x05]	144	1		T148	1		T47	2		T104	2
valid_sources[0x06]	126	1		T46	1		T172	6		T60	2
valid_sources[0x07]	158	1		T205	1		T59	2		T86	1
valid_sources[0x08]	115	1		T206	5		T86	1		T88	1
valid_sources[0x09]	95	1		T141	2		T195	1		T60	1
valid_sources[0x0a]	141	1		T85	1		T58	19		T89	2
valid_sources[0x0b]	102	1		T34	2		T83	1		T47	4
valid_sources[0x0c]	93	1		T6	1		T60	1		T86	1
valid_sources[0x0d]	90	1		T23	1		T158	1		T69	1
valid_sources[0x0e]	74	1		T5	1		T34	1		T178	1
valid_sources[0x0f]	121	1		T60	2		T86	2		T83	3
valid_sources[0x10]	579	1		T11	3		T196	1		T61	361
valid_sources[0x11]	89	1		T23	1		T207	1		T86	1
valid_sources[0x12]	124	1		T206	1		T208	1		T209	4
valid_sources[0x13]	89	1		T45	2		T19	1		T11	1
valid_sources[0x14]	85	1		T210	1		T160	1		T94	1
valid_sources[0x15]	152	1		T28	1		T22	1		T211	10
valid_sources[0x16]	125	1		T17	6		T212	2		T88	3
valid_sources[0x17]	168	1		T77	6		T58	2		T83	6
valid_sources[0x18]	135	1		T213	8		T212	1		T214	1
valid_sources[0x19]	108	1		T215	1		T9	1		T59	4
valid_sources[0x1a]	114	1		T216	1		T86	2		T87	3
valid_sources[0x1b]	91	1		T16	2		T196	1		T217	1
valid_sources[0x1c]	109	1		T25	1		T218	1		T62	2
valid_sources[0x1d]	151	1		T25	1		T197	1		T86	2
valid_sources[0x1e]	80	1		T88	2		T47	2		T92	2
valid_sources[0x1f]	75	1		T15	1		T164	1		T47	3
valid_sources[0x20]	226	1		T196	1		T219	1		T86	1
valid_sources[0x21]	85	1		T57	3		T164	1		T136	2
valid_sources[0x22]	95	1		T24	1		T220	1		T221	3
valid_sources[0x23]	97	1		T222	1		T223	4		T224	3
valid_sources[0x24]	134	1		T47	4		T90	1		T92	5
valid_sources[0x25]	135	1		T225	1		T40	1		T63	5
valid_sources[0x26]	88	1		T197	1		T62	3		T94	1
valid_sources[0x27]	95	1		T8	1		T149	1		T83	1
valid_sources[0x28]	138	1		T35	1		T209	2		T88	4
valid_sources[0x29]	134	1		T139	1		T181	1		T84	3
valid_sources[0x2a]	95	1		T93	3		T226	1		T214	1
valid_sources[0x2b]	112	1		T88	1		T89	1		T47	5
valid_sources[0x2c]	84	1		T86	1		T87	2		T83	4
valid_sources[0x2d]	130	1		T227	1		T60	1		T86	2
valid_sources[0x2e]	114	1		T9	1		T60	1		T86	1
valid_sources[0x2f]	104	1		T33	1		T86	2		T88	1
valid_sources[0x30]	254	1		T44	1		T64	1		T162	2
valid_sources[0x31]	102	1		T93	2		T144	1		T60	1
valid_sources[0x32]	93	1		T158	1		T228	1		T86	1
valid_sources[0x33]	110	1		T229	1		T180	1		T212	2
valid_sources[0x34]	108	1		T24	1		T230	5		T95	8
valid_sources[0x35]	141	1		T44	2		T132	5		T206	3
valid_sources[0x36]	90	1		T175	1		T60	1		T86	1
valid_sources[0x37]	101	1		T6	1		T86	1		T83	2
valid_sources[0x38]	111	1		T226	2		T59	1		T86	1
valid_sources[0x39]	138	1		T10	1		T224	1		T88	1
valid_sources[0x3a]	91	1		T10	1		T74	4		T196	1
valid_sources[0x3b]	127	1		T139	2		T9	2		T216	1
valid_sources[0x3c]	101	1		T86	3		T89	1		T47	4
valid_sources[0x3d]	103	1		T14	1		T59	4		T88	2
valid_sources[0x3e]	146	1		T86	1		T83	3		T89	1
valid_sources[0x3f]	135	1		T29	9		T231	7		T142	1
valid_sources[0x40]	104	1		T222	1		T70	1		T83	4
valid_sources[0x41]	82	1		T168	1		T60	1		T83	2
valid_sources[0x42]	138	1		T3	1		T70	1		T60	2
valid_sources[0x43]	127	1		T62	1		T63	6		T86	1
valid_sources[0x44]	116	1		T25	1		T84	3		T83	1
valid_sources[0x45]	107	1		T232	1		T208	2		T152	1
valid_sources[0x46]	86	1		T60	3		T83	3		T47	1
valid_sources[0x47]	110	1		T43	1		T86	2		T83	1
valid_sources[0x48]	75	1		T23	1		T206	1		T173	4
valid_sources[0x49]	150	1		T206	2		T222	1		T167	1
valid_sources[0x4a]	186	1		T25	1		T196	1		T216	1
valid_sources[0x4b]	140	1		T208	1		T83	3		T96	1
valid_sources[0x4c]	167	1		T233	1		T167	2		T209	2
valid_sources[0x4d]	114	1		T200	1		T228	1		T60	2
valid_sources[0x4e]	111	1		T234	2		T235	2		T62	1
valid_sources[0x4f]	148	1		T50	2		T200	1		T59	4
valid_sources[0x50]	142	1		T23	1		T14	1		T137	1
valid_sources[0x51]	131	1		T12	1		T200	2		T86	1
valid_sources[0x52]	150	1		T44	1		T222	1		T69	1
valid_sources[0x53]	121	1		T5	2		T143	1		T217	1
valid_sources[0x54]	174	1		T222	1		T167	1		T150	1
valid_sources[0x55]	150	1		T6	1		T209	1		T86	1
valid_sources[0x56]	115	1		T236	1		T200	1		T83	2
valid_sources[0x57]	100	1		T32	1		T208	1		T62	1
valid_sources[0x58]	122	1		T198	1		T222	1		T86	1
valid_sources[0x59]	106	1		T79	1		T63	7		T83	5
valid_sources[0x5a]	163	1		T237	2		T208	2		T153	1
valid_sources[0x5b]	83	1		T31	1		T158	1		T238	1
valid_sources[0x5c]	103	1		T1	2		T30	1		T213	4
valid_sources[0x5d]	108	1		T160	2		T217	1		T168	2
valid_sources[0x5e]	87	1		T94	2		T83	5		T100	1
valid_sources[0x5f]	106	1		T24	1		T147	2		T220	1
valid_sources[0x60]	104	1		T46	1		T201	1		T84	15
valid_sources[0x61]	99	1		T239	7		T86	3		T83	1
valid_sources[0x62]	163	1		T226	1		T220	3		T62	4
valid_sources[0x63]	86	1		T28	1		T164	1		T52	1
valid_sources[0x64]	106	1		T59	2		T88	2		T83	3
valid_sources[0x65]	143	1		T233	1		T94	2		T60	1
valid_sources[0x66]	86	1		T6	1		T206	3		T86	1
valid_sources[0x67]	130	1		T34	2		T86	2		T83	3
valid_sources[0x68]	113	1		T222	1		T240	1		T62	5
valid_sources[0x69]	116	1		T197	1		T170	8		T59	2
valid_sources[0x6a]	102	1		T241	2		T224	3		T83	1
valid_sources[0x6b]	174	1		T226	1		T59	4		T86	1
valid_sources[0x6c]	108	1		T163	1		T10	1		T214	1
valid_sources[0x6d]	86	1		T22	1		T11	1		T209	1
valid_sources[0x6e]	123	1		T214	2		T160	1		T87	4
valid_sources[0x6f]	108	1		T210	2		T9	1		T63	7
valid_sources[0x70]	97	1		T203	1		T195	1		T83	3
valid_sources[0x71]	107	1		T171	6		T214	2		T83	1
valid_sources[0x72]	107	1		T158	1		T47	3		T91	3
valid_sources[0x73]	136	1		T157	1		T242	1		T200	1
valid_sources[0x74]	126	1		T2	1		T158	1		T208	1
valid_sources[0x75]	138	1		T44	1		T210	1		T83	3
valid_sources[0x76]	140	1		T24	1		T94	1		T60	1
valid_sources[0x77]	81	1		T6	1		T196	1		T60	1
valid_sources[0x78]	313	1		T88	1		T83	2		T47	2
valid_sources[0x79]	103	1		T25	1		T163	3		T168	1
valid_sources[0x7a]	77	1		T34	1		T60	1		T84	3
valid_sources[0x7b]	125	1		T158	1		T196	1		T59	1
valid_sources[0x7c]	154	1		T34	1		T30	1		T23	1
valid_sources[0x7d]	107	1		T25	1		T182	1		T169	9
valid_sources[0x7e]	119	1		T23	1		T243	1		T59	2
valid_sources[0x7f]	106	1		T28	2		T147	5		T244	3
valid_sources[0x80]	127	1		T200	1		T221	2		T88	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8857

1

T62

33

T58

23

T61

161

values[0x0]

all_enables

biggest_size

9113

1

T3

1

T46

2

T26

1

values[0x1]

all_enables

biggest_size

8879

1

T1

3

T2

1

T13

1