Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	285588	1		T4	8		T7	1		T5	10
full_word	622035	1		T3	2		T4	6		T5	8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	907323	1		T3	2		T4	14		T7	1
auto[TlIntgErrCmd]	109	1		T59	2		T60	2		T84	12
auto[TlIntgErrData]	95	1		T59	6		T60	7		T84	4
auto[TlIntgErrBoth]	96	1		T59	2		T60	1		T84	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	529867	1		T3	1		T4	6		T5	6
auto[1]	377756	1		T3	1		T4	8		T7	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	219807	1		T4	3		T5	2		T38	1
auto[TlIntgErrNone]	partial	auto[1]	65505	1		T4	5		T7	1		T5	8
auto[TlIntgErrNone]	full_word	auto[0]	309910	1		T3	1		T4	3		T5	4
auto[TlIntgErrNone]	full_word	auto[1]	312101	1		T3	1		T4	3		T5	4
auto[TlIntgErrCmd]	partial	auto[0]	46	1		T59	2		T60	1		T84	6
auto[TlIntgErrCmd]	partial	auto[1]	52	1		T60	1		T84	5		T86	4
auto[TlIntgErrCmd]	full_word	auto[0]	7	1		T86	1		T189	1		T190	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T84	1		T86	1		T191	2
auto[TlIntgErrData]	partial	auto[0]	51	1		T59	2		T60	4		T84	2
auto[TlIntgErrData]	partial	auto[1]	36	1		T59	4		T60	2		T84	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T60	1		T186	1		T192	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T89	1		T91	1		T189	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T59	2		T60	1		T86	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T84	4		T86	5		T87	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T88	1		T193	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T186	1		T188	1		T194	1