Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.70	96.97	57.45	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	120321097	18768	0	0
late_debug_enable_rd_A	120321097	3061	0	0
late_debug_enable_regwen_rd_A	120321097	2782	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120321097	18768	0	0
T47	133373	821	0	0
T58	8516	20	0	0
T59	31150	1	0	0
T60	56685	3	0	0
T61	23166	536	0	0
T83	212480	170	0	0
T84	222514	5	0	0
T86	147214	5	0	0
T88	243299	4	0	0
T89	338024	7	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120321097	3061	0	0
T47	133373	224	0	0
T58	8516	10	0	0
T60	56685	43	0	0
T63	20717	11	0	0
T90	10560	69	0	0
T91	118479	26	0	0
T100	12246	3	0	0
T104	16374	34	0	0
T130	26486	24	0	0
T134	12154	54	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120321097	2782	0	0
T47	133373	225	0	0
T58	8516	25	0	0
T60	56685	54	0	0
T63	20717	21	0	0
T90	10560	21	0	0
T91	118479	18	0	0
T100	12246	12	0	0
T104	16374	15	0	0
T130	26486	3	0	0
T134	12154	52	0	0