Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	87.50	100.00					75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.70	96.97	57.45	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm_enable_checker

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
36	1	1

---

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	48887186	5590368	0	0
MemTLResponseWithoutDebugIsError_A	48887186	7	0	0
NdmResetAckNeedsDebug_A	48887186	0	0	0
SbaTLRequestNeedsDebug_A	48887186	13481	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48887186	5590368	0	0
T4	20683	9670	0	0
T5	569346	203736	0	0
T6	0	147192	0	0
T7	4350	2767	0	0
T15	0	3988	0	0
T16	0	59379	0	0
T25	82113	0	0	0
T26	42312	0	0	0
T27	5469	0	0	0
T29	0	96517	0	0
T34	0	51184	0	0
T37	333172	0	0	0
T38	0	23540	0	0
T46	1513	0	0	0
T57	10431	0	0	0
T67	0	16633	0	0
T68	672137	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48887186	7	0	0
T52	2425	5	0	0
T53	0	2	0	0
T69	264492	0	0	0
T70	179844	0	0	0
T71	41691	0	0	0
T72	1817	0	0	0
T73	82050	0	0	0
T74	617937	0	0	0
T75	5659	0	0	0
T76	1365	0	0	0
T77	2588	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48887186	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48887186	13481	0	0
T1	495871	15	0	0
T2	876695	1022	0	0
T3	9364	0	0	0
T4	20683	0	0	0
T8	146065	0	0	0
T13	41975	160	0	0
T25	0	89	0	0
T26	42312	0	0	0
T28	0	81	0	0
T37	0	117	0	0
T44	1481	0	0	0
T45	4708	0	0	0
T46	1513	0	0	0
T64	0	109	0	0
T68	0	125	0	0
T78	0	126	0	0
T79	0	97	0	0