Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
8902390 |
8901096 |
0 |
0 |
selKnown1 |
55318759 |
55317465 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8902390 |
8901096 |
0 |
0 |
T1 |
39906 |
39902 |
0 |
0 |
T2 |
169014 |
169010 |
0 |
0 |
T3 |
1570 |
1566 |
0 |
0 |
T4 |
5192 |
5188 |
0 |
0 |
T5 |
0 |
6 |
0 |
0 |
T6 |
0 |
8 |
0 |
0 |
T8 |
7695 |
7691 |
0 |
0 |
T13 |
38736 |
38732 |
0 |
0 |
T25 |
0 |
18 |
0 |
0 |
T26 |
1129 |
1125 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
T28 |
0 |
12 |
0 |
0 |
T29 |
0 |
8 |
0 |
0 |
T34 |
0 |
8 |
0 |
0 |
T44 |
855 |
851 |
0 |
0 |
T45 |
439 |
435 |
0 |
0 |
T46 |
881 |
877 |
0 |
0 |
T54 |
0 |
40 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
55318759 |
55317465 |
0 |
0 |
T1 |
515827 |
515823 |
0 |
0 |
T2 |
961203 |
961199 |
0 |
0 |
T3 |
10150 |
10146 |
0 |
0 |
T4 |
23280 |
23276 |
0 |
0 |
T5 |
0 |
6 |
0 |
0 |
T6 |
0 |
8 |
0 |
0 |
T8 |
149903 |
149899 |
0 |
0 |
T13 |
61344 |
61340 |
0 |
0 |
T16 |
0 |
4 |
0 |
0 |
T17 |
0 |
10 |
0 |
0 |
T25 |
0 |
18 |
0 |
0 |
T26 |
42876 |
42872 |
0 |
0 |
T28 |
0 |
12 |
0 |
0 |
T29 |
0 |
8 |
0 |
0 |
T34 |
0 |
4 |
0 |
0 |
T44 |
1909 |
1905 |
0 |
0 |
T45 |
4928 |
4924 |
0 |
0 |
T46 |
1954 |
1950 |
0 |
0 |
T54 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2470077 |
2469863 |
0 |
0 |
selKnown1 |
48887186 |
48886972 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2470077 |
2469863 |
0 |
0 |
T1 |
19950 |
19949 |
0 |
0 |
T2 |
84506 |
84505 |
0 |
0 |
T3 |
784 |
783 |
0 |
0 |
T4 |
2595 |
2594 |
0 |
0 |
T8 |
3836 |
3835 |
0 |
0 |
T13 |
19367 |
19366 |
0 |
0 |
T26 |
562 |
561 |
0 |
0 |
T44 |
426 |
425 |
0 |
0 |
T45 |
218 |
217 |
0 |
0 |
T46 |
439 |
438 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
48887186 |
48886972 |
0 |
0 |
T1 |
495871 |
495870 |
0 |
0 |
T2 |
876695 |
876694 |
0 |
0 |
T3 |
9364 |
9363 |
0 |
0 |
T4 |
20683 |
20682 |
0 |
0 |
T8 |
146065 |
146064 |
0 |
0 |
T13 |
41975 |
41974 |
0 |
0 |
T26 |
42312 |
42311 |
0 |
0 |
T44 |
1481 |
1480 |
0 |
0 |
T45 |
4708 |
4707 |
0 |
0 |
T46 |
1513 |
1512 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
724 |
510 |
0 |
0 |
T1 |
3 |
2 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
0 |
3 |
0 |
0 |
T6 |
0 |
4 |
0 |
0 |
T8 |
11 |
10 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T26 |
2 |
1 |
0 |
0 |
T28 |
0 |
6 |
0 |
0 |
T29 |
0 |
4 |
0 |
0 |
T34 |
0 |
8 |
0 |
0 |
T44 |
1 |
0 |
0 |
0 |
T45 |
1 |
0 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T54 |
0 |
20 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
561 |
347 |
0 |
0 |
T1 |
3 |
2 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
0 |
3 |
0 |
0 |
T6 |
0 |
4 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T16 |
0 |
2 |
0 |
0 |
T17 |
0 |
5 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T28 |
0 |
6 |
0 |
0 |
T29 |
0 |
4 |
0 |
0 |
T34 |
0 |
2 |
0 |
0 |
T44 |
1 |
0 |
0 |
0 |
T45 |
1 |
0 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T54 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6429527 |
6429094 |
0 |
0 |
selKnown1 |
6429335 |
6428902 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6429527 |
6429094 |
0 |
0 |
T1 |
19950 |
19949 |
0 |
0 |
T2 |
84506 |
84505 |
0 |
0 |
T3 |
784 |
783 |
0 |
0 |
T4 |
2595 |
2594 |
0 |
0 |
T8 |
3837 |
3836 |
0 |
0 |
T13 |
19367 |
19366 |
0 |
0 |
T26 |
563 |
562 |
0 |
0 |
T44 |
427 |
426 |
0 |
0 |
T45 |
219 |
218 |
0 |
0 |
T46 |
440 |
439 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6429335 |
6428902 |
0 |
0 |
T1 |
19950 |
19949 |
0 |
0 |
T2 |
84506 |
84505 |
0 |
0 |
T3 |
784 |
783 |
0 |
0 |
T4 |
2595 |
2594 |
0 |
0 |
T8 |
3836 |
3835 |
0 |
0 |
T13 |
19367 |
19366 |
0 |
0 |
T26 |
562 |
561 |
0 |
0 |
T44 |
426 |
425 |
0 |
0 |
T45 |
218 |
217 |
0 |
0 |
T46 |
439 |
438 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2062 |
1629 |
0 |
0 |
selKnown1 |
1677 |
1244 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2062 |
1629 |
0 |
0 |
T1 |
3 |
2 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
0 |
3 |
0 |
0 |
T6 |
0 |
4 |
0 |
0 |
T8 |
11 |
10 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T26 |
2 |
1 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
T28 |
0 |
6 |
0 |
0 |
T29 |
0 |
4 |
0 |
0 |
T44 |
1 |
0 |
0 |
0 |
T45 |
1 |
0 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T54 |
0 |
20 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1677 |
1244 |
0 |
0 |
T1 |
3 |
2 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
0 |
3 |
0 |
0 |
T6 |
0 |
4 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T16 |
0 |
2 |
0 |
0 |
T17 |
0 |
5 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T28 |
0 |
6 |
0 |
0 |
T29 |
0 |
4 |
0 |
0 |
T34 |
0 |
2 |
0 |
0 |
T44 |
1 |
0 |
0 |
0 |
T45 |
1 |
0 |
0 |
0 |
T46 |
1 |
0 |
0 |
0 |
T54 |
0 |
20 |
0 |
0 |