Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 231054 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 618359 1 T4 2 T5 3 T6 10



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 527394 1 T4 1 T8 8 T18 6
values[0x0] 157759 1 T4 3 T5 2 T6 12
values[0x1] 164260 1 T4 2 T5 4 T6 17



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 177191 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 672222 1 T4 2 T5 4 T6 11



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3529 1 T21 1 T58 9 T61 4
valid_sources[0x01] 3278 1 T34 1 T58 8 T61 3
valid_sources[0x02] 4618 1 T95 1 T58 8 T59 5
valid_sources[0x03] 3532 1 T58 14 T61 1 T59 3
valid_sources[0x04] 3321 1 T187 2 T58 3 T61 2
valid_sources[0x05] 3087 1 T95 1 T58 1 T61 5
valid_sources[0x06] 3219 1 T142 3 T141 4 T58 4
valid_sources[0x07] 3439 1 T13 1 T17 1 T58 6
valid_sources[0x08] 3504 1 T58 1 T61 3 T59 4
valid_sources[0x09] 3273 1 T58 6 T61 1 T59 4
valid_sources[0x0a] 3151 1 T12 2 T58 8 T61 1
valid_sources[0x0b] 3493 1 T24 1 T58 1 T61 1
valid_sources[0x0c] 3096 1 T58 3 T61 1 T60 4
valid_sources[0x0d] 3758 1 T58 9 T59 2 T60 3
valid_sources[0x0e] 3261 1 T9 1 T146 1 T58 15
valid_sources[0x0f] 3088 1 T58 19 T61 5 T59 6
valid_sources[0x10] 3542 1 T95 1 T23 2 T188 1
valid_sources[0x11] 3234 1 T137 1 T139 3 T58 2
valid_sources[0x12] 3079 1 T58 10 T61 1 T59 3
valid_sources[0x13] 3125 1 T189 4 T58 3 T61 4
valid_sources[0x14] 3238 1 T190 6 T135 3 T58 8
valid_sources[0x15] 2921 1 T95 1 T34 2 T141 5
valid_sources[0x16] 2999 1 T13 4 T58 3 T59 5
valid_sources[0x17] 3707 1 T25 1 T58 12 T61 3
valid_sources[0x18] 3379 1 T24 2 T34 1 T58 2
valid_sources[0x19] 3245 1 T34 1 T135 2 T58 10
valid_sources[0x1a] 3411 1 T58 7 T61 3 T59 8
valid_sources[0x1b] 3283 1 T34 1 T141 9 T58 12
valid_sources[0x1c] 3334 1 T34 1 T35 1 T141 2
valid_sources[0x1d] 3723 1 T35 1 T58 12 T61 2
valid_sources[0x1e] 3516 1 T10 2 T95 3 T34 2
valid_sources[0x1f] 3033 1 T35 2 T58 11 T61 2
valid_sources[0x20] 3291 1 T34 1 T187 1 T144 9
valid_sources[0x21] 3661 1 T39 1 T14 1 T35 1
valid_sources[0x22] 3398 1 T24 1 T14 1 T58 2
valid_sources[0x23] 3234 1 T9 1 T34 1 T35 1
valid_sources[0x24] 3117 1 T34 1 T35 1 T58 5
valid_sources[0x25] 2922 1 T39 1 T34 1 T58 8
valid_sources[0x26] 3278 1 T191 1 T35 1 T58 13
valid_sources[0x27] 3325 1 T14 1 T58 8 T61 2
valid_sources[0x28] 3331 1 T20 1 T35 1 T58 6
valid_sources[0x29] 3331 1 T81 2 T58 6 T59 4
valid_sources[0x2a] 3192 1 T9 1 T16 1 T34 1
valid_sources[0x2b] 3138 1 T58 8 T61 4 T59 3
valid_sources[0x2c] 3373 1 T61 2 T59 4 T60 2
valid_sources[0x2d] 3947 1 T14 1 T35 1 T63 57
valid_sources[0x2e] 3119 1 T34 1 T14 1 T35 1
valid_sources[0x2f] 3663 1 T22 20 T34 1 T58 3
valid_sources[0x30] 3534 1 T13 2 T20 1 T58 4
valid_sources[0x31] 3458 1 T20 1 T141 3 T58 3
valid_sources[0x32] 3058 1 T95 1 T58 9 T61 1
valid_sources[0x33] 4214 1 T19 1 T58 3 T61 2
valid_sources[0x34] 3145 1 T95 1 T58 15 T61 1
valid_sources[0x35] 3227 1 T9 1 T137 3 T141 4
valid_sources[0x36] 3292 1 T142 20 T34 1 T35 1
valid_sources[0x37] 3226 1 T135 1 T58 6 T61 2
valid_sources[0x38] 3529 1 T95 1 T35 1 T58 5
valid_sources[0x39] 3012 1 T24 2 T14 1 T35 2
valid_sources[0x3a] 3165 1 T58 12 T61 3 T59 5
valid_sources[0x3b] 3461 1 T187 1 T139 4 T35 2
valid_sources[0x3c] 3512 1 T34 1 T58 2 T61 2
valid_sources[0x3d] 3114 1 T34 1 T14 1 T58 18
valid_sources[0x3e] 3270 1 T187 1 T58 15 T61 2
valid_sources[0x3f] 3140 1 T24 1 T137 2 T20 1
valid_sources[0x40] 3076 1 T13 1 T141 3 T58 1
valid_sources[0x41] 3147 1 T24 1 T146 1 T58 2
valid_sources[0x42] 3377 1 T58 2 T61 2 T59 10
valid_sources[0x43] 3578 1 T20 1 T14 1 T58 6
valid_sources[0x44] 3047 1 T135 1 T61 5 T59 16
valid_sources[0x45] 3346 1 T12 2 T139 1 T35 4
valid_sources[0x46] 3493 1 T81 2 T58 28 T61 3
valid_sources[0x47] 3202 1 T137 2 T61 4 T59 9
valid_sources[0x48] 3115 1 T39 1 T58 12 T61 1
valid_sources[0x49] 3405 1 T137 3 T58 6 T61 4
valid_sources[0x4a] 3488 1 T14 1 T35 1 T61 1
valid_sources[0x4b] 3448 1 T58 6 T61 3 T59 6
valid_sources[0x4c] 3406 1 T18 39 T34 1 T58 7
valid_sources[0x4d] 3260 1 T34 1 T61 4 T59 5
valid_sources[0x4e] 3653 1 T95 1 T135 1 T58 8
valid_sources[0x4f] 3409 1 T35 1 T61 5 T59 10
valid_sources[0x50] 3291 1 T4 6 T9 2 T14 1
valid_sources[0x51] 3028 1 T95 1 T14 1 T63 45
valid_sources[0x52] 3207 1 T34 1 T58 5 T61 2
valid_sources[0x53] 3228 1 T19 1 T34 2 T145 27
valid_sources[0x54] 3565 1 T35 1 T144 1 T58 7
valid_sources[0x55] 2952 1 T13 4 T24 3 T187 1
valid_sources[0x56] 3583 1 T141 6 T58 12 T61 2
valid_sources[0x57] 3081 1 T24 1 T146 1 T34 1
valid_sources[0x58] 3297 1 T58 5 T61 4 T59 16
valid_sources[0x59] 3169 1 T20 1 T58 10 T61 2
valid_sources[0x5a] 3191 1 T34 1 T58 4 T61 2
valid_sources[0x5b] 3619 1 T37 1 T61 2 T59 11
valid_sources[0x5c] 3150 1 T24 3 T34 1 T14 1
valid_sources[0x5d] 3288 1 T13 5 T12 1 T9 1
valid_sources[0x5e] 3159 1 T187 2 T58 6 T61 2
valid_sources[0x5f] 3291 1 T9 1 T34 1 T14 1
valid_sources[0x60] 3247 1 T35 1 T58 2 T59 9
valid_sources[0x61] 3207 1 T25 5 T14 1 T35 1
valid_sources[0x62] 3077 1 T34 2 T135 2 T63 12
valid_sources[0x63] 3251 1 T137 1 T35 1 T61 4
valid_sources[0x64] 3150 1 T13 4 T37 1 T14 2
valid_sources[0x65] 3426 1 T135 1 T35 1 T58 5
valid_sources[0x66] 3221 1 T31 1 T39 1 T135 1
valid_sources[0x67] 3361 1 T24 1 T35 2 T58 8
valid_sources[0x68] 3220 1 T25 1 T42 26 T58 4
valid_sources[0x69] 3075 1 T24 1 T95 1 T34 1
valid_sources[0x6a] 3175 1 T34 1 T139 1 T61 4
valid_sources[0x6b] 3791 1 T34 1 T58 1 T61 2
valid_sources[0x6c] 2975 1 T19 1 T141 1 T61 2
valid_sources[0x6d] 3426 1 T24 1 T34 1 T58 13
valid_sources[0x6e] 3280 1 T81 1 T58 2 T61 1
valid_sources[0x6f] 3536 1 T95 1 T58 2 T61 2
valid_sources[0x70] 3338 1 T39 1 T139 2 T58 6
valid_sources[0x71] 3247 1 T31 1 T138 19 T135 2
valid_sources[0x72] 3065 1 T58 3 T61 2 T59 4
valid_sources[0x73] 3767 1 T17 1 T34 1 T58 1
valid_sources[0x74] 3362 1 T24 2 T58 1 T61 2
valid_sources[0x75] 3025 1 T95 2 T58 12 T61 4
valid_sources[0x76] 3405 1 T137 8 T35 1 T58 6
valid_sources[0x77] 3480 1 T24 1 T20 1 T34 2
valid_sources[0x78] 3257 1 T34 1 T58 8 T61 3
valid_sources[0x79] 3065 1 T24 1 T61 2 T59 9
valid_sources[0x7a] 4271 1 T13 1 T58 11 T61 2
valid_sources[0x7b] 3285 1 T9 2 T58 4 T59 4
valid_sources[0x7c] 3308 1 T34 2 T139 1 T35 3
valid_sources[0x7d] 3321 1 T144 3 T58 3 T61 2
valid_sources[0x7e] 3136 1 T25 4 T9 1 T61 1
valid_sources[0x7f] 3283 1 T24 1 T137 1 T34 1
valid_sources[0x80] 3961 1 T20 1 T192 11 T58 13



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 306859 1 T8 4 T18 4 T24 4
values[0x0] all_enables biggest_size 155586 1 T4 1 T5 2 T6 5
values[0x1] all_enables biggest_size 155914 1 T4 1 T5 1 T6 5


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5623 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 21660 1 T1 1 T2 1 T7 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 10710 1 T63 3 T58 18 T61 100
values[0x0] 8248 1 T7 1 T4 4 T26 6
values[0x1] 8325 1 T1 1 T2 1 T4 2



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4390 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 22893 1 T1 1 T2 1 T7 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 145 1 T193 2 T21 1 T140 2
valid_sources[0x01] 52 1 T60 1 T90 1 T89 2
valid_sources[0x02] 89 1 T194 1 T61 1 T90 3
valid_sources[0x03] 63 1 T12 2 T139 7 T60 1
valid_sources[0x04] 108 1 T195 1 T21 1 T61 3
valid_sources[0x05] 73 1 T137 1 T90 1 T98 1
valid_sources[0x06] 78 1 T128 1 T196 1 T137 1
valid_sources[0x07] 369 1 T43 4 T148 2 T90 1
valid_sources[0x08] 102 1 T57 2 T8 8 T24 1
valid_sources[0x09] 55 1 T197 1 T61 1 T60 1
valid_sources[0x0a] 53 1 T166 1 T198 1 T90 3
valid_sources[0x0b] 93 1 T199 1 T90 2 T98 7
valid_sources[0x0c] 87 1 T61 4 T60 1 T90 1
valid_sources[0x0d] 193 1 T192 1 T200 1 T59 2
valid_sources[0x0e] 101 1 T127 1 T201 1 T202 1
valid_sources[0x0f] 296 1 T27 4 T203 1 T140 1
valid_sources[0x10] 70 1 T13 2 T204 5 T61 2
valid_sources[0x11] 102 1 T205 1 T206 1 T90 1
valid_sources[0x12] 93 1 T85 1 T61 1 T90 3
valid_sources[0x13] 335 1 T16 1 T153 2 T61 2
valid_sources[0x14] 92 1 T199 1 T207 1 T78 1
valid_sources[0x15] 91 1 T61 3 T91 1 T100 4
valid_sources[0x16] 120 1 T27 3 T48 13 T22 2
valid_sources[0x17] 58 1 T75 6 T140 1 T61 1
valid_sources[0x18] 93 1 T208 3 T195 1 T197 1
valid_sources[0x19] 88 1 T61 1 T98 7 T91 1
valid_sources[0x1a] 99 1 T127 1 T209 8 T61 1
valid_sources[0x1b] 103 1 T210 1 T161 1 T211 1
valid_sources[0x1c] 72 1 T127 1 T207 1 T71 1
valid_sources[0x1d] 65 1 T61 1 T59 1 T89 1
valid_sources[0x1e] 40 1 T21 1 T212 1 T90 1
valid_sources[0x1f] 100 1 T213 1 T207 1 T60 3
valid_sources[0x20] 81 1 T40 1 T89 1 T98 1
valid_sources[0x21] 62 1 T1 1 T127 1 T100 4
valid_sources[0x22] 124 1 T214 1 T215 1 T216 1
valid_sources[0x23] 266 1 T217 1 T61 3 T59 2
valid_sources[0x24] 83 1 T84 1 T127 1 T70 2
valid_sources[0x25] 74 1 T13 1 T61 1 T90 1
valid_sources[0x26] 85 1 T216 1 T90 2 T98 1
valid_sources[0x27] 157 1 T218 1 T215 1 T61 3
valid_sources[0x28] 83 1 T219 2 T141 1 T61 3
valid_sources[0x29] 68 1 T22 1 T61 4 T60 4
valid_sources[0x2a] 66 1 T220 1 T59 2 T89 2
valid_sources[0x2b] 67 1 T24 1 T89 1 T97 1
valid_sources[0x2c] 49 1 T207 1 T141 2 T61 6
valid_sources[0x2d] 212 1 T13 4 T217 4 T61 1
valid_sources[0x2e] 80 1 T140 1 T90 3 T89 2
valid_sources[0x2f] 94 1 T221 4 T78 1 T222 7
valid_sources[0x30] 85 1 T64 1 T194 1 T205 1
valid_sources[0x31] 59 1 T205 1 T61 2 T62 2
valid_sources[0x32] 104 1 T216 1 T59 16 T100 5
valid_sources[0x33] 76 1 T203 1 T144 9 T89 1
valid_sources[0x34] 77 1 T29 1 T9 3 T194 1
valid_sources[0x35] 67 1 T61 3 T90 2 T97 1
valid_sources[0x36] 74 1 T57 2 T208 1 T90 1
valid_sources[0x37] 71 1 T15 1 T90 1 T100 1
valid_sources[0x38] 70 1 T223 1 T206 1 T60 2
valid_sources[0x39] 231 1 T224 4 T212 2 T89 1
valid_sources[0x3a] 68 1 T208 2 T58 2 T61 3
valid_sources[0x3b] 67 1 T192 1 T63 1 T61 1
valid_sources[0x3c] 91 1 T24 1 T61 1 T90 3
valid_sources[0x3d] 146 1 T216 1 T98 1 T93 2
valid_sources[0x3e] 78 1 T203 1 T143 3 T61 1
valid_sources[0x3f] 57 1 T196 1 T58 1 T90 1
valid_sources[0x40] 117 1 T13 1 T17 1 T141 1
valid_sources[0x41] 64 1 T145 1 T93 4 T100 2
valid_sources[0x42] 126 1 T25 6 T225 1 T89 3
valid_sources[0x43] 60 1 T90 1 T98 5 T93 1
valid_sources[0x44] 62 1 T61 8 T92 11 T100 1
valid_sources[0x45] 236 1 T31 1 T226 1 T150 4
valid_sources[0x46] 60 1 T61 9 T60 5 T98 7
valid_sources[0x47] 57 1 T194 1 T150 2 T215 1
valid_sources[0x48] 137 1 T227 1 T89 3 T91 1
valid_sources[0x49] 80 1 T89 1 T98 5 T92 29
valid_sources[0x4a] 140 1 T96 11 T100 4 T103 4
valid_sources[0x4b] 82 1 T12 5 T194 1 T90 1
valid_sources[0x4c] 92 1 T95 2 T61 1 T90 1
valid_sources[0x4d] 97 1 T221 1 T63 1 T90 3
valid_sources[0x4e] 74 1 T89 1 T93 4 T100 2
valid_sources[0x4f] 105 1 T127 1 T64 1 T201 2
valid_sources[0x50] 114 1 T208 1 T228 2 T90 1
valid_sources[0x51] 95 1 T218 5 T228 1 T72 7
valid_sources[0x52] 227 1 T4 1 T58 7 T59 4
valid_sources[0x53] 73 1 T90 1 T91 1 T100 2
valid_sources[0x54] 129 1 T229 1 T211 1 T216 1
valid_sources[0x55] 57 1 T26 6 T230 1 T61 2
valid_sources[0x56] 118 1 T30 1 T81 5 T140 1
valid_sources[0x57] 78 1 T89 6 T97 1 T93 10
valid_sources[0x58] 108 1 T57 1 T95 1 T228 1
valid_sources[0x59] 104 1 T227 1 T170 1 T145 1
valid_sources[0x5a] 71 1 T46 1 T98 1 T93 3
valid_sources[0x5b] 100 1 T20 1 T61 4 T100 2
valid_sources[0x5c] 79 1 T6 1 T14 7 T141 1
valid_sources[0x5d] 72 1 T205 2 T89 2 T91 1
valid_sources[0x5e] 67 1 T24 1 T20 1 T211 2
valid_sources[0x5f] 96 1 T90 1 T98 16 T91 1
valid_sources[0x60] 84 1 T49 1 T37 1 T207 1
valid_sources[0x61] 246 1 T129 1 T134 1 T231 1
valid_sources[0x62] 103 1 T205 1 T217 1 T58 1
valid_sources[0x63] 93 1 T29 1 T61 2 T90 2
valid_sources[0x64] 79 1 T205 1 T216 1 T60 1
valid_sources[0x65] 70 1 T22 1 T199 2 T145 2
valid_sources[0x66] 66 1 T90 1 T89 5 T92 3
valid_sources[0x67] 115 1 T148 6 T145 1 T90 3
valid_sources[0x68] 63 1 T232 1 T203 1 T90 1
valid_sources[0x69] 70 1 T54 1 T151 1 T61 2
valid_sources[0x6a] 85 1 T190 1 T89 1 T98 3
valid_sources[0x6b] 73 1 T215 2 T63 1 T90 2
valid_sources[0x6c] 75 1 T158 1 T61 3 T90 3
valid_sources[0x6d] 63 1 T233 7 T90 1 T89 3
valid_sources[0x6e] 84 1 T127 1 T195 1 T61 2
valid_sources[0x6f] 67 1 T22 1 T234 1 T89 3
valid_sources[0x70] 53 1 T197 1 T156 1 T61 2
valid_sources[0x71] 72 1 T6 1 T62 1 T90 1
valid_sources[0x72] 78 1 T22 1 T59 3 T90 3
valid_sources[0x73] 361 1 T195 2 T137 1 T191 1
valid_sources[0x74] 94 1 T173 1 T39 1 T217 1
valid_sources[0x75] 95 1 T235 1 T83 11 T61 2
valid_sources[0x76] 249 1 T49 1 T6 1 T199 3
valid_sources[0x77] 105 1 T195 1 T236 1 T197 1
valid_sources[0x78] 78 1 T49 1 T193 1 T194 1
valid_sources[0x79] 95 1 T237 7 T228 1 T192 1
valid_sources[0x7a] 93 1 T169 1 T69 19 T217 2
valid_sources[0x7b] 93 1 T90 2 T89 3 T93 2
valid_sources[0x7c] 63 1 T127 2 T90 4 T89 1
valid_sources[0x7d] 93 1 T49 1 T238 9 T237 3
valid_sources[0x7e] 84 1 T78 1 T217 1 T61 5
valid_sources[0x7f] 94 1 T195 1 T138 10 T199 1
valid_sources[0x80] 72 1 T232 1 T225 1 T230 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7289 1 T58 11 T61 95 T62 3
values[0x0] all_enables biggest_size 7384 1 T7 1 T4 4 T26 6
values[0x1] all_enables biggest_size 6987 1 T1 1 T2 1 T4 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%