Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
280606 |
1 |
|
T4 |
4 |
|
T5 |
3 |
|
T6 |
19 |
full_word |
620399 |
1 |
|
T4 |
2 |
|
T5 |
3 |
|
T6 |
10 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
900755 |
1 |
|
T4 |
6 |
|
T5 |
6 |
|
T6 |
29 |
auto[TlIntgErrCmd] |
82 |
1 |
|
T91 |
5 |
|
T130 |
7 |
|
T133 |
3 |
auto[TlIntgErrData] |
78 |
1 |
|
T91 |
2 |
|
T130 |
6 |
|
T133 |
5 |
auto[TlIntgErrBoth] |
90 |
1 |
|
T91 |
3 |
|
T130 |
7 |
|
T133 |
2 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
529959 |
1 |
|
T4 |
1 |
|
T8 |
8 |
|
T18 |
6 |
auto[1] |
371046 |
1 |
|
T4 |
5 |
|
T5 |
6 |
|
T6 |
29 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
222716 |
1 |
|
T4 |
1 |
|
T8 |
4 |
|
T18 |
2 |
auto[TlIntgErrNone] |
partial |
auto[1] |
57661 |
1 |
|
T4 |
3 |
|
T5 |
3 |
|
T6 |
19 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
307134 |
1 |
|
T8 |
4 |
|
T18 |
4 |
|
T24 |
4 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
313244 |
1 |
|
T4 |
2 |
|
T5 |
3 |
|
T6 |
10 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
31 |
1 |
|
T91 |
2 |
|
T130 |
3 |
|
T133 |
2 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
44 |
1 |
|
T91 |
2 |
|
T130 |
4 |
|
T133 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
3 |
1 |
|
T175 |
1 |
|
T184 |
2 |
|
- |
- |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
4 |
1 |
|
T91 |
1 |
|
T185 |
1 |
|
T175 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
37 |
1 |
|
T91 |
1 |
|
T130 |
4 |
|
T133 |
3 |
auto[TlIntgErrData] |
partial |
auto[1] |
34 |
1 |
|
T91 |
1 |
|
T130 |
2 |
|
T133 |
2 |
auto[TlIntgErrData] |
full_word |
auto[0] |
2 |
1 |
|
T175 |
1 |
|
T186 |
1 |
|
- |
- |
auto[TlIntgErrData] |
full_word |
auto[1] |
5 |
1 |
|
T179 |
1 |
|
T175 |
1 |
|
T178 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
34 |
1 |
|
T91 |
1 |
|
T130 |
3 |
|
T133 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
49 |
1 |
|
T91 |
1 |
|
T130 |
4 |
|
T133 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
2 |
1 |
|
T183 |
1 |
|
T177 |
1 |
|
- |
- |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
5 |
1 |
|
T91 |
1 |
|
T185 |
1 |
|
T182 |
2 |