Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	122203077	17318	0	0
late_debug_enable_rd_A	122203077	5128	0	0
late_debug_enable_regwen_rd_A	122203077	3734	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122203077	17318	0	0
T58	38989	12	0	0
T59	164978	83	0	0
T60	431863	17	0	0
T61	6131	575	0	0
T89	35686	214	0	0
T90	9924	155	0	0
T91	285262	1	0	0
T92	9402	491	0	0
T93	8521	415	0	0
T94	271665	233	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122203077	5128	0	0
T58	38989	10	0	0
T100	737792	433	0	0
T101	17607	5	0	0
T109	39069	27	0	0
T110	8773	3	0	0
T112	11446	9	0	0
T126	8143	5	0	0
T130	192227	57	0	0
T131	62679	90	0	0
T132	56063	13	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122203077	3734	0	0
T58	38989	18	0	0
T100	737792	433	0	0
T101	17607	10	0	0
T108	5318	1	0	0
T109	39069	40	0	0
T110	8773	2	0	0
T112	11446	5	0	0
T126	8143	6	0	0
T130	192227	78	0	0
T131	62679	81	0	0