Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	87.50	100.00					75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm_enable_checker

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
36	1	1

---

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	59960735	5204279	0	0
MemTLResponseWithoutDebugIsError_A	59960735	3	0	0
NdmResetAckNeedsDebug_A	59960735	0	0	0
SbaTLRequestNeedsDebug_A	59960735	10317	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59960735	5204279	0	0
T4	28194	16579	0	0
T5	0	187304	0	0
T6	0	43188	0	0
T8	0	21768	0	0
T11	681207	0	0	0
T12	0	69835	0	0
T13	0	208114	0	0
T15	0	94616	0	0
T18	0	345793	0	0
T24	0	389464	0	0
T26	811083	0	0	0
T27	201005	0	0	0
T29	128443	0	0	0
T40	75975	0	0	0
T41	266770	0	0	0
T43	0	281890	0	0
T48	13901	0	0	0
T49	3688	0	0	0
T55	232742	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59960735	3	0	0
T47	1059	3	0	0
T52	119808	0	0	0
T76	60625	0	0	0
T77	696694	0	0	0
T78	2920	0	0	0
T79	182185	0	0	0
T80	8206	0	0	0
T81	297872	0	0	0
T82	2367	0	0	0
T83	1179	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59960735	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59960735	10317	0	0
T1	969604	63	0	0
T2	162287	157	0	0
T3	42754	0	0	0
T4	28194	0	0	0
T7	29179	0	0	0
T11	681207	40	0	0
T26	811083	97	0	0
T27	201005	250	0	0
T29	0	27	0	0
T40	75975	80	0	0
T41	266770	35	0	0
T55	0	101	0	0
T84	0	76	0	0