Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
8747891 |
8746619 |
0 |
0 |
selKnown1 |
66039956 |
66038684 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8747891 |
8746619 |
0 |
0 |
T1 |
20063 |
20061 |
0 |
0 |
T2 |
34566 |
34564 |
0 |
0 |
T3 |
4932 |
4930 |
0 |
0 |
T4 |
12256 |
12252 |
0 |
0 |
T5 |
0 |
20 |
0 |
0 |
T6 |
0 |
4 |
0 |
0 |
T7 |
1664 |
1662 |
0 |
0 |
T8 |
0 |
23 |
0 |
0 |
T11 |
21149 |
21145 |
0 |
0 |
T26 |
38690 |
38686 |
0 |
0 |
T27 |
59874 |
59870 |
0 |
0 |
T28 |
0 |
10 |
0 |
0 |
T29 |
4 |
2 |
0 |
0 |
T40 |
25361 |
25357 |
0 |
0 |
T41 |
9693 |
9689 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
T48 |
2 |
0 |
0 |
0 |
T49 |
2 |
0 |
0 |
0 |
T54 |
0 |
10 |
0 |
0 |
T55 |
2 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
66039956 |
66038684 |
0 |
0 |
T1 |
979635 |
979633 |
0 |
0 |
T2 |
179570 |
179568 |
0 |
0 |
T3 |
45220 |
45218 |
0 |
0 |
T4 |
34324 |
34320 |
0 |
0 |
T5 |
0 |
4 |
0 |
0 |
T6 |
0 |
4 |
0 |
0 |
T7 |
30011 |
30009 |
0 |
0 |
T8 |
0 |
10 |
0 |
0 |
T11 |
691782 |
691778 |
0 |
0 |
T26 |
830435 |
830431 |
0 |
0 |
T27 |
230952 |
230948 |
0 |
0 |
T29 |
4 |
2 |
0 |
0 |
T40 |
88656 |
88652 |
0 |
0 |
T41 |
271617 |
271613 |
0 |
0 |
T43 |
0 |
8 |
0 |
0 |
T48 |
2 |
0 |
0 |
0 |
T49 |
2 |
0 |
0 |
0 |
T54 |
0 |
10 |
0 |
0 |
T55 |
2 |
0 |
0 |
0 |
T56 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2668003 |
2667793 |
0 |
0 |
selKnown1 |
59960735 |
59960525 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2668003 |
2667793 |
0 |
0 |
T1 |
10031 |
10030 |
0 |
0 |
T2 |
17283 |
17282 |
0 |
0 |
T3 |
2466 |
2465 |
0 |
0 |
T4 |
6126 |
6125 |
0 |
0 |
T7 |
832 |
831 |
0 |
0 |
T11 |
10573 |
10572 |
0 |
0 |
T26 |
19338 |
19337 |
0 |
0 |
T27 |
29927 |
29926 |
0 |
0 |
T40 |
12679 |
12678 |
0 |
0 |
T41 |
4845 |
4844 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
59960735 |
59960525 |
0 |
0 |
T1 |
969604 |
969603 |
0 |
0 |
T2 |
162287 |
162286 |
0 |
0 |
T3 |
42754 |
42753 |
0 |
0 |
T4 |
28194 |
28193 |
0 |
0 |
T7 |
29179 |
29178 |
0 |
0 |
T11 |
681207 |
681206 |
0 |
0 |
T26 |
811083 |
811082 |
0 |
0 |
T27 |
201005 |
201004 |
0 |
0 |
T40 |
75975 |
75974 |
0 |
0 |
T41 |
266770 |
266769 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
708 |
498 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
0 |
7 |
0 |
0 |
T6 |
0 |
2 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T26 |
7 |
6 |
0 |
0 |
T27 |
10 |
9 |
0 |
0 |
T28 |
0 |
5 |
0 |
0 |
T29 |
2 |
1 |
0 |
0 |
T40 |
1 |
0 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T49 |
1 |
0 |
0 |
0 |
T54 |
0 |
5 |
0 |
0 |
T55 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563 |
353 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T6 |
0 |
2 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T26 |
7 |
6 |
0 |
0 |
T27 |
10 |
9 |
0 |
0 |
T29 |
2 |
1 |
0 |
0 |
T40 |
1 |
0 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T49 |
1 |
0 |
0 |
0 |
T54 |
0 |
5 |
0 |
0 |
T55 |
1 |
0 |
0 |
0 |
T56 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6077388 |
6076962 |
0 |
0 |
selKnown1 |
6077195 |
6076769 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6077388 |
6076962 |
0 |
0 |
T1 |
10032 |
10031 |
0 |
0 |
T2 |
17283 |
17282 |
0 |
0 |
T3 |
2466 |
2465 |
0 |
0 |
T4 |
6126 |
6125 |
0 |
0 |
T7 |
832 |
831 |
0 |
0 |
T11 |
10574 |
10573 |
0 |
0 |
T26 |
19338 |
19337 |
0 |
0 |
T27 |
29927 |
29926 |
0 |
0 |
T40 |
12680 |
12679 |
0 |
0 |
T41 |
4846 |
4845 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6077195 |
6076769 |
0 |
0 |
T1 |
10031 |
10030 |
0 |
0 |
T2 |
17283 |
17282 |
0 |
0 |
T3 |
2466 |
2465 |
0 |
0 |
T4 |
6126 |
6125 |
0 |
0 |
T7 |
832 |
831 |
0 |
0 |
T11 |
10573 |
10572 |
0 |
0 |
T26 |
19338 |
19337 |
0 |
0 |
T27 |
29927 |
29926 |
0 |
0 |
T40 |
12679 |
12678 |
0 |
0 |
T41 |
4845 |
4844 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1792 |
1366 |
0 |
0 |
selKnown1 |
1463 |
1037 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792 |
1366 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
0 |
13 |
0 |
0 |
T6 |
0 |
2 |
0 |
0 |
T8 |
0 |
18 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T26 |
7 |
6 |
0 |
0 |
T27 |
10 |
9 |
0 |
0 |
T28 |
0 |
5 |
0 |
0 |
T29 |
2 |
1 |
0 |
0 |
T40 |
1 |
0 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T43 |
0 |
6 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T49 |
1 |
0 |
0 |
0 |
T54 |
0 |
5 |
0 |
0 |
T55 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1463 |
1037 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T6 |
0 |
2 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T26 |
7 |
6 |
0 |
0 |
T27 |
10 |
9 |
0 |
0 |
T29 |
2 |
1 |
0 |
0 |
T40 |
1 |
0 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T49 |
1 |
0 |
0 |
0 |
T54 |
0 |
5 |
0 |
0 |
T55 |
1 |
0 |
0 |
0 |
T56 |
0 |
2 |
0 |
0 |