SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
82.66 | 98.04 | 77.78 | 100.00 | 87.50 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1260 | 1260 | 0 | 0 |
OutputsKnown_A | 359764410 | 359539842 | 0 | 0 |
gen_flops.OutputDelay_A | 179882205 | 179764854 | 0 | 1890 |
gen_no_flops.OutputDelay_A | 179882205 | 179769921 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1260 | 1260 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T11 | 6 | 6 | 0 | 0 |
T26 | 6 | 6 | 0 | 0 |
T27 | 6 | 6 | 0 | 0 |
T40 | 6 | 6 | 0 | 0 |
T41 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 359764410 | 359539842 | 0 | 0 |
T1 | 5817624 | 5817156 | 0 | 0 |
T2 | 973722 | 973308 | 0 | 0 |
T3 | 256524 | 256194 | 0 | 0 |
T4 | 169164 | 168336 | 0 | 0 |
T7 | 175074 | 174750 | 0 | 0 |
T11 | 4087242 | 4086906 | 0 | 0 |
T26 | 4866498 | 4863414 | 0 | 0 |
T27 | 1206030 | 1202094 | 0 | 0 |
T40 | 455850 | 455550 | 0 | 0 |
T41 | 1600620 | 1600170 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 179882205 | 179764854 | 0 | 1890 |
T1 | 2908812 | 2908569 | 0 | 9 |
T2 | 486861 | 486645 | 0 | 9 |
T3 | 128262 | 128088 | 0 | 9 |
T4 | 84582 | 84150 | 0 | 9 |
T7 | 87537 | 87366 | 0 | 9 |
T11 | 2043621 | 2043444 | 0 | 9 |
T26 | 2433249 | 2431644 | 0 | 9 |
T27 | 603015 | 600957 | 0 | 9 |
T40 | 227925 | 227766 | 0 | 9 |
T41 | 800310 | 800076 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 179882205 | 179769921 | 0 | 0 |
T1 | 2908812 | 2908578 | 0 | 0 |
T2 | 486861 | 486654 | 0 | 0 |
T3 | 128262 | 128097 | 0 | 0 |
T4 | 84582 | 84168 | 0 | 0 |
T7 | 87537 | 87375 | 0 | 0 |
T11 | 2043621 | 2043453 | 0 | 0 |
T26 | 2433249 | 2431707 | 0 | 0 |
T27 | 603015 | 601047 | 0 | 0 |
T40 | 227925 | 227775 | 0 | 0 |
T41 | 800310 | 800085 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 210 | 210 | 0 | 0 |
OutputsKnown_A | 59960735 | 59923307 | 0 | 0 |
gen_flops.OutputDelay_A | 59960735 | 59921618 | 0 | 630 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 210 | 210 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 59960735 | 59923307 | 0 | 0 |
T1 | 969604 | 969526 | 0 | 0 |
T2 | 162287 | 162218 | 0 | 0 |
T3 | 42754 | 42699 | 0 | 0 |
T4 | 28194 | 28056 | 0 | 0 |
T7 | 29179 | 29125 | 0 | 0 |
T11 | 681207 | 681151 | 0 | 0 |
T26 | 811083 | 810569 | 0 | 0 |
T27 | 201005 | 200349 | 0 | 0 |
T40 | 75975 | 75925 | 0 | 0 |
T41 | 266770 | 266695 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 59960735 | 59921618 | 0 | 630 |
T1 | 969604 | 969523 | 0 | 3 |
T2 | 162287 | 162215 | 0 | 3 |
T3 | 42754 | 42696 | 0 | 3 |
T4 | 28194 | 28050 | 0 | 3 |
T7 | 29179 | 29122 | 0 | 3 |
T11 | 681207 | 681148 | 0 | 3 |
T26 | 811083 | 810548 | 0 | 3 |
T27 | 201005 | 200319 | 0 | 3 |
T40 | 75975 | 75922 | 0 | 3 |
T41 | 266770 | 266692 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 210 | 210 | 0 | 0 |
OutputsKnown_A | 59960735 | 59923307 | 0 | 0 |
gen_flops.OutputDelay_A | 59960735 | 59921618 | 0 | 630 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 210 | 210 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 59960735 | 59923307 | 0 | 0 |
T1 | 969604 | 969526 | 0 | 0 |
T2 | 162287 | 162218 | 0 | 0 |
T3 | 42754 | 42699 | 0 | 0 |
T4 | 28194 | 28056 | 0 | 0 |
T7 | 29179 | 29125 | 0 | 0 |
T11 | 681207 | 681151 | 0 | 0 |
T26 | 811083 | 810569 | 0 | 0 |
T27 | 201005 | 200349 | 0 | 0 |
T40 | 75975 | 75925 | 0 | 0 |
T41 | 266770 | 266695 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 59960735 | 59921618 | 0 | 630 |
T1 | 969604 | 969523 | 0 | 3 |
T2 | 162287 | 162215 | 0 | 3 |
T3 | 42754 | 42696 | 0 | 3 |
T4 | 28194 | 28050 | 0 | 3 |
T7 | 29179 | 29122 | 0 | 3 |
T11 | 681207 | 681148 | 0 | 3 |
T26 | 811083 | 810548 | 0 | 3 |
T27 | 201005 | 200319 | 0 | 3 |
T40 | 75975 | 75922 | 0 | 3 |
T41 | 266770 | 266692 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 210 | 210 | 0 | 0 |
OutputsKnown_A | 59960735 | 59923307 | 0 | 0 |
gen_no_flops.OutputDelay_A | 59960735 | 59923307 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 210 | 210 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 59960735 | 59923307 | 0 | 0 |
T1 | 969604 | 969526 | 0 | 0 |
T2 | 162287 | 162218 | 0 | 0 |
T3 | 42754 | 42699 | 0 | 0 |
T4 | 28194 | 28056 | 0 | 0 |
T7 | 29179 | 29125 | 0 | 0 |
T11 | 681207 | 681151 | 0 | 0 |
T26 | 811083 | 810569 | 0 | 0 |
T27 | 201005 | 200349 | 0 | 0 |
T40 | 75975 | 75925 | 0 | 0 |
T41 | 266770 | 266695 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 59960735 | 59923307 | 0 | 0 |
T1 | 969604 | 969526 | 0 | 0 |
T2 | 162287 | 162218 | 0 | 0 |
T3 | 42754 | 42699 | 0 | 0 |
T4 | 28194 | 28056 | 0 | 0 |
T7 | 29179 | 29125 | 0 | 0 |
T11 | 681207 | 681151 | 0 | 0 |
T26 | 811083 | 810569 | 0 | 0 |
T27 | 201005 | 200349 | 0 | 0 |
T40 | 75975 | 75925 | 0 | 0 |
T41 | 266770 | 266695 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 210 | 210 | 0 | 0 |
OutputsKnown_A | 59960735 | 59923307 | 0 | 0 |
gen_flops.OutputDelay_A | 59960735 | 59921618 | 0 | 630 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 210 | 210 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 59960735 | 59923307 | 0 | 0 |
T1 | 969604 | 969526 | 0 | 0 |
T2 | 162287 | 162218 | 0 | 0 |
T3 | 42754 | 42699 | 0 | 0 |
T4 | 28194 | 28056 | 0 | 0 |
T7 | 29179 | 29125 | 0 | 0 |
T11 | 681207 | 681151 | 0 | 0 |
T26 | 811083 | 810569 | 0 | 0 |
T27 | 201005 | 200349 | 0 | 0 |
T40 | 75975 | 75925 | 0 | 0 |
T41 | 266770 | 266695 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 59960735 | 59921618 | 0 | 630 |
T1 | 969604 | 969523 | 0 | 3 |
T2 | 162287 | 162215 | 0 | 3 |
T3 | 42754 | 42696 | 0 | 3 |
T4 | 28194 | 28050 | 0 | 3 |
T7 | 29179 | 29122 | 0 | 3 |
T11 | 681207 | 681148 | 0 | 3 |
T26 | 811083 | 810548 | 0 | 3 |
T27 | 201005 | 200319 | 0 | 3 |
T40 | 75975 | 75922 | 0 | 3 |
T41 | 266770 | 266692 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 210 | 210 | 0 | 0 |
OutputsKnown_A | 59960735 | 59923307 | 0 | 0 |
gen_no_flops.OutputDelay_A | 59960735 | 59923307 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 210 | 210 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 59960735 | 59923307 | 0 | 0 |
T1 | 969604 | 969526 | 0 | 0 |
T2 | 162287 | 162218 | 0 | 0 |
T3 | 42754 | 42699 | 0 | 0 |
T4 | 28194 | 28056 | 0 | 0 |
T7 | 29179 | 29125 | 0 | 0 |
T11 | 681207 | 681151 | 0 | 0 |
T26 | 811083 | 810569 | 0 | 0 |
T27 | 201005 | 200349 | 0 | 0 |
T40 | 75975 | 75925 | 0 | 0 |
T41 | 266770 | 266695 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 59960735 | 59923307 | 0 | 0 |
T1 | 969604 | 969526 | 0 | 0 |
T2 | 162287 | 162218 | 0 | 0 |
T3 | 42754 | 42699 | 0 | 0 |
T4 | 28194 | 28056 | 0 | 0 |
T7 | 29179 | 29125 | 0 | 0 |
T11 | 681207 | 681151 | 0 | 0 |
T26 | 811083 | 810569 | 0 | 0 |
T27 | 201005 | 200349 | 0 | 0 |
T40 | 75975 | 75925 | 0 | 0 |
T41 | 266770 | 266695 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 210 | 210 | 0 | 0 |
OutputsKnown_A | 59960735 | 59923307 | 0 | 0 |
gen_no_flops.OutputDelay_A | 59960735 | 59923307 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 210 | 210 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 59960735 | 59923307 | 0 | 0 |
T1 | 969604 | 969526 | 0 | 0 |
T2 | 162287 | 162218 | 0 | 0 |
T3 | 42754 | 42699 | 0 | 0 |
T4 | 28194 | 28056 | 0 | 0 |
T7 | 29179 | 29125 | 0 | 0 |
T11 | 681207 | 681151 | 0 | 0 |
T26 | 811083 | 810569 | 0 | 0 |
T27 | 201005 | 200349 | 0 | 0 |
T40 | 75975 | 75925 | 0 | 0 |
T41 | 266770 | 266695 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 59960735 | 59923307 | 0 | 0 |
T1 | 969604 | 969526 | 0 | 0 |
T2 | 162287 | 162218 | 0 | 0 |
T3 | 42754 | 42699 | 0 | 0 |
T4 | 28194 | 28056 | 0 | 0 |
T7 | 29179 | 29125 | 0 | 0 |
T11 | 681207 | 681151 | 0 | 0 |
T26 | 811083 | 810569 | 0 | 0 |
T27 | 201005 | 200349 | 0 | 0 |
T40 | 75975 | 75925 | 0 | 0 |
T41 | 266770 | 266695 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |