SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
82.07 | 95.57 | 79.86 | 89.42 | 74.36 | 86.00 | 98.21 | 51.03 |
T86 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1930136996 | Jul 09 06:42:34 PM PDT 24 | Jul 09 06:42:40 PM PDT 24 | 192106650 ps | ||
T79 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1571227722 | Jul 09 06:41:56 PM PDT 24 | Jul 09 06:41:59 PM PDT 24 | 614507590 ps | ||
T304 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3827717902 | Jul 09 06:41:36 PM PDT 24 | Jul 09 06:41:38 PM PDT 24 | 954898291 ps | ||
T305 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1814578146 | Jul 09 06:40:53 PM PDT 24 | Jul 09 06:41:30 PM PDT 24 | 12602779989 ps | ||
T306 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.514799460 | Jul 09 06:42:32 PM PDT 24 | Jul 09 06:42:36 PM PDT 24 | 732160712 ps | ||
T101 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4236145178 | Jul 09 06:42:37 PM PDT 24 | Jul 09 06:42:49 PM PDT 24 | 1143289414 ps | ||
T307 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2066794099 | Jul 09 06:41:46 PM PDT 24 | Jul 09 06:42:14 PM PDT 24 | 35938940926 ps | ||
T87 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.852730159 | Jul 09 06:42:17 PM PDT 24 | Jul 09 06:42:24 PM PDT 24 | 219804285 ps | ||
T308 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2143838676 | Jul 09 06:41:39 PM PDT 24 | Jul 09 06:42:06 PM PDT 24 | 47120566589 ps | ||
T50 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2598604709 | Jul 09 06:41:19 PM PDT 24 | Jul 09 06:42:21 PM PDT 24 | 20941199888 ps | ||
T135 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3617307159 | Jul 09 06:41:21 PM PDT 24 | Jul 09 06:41:33 PM PDT 24 | 4991403573 ps | ||
T309 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2020544332 | Jul 09 06:41:57 PM PDT 24 | Jul 09 06:42:01 PM PDT 24 | 1019102455 ps | ||
T310 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4018834677 | Jul 09 06:42:10 PM PDT 24 | Jul 09 06:42:13 PM PDT 24 | 526586391 ps | ||
T88 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2377021358 | Jul 09 06:40:37 PM PDT 24 | Jul 09 06:40:43 PM PDT 24 | 379084369 ps | ||
T136 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.811261374 | Jul 09 06:41:56 PM PDT 24 | Jul 09 06:42:07 PM PDT 24 | 2369706204 ps | ||
T311 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3574751496 | Jul 09 06:41:08 PM PDT 24 | Jul 09 06:41:10 PM PDT 24 | 779374589 ps | ||
T312 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1116444447 | Jul 09 06:41:22 PM PDT 24 | Jul 09 06:41:24 PM PDT 24 | 232533061 ps | ||
T313 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.992668952 | Jul 09 06:42:38 PM PDT 24 | Jul 09 06:42:57 PM PDT 24 | 13564471776 ps | ||
T100 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1034104668 | Jul 09 06:42:13 PM PDT 24 | Jul 09 06:42:16 PM PDT 24 | 163977519 ps | ||
T314 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3847262361 | Jul 09 06:40:52 PM PDT 24 | Jul 09 06:41:09 PM PDT 24 | 7270958085 ps | ||
T107 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1359138335 | Jul 09 06:40:41 PM PDT 24 | Jul 09 06:41:09 PM PDT 24 | 3563962490 ps | ||
T315 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.612943405 | Jul 09 06:41:16 PM PDT 24 | Jul 09 06:41:18 PM PDT 24 | 49867614 ps | ||
T102 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.356806715 | Jul 09 06:42:05 PM PDT 24 | Jul 09 06:42:15 PM PDT 24 | 3365286314 ps | ||
T137 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4233306282 | Jul 09 06:41:55 PM PDT 24 | Jul 09 06:42:07 PM PDT 24 | 964251251 ps | ||
T138 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.546407431 | Jul 09 06:42:34 PM PDT 24 | Jul 09 06:42:39 PM PDT 24 | 281987558 ps | ||
T108 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1887072906 | Jul 09 06:41:03 PM PDT 24 | Jul 09 06:41:07 PM PDT 24 | 232337944 ps | ||
T316 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1461374073 | Jul 09 06:42:26 PM PDT 24 | Jul 09 06:42:28 PM PDT 24 | 253787005 ps | ||
T317 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1030136674 | Jul 09 06:41:24 PM PDT 24 | Jul 09 06:41:26 PM PDT 24 | 632616889 ps | ||
T318 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.682101403 | Jul 09 06:42:06 PM PDT 24 | Jul 09 06:42:09 PM PDT 24 | 3049179384 ps | ||
T139 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3936915790 | Jul 09 06:42:02 PM PDT 24 | Jul 09 06:42:14 PM PDT 24 | 2028164046 ps | ||
T109 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1543634237 | Jul 09 06:41:26 PM PDT 24 | Jul 09 06:42:41 PM PDT 24 | 8581723911 ps | ||
T319 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2212505229 | Jul 09 06:41:56 PM PDT 24 | Jul 09 06:42:41 PM PDT 24 | 43543998703 ps | ||
T320 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1735883156 | Jul 09 06:42:23 PM PDT 24 | Jul 09 06:42:26 PM PDT 24 | 582594577 ps | ||
T110 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2295485176 | Jul 09 06:41:25 PM PDT 24 | Jul 09 06:41:33 PM PDT 24 | 186356525 ps | ||
T103 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.932050445 | Jul 09 06:40:37 PM PDT 24 | Jul 09 06:40:45 PM PDT 24 | 7514997411 ps | ||
T117 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1213010835 | Jul 09 06:41:56 PM PDT 24 | Jul 09 06:41:59 PM PDT 24 | 104852481 ps | ||
T321 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1384432511 | Jul 09 06:42:14 PM PDT 24 | Jul 09 06:42:37 PM PDT 24 | 13216818436 ps | ||
T322 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1059055278 | Jul 09 06:42:12 PM PDT 24 | Jul 09 06:42:19 PM PDT 24 | 555726276 ps | ||
T323 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3636685132 | Jul 09 06:41:15 PM PDT 24 | Jul 09 06:41:47 PM PDT 24 | 11757864532 ps | ||
T324 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.241745237 | Jul 09 06:42:17 PM PDT 24 | Jul 09 06:43:08 PM PDT 24 | 17260444395 ps | ||
T325 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2060335817 | Jul 09 06:41:35 PM PDT 24 | Jul 09 06:41:37 PM PDT 24 | 33475222 ps | ||
T326 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3049796949 | Jul 09 06:41:56 PM PDT 24 | Jul 09 06:42:02 PM PDT 24 | 4343343784 ps | ||
T118 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1203529251 | Jul 09 06:40:37 PM PDT 24 | Jul 09 06:40:41 PM PDT 24 | 397609175 ps | ||
T180 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3981872764 | Jul 09 06:41:11 PM PDT 24 | Jul 09 06:41:34 PM PDT 24 | 3165610064 ps | ||
T327 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1419243549 | Jul 09 06:41:13 PM PDT 24 | Jul 09 06:41:20 PM PDT 24 | 5248195046 ps | ||
T328 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4282732762 | Jul 09 06:41:25 PM PDT 24 | Jul 09 06:41:32 PM PDT 24 | 2096568634 ps | ||
T119 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2495423995 | Jul 09 06:41:04 PM PDT 24 | Jul 09 06:41:36 PM PDT 24 | 2142783437 ps | ||
T131 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2283576628 | Jul 09 06:41:15 PM PDT 24 | Jul 09 06:41:18 PM PDT 24 | 85764877 ps | ||
T132 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1172475458 | Jul 09 06:41:27 PM PDT 24 | Jul 09 06:41:30 PM PDT 24 | 165605883 ps | ||
T188 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.787227864 | Jul 09 06:41:56 PM PDT 24 | Jul 09 06:42:36 PM PDT 24 | 44086908281 ps | ||
T329 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.593201809 | Jul 09 06:42:35 PM PDT 24 | Jul 09 06:43:02 PM PDT 24 | 8990612838 ps | ||
T330 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1693407553 | Jul 09 06:42:14 PM PDT 24 | Jul 09 06:42:18 PM PDT 24 | 2456943270 ps | ||
T331 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.635460586 | Jul 09 06:40:37 PM PDT 24 | Jul 09 06:40:44 PM PDT 24 | 1569984082 ps | ||
T332 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2748744439 | Jul 09 06:41:55 PM PDT 24 | Jul 09 06:41:58 PM PDT 24 | 293454038 ps | ||
T184 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3076448565 | Jul 09 06:42:22 PM PDT 24 | Jul 09 06:42:34 PM PDT 24 | 879929718 ps | ||
T333 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3433590020 | Jul 09 06:40:34 PM PDT 24 | Jul 09 06:40:36 PM PDT 24 | 222225587 ps | ||
T334 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2381908014 | Jul 09 06:42:12 PM PDT 24 | Jul 09 06:42:14 PM PDT 24 | 254079296 ps | ||
T335 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.633301043 | Jul 09 06:41:45 PM PDT 24 | Jul 09 06:41:49 PM PDT 24 | 2845255138 ps | ||
T126 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3266943338 | Jul 09 06:41:08 PM PDT 24 | Jul 09 06:41:12 PM PDT 24 | 418829863 ps | ||
T336 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2482681868 | Jul 09 06:41:19 PM PDT 24 | Jul 09 06:41:26 PM PDT 24 | 1124781743 ps | ||
T337 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2239231349 | Jul 09 06:41:25 PM PDT 24 | Jul 09 06:42:35 PM PDT 24 | 14887360211 ps | ||
T338 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2212564230 | Jul 09 06:41:19 PM PDT 24 | Jul 09 06:41:27 PM PDT 24 | 7978690186 ps | ||
T339 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3246476525 | Jul 09 06:42:24 PM PDT 24 | Jul 09 06:42:30 PM PDT 24 | 264823571 ps | ||
T127 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.594114554 | Jul 09 06:42:17 PM PDT 24 | Jul 09 06:42:25 PM PDT 24 | 209212325 ps | ||
T340 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.4033016917 | Jul 09 06:42:22 PM PDT 24 | Jul 09 06:42:57 PM PDT 24 | 13275928113 ps | ||
T104 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3443853551 | Jul 09 06:40:48 PM PDT 24 | Jul 09 06:40:53 PM PDT 24 | 2372155672 ps | ||
T341 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3205683653 | Jul 09 06:41:31 PM PDT 24 | Jul 09 06:42:24 PM PDT 24 | 21315387792 ps | ||
T187 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.465297316 | Jul 09 06:40:37 PM PDT 24 | Jul 09 06:41:06 PM PDT 24 | 33684854748 ps | ||
T342 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.975699072 | Jul 09 06:41:22 PM PDT 24 | Jul 09 06:41:57 PM PDT 24 | 22123923143 ps | ||
T343 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1119146000 | Jul 09 06:42:31 PM PDT 24 | Jul 09 06:43:27 PM PDT 24 | 79665986034 ps | ||
T183 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.920610080 | Jul 09 06:42:32 PM PDT 24 | Jul 09 06:42:54 PM PDT 24 | 2725412217 ps | ||
T344 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3156486091 | Jul 09 06:42:06 PM PDT 24 | Jul 09 06:42:18 PM PDT 24 | 2360004624 ps | ||
T345 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2353450727 | Jul 09 06:42:11 PM PDT 24 | Jul 09 06:42:14 PM PDT 24 | 164306483 ps | ||
T346 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3463686525 | Jul 09 06:42:29 PM PDT 24 | Jul 09 06:42:51 PM PDT 24 | 23563599702 ps | ||
T181 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3856355782 | Jul 09 06:42:12 PM PDT 24 | Jul 09 06:42:32 PM PDT 24 | 2233925005 ps | ||
T347 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3823047099 | Jul 09 06:41:45 PM PDT 24 | Jul 09 06:42:12 PM PDT 24 | 9499613333 ps | ||
T348 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.541246701 | Jul 09 06:41:52 PM PDT 24 | Jul 09 06:41:54 PM PDT 24 | 116415728 ps | ||
T349 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.22218127 | Jul 09 06:42:17 PM PDT 24 | Jul 09 06:42:20 PM PDT 24 | 226413248 ps | ||
T350 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.145254662 | Jul 09 06:42:33 PM PDT 24 | Jul 09 06:42:36 PM PDT 24 | 307510137 ps | ||
T351 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3492028356 | Jul 09 06:41:14 PM PDT 24 | Jul 09 06:41:17 PM PDT 24 | 293505377 ps | ||
T352 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.178769331 | Jul 09 06:41:51 PM PDT 24 | Jul 09 06:41:55 PM PDT 24 | 336326344 ps | ||
T353 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.213352491 | Jul 09 06:40:43 PM PDT 24 | Jul 09 06:40:50 PM PDT 24 | 5199567448 ps | ||
T128 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.973335549 | Jul 09 06:42:21 PM PDT 24 | Jul 09 06:42:29 PM PDT 24 | 362812056 ps | ||
T354 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3707861786 | Jul 09 06:42:05 PM PDT 24 | Jul 09 06:42:10 PM PDT 24 | 664144717 ps | ||
T355 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3016245338 | Jul 09 06:41:08 PM PDT 24 | Jul 09 06:41:10 PM PDT 24 | 123793009 ps | ||
T356 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1022453232 | Jul 09 06:40:38 PM PDT 24 | Jul 09 06:40:46 PM PDT 24 | 2611800121 ps | ||
T105 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.880280268 | Jul 09 06:41:19 PM PDT 24 | Jul 09 06:41:32 PM PDT 24 | 6775771566 ps | ||
T111 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.984518752 | Jul 09 06:41:40 PM PDT 24 | Jul 09 06:41:47 PM PDT 24 | 743676256 ps | ||
T120 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.642751235 | Jul 09 06:41:36 PM PDT 24 | Jul 09 06:42:10 PM PDT 24 | 5980497265 ps | ||
T121 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.492778613 | Jul 09 06:41:15 PM PDT 24 | Jul 09 06:41:45 PM PDT 24 | 716682249 ps | ||
T129 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1391346333 | Jul 09 06:42:18 PM PDT 24 | Jul 09 06:42:28 PM PDT 24 | 1114813921 ps | ||
T357 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.371771520 | Jul 09 06:41:20 PM PDT 24 | Jul 09 06:41:35 PM PDT 24 | 5463604239 ps | ||
T130 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1139654029 | Jul 09 06:41:50 PM PDT 24 | Jul 09 06:41:56 PM PDT 24 | 162054860 ps | ||
T358 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2305829961 | Jul 09 06:40:39 PM PDT 24 | Jul 09 06:40:42 PM PDT 24 | 445687530 ps | ||
T359 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.192460788 | Jul 09 06:40:39 PM PDT 24 | Jul 09 06:40:41 PM PDT 24 | 48624762 ps | ||
T112 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.910457546 | Jul 09 06:42:33 PM PDT 24 | Jul 09 06:42:42 PM PDT 24 | 992499920 ps | ||
T113 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3535570760 | Jul 09 06:41:26 PM PDT 24 | Jul 09 06:41:30 PM PDT 24 | 619061712 ps | ||
T360 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2561831248 | Jul 09 06:41:10 PM PDT 24 | Jul 09 06:43:40 PM PDT 24 | 61186351051 ps | ||
T361 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4100962230 | Jul 09 06:41:36 PM PDT 24 | Jul 09 06:41:40 PM PDT 24 | 412504462 ps | ||
T362 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.452493133 | Jul 09 06:42:13 PM PDT 24 | Jul 09 06:42:33 PM PDT 24 | 13777847182 ps | ||
T122 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3779101487 | Jul 09 06:40:58 PM PDT 24 | Jul 09 06:42:17 PM PDT 24 | 42043560703 ps | ||
T363 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1563643377 | Jul 09 06:41:35 PM PDT 24 | Jul 09 06:41:38 PM PDT 24 | 130691092 ps | ||
T123 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.406116264 | Jul 09 06:42:18 PM PDT 24 | Jul 09 06:42:21 PM PDT 24 | 1153087165 ps | ||
T364 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.295503387 | Jul 09 06:42:34 PM PDT 24 | Jul 09 06:42:36 PM PDT 24 | 80412447 ps | ||
T365 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1254970126 | Jul 09 06:41:50 PM PDT 24 | Jul 09 06:41:53 PM PDT 24 | 366358057 ps | ||
T366 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3672189123 | Jul 09 06:41:47 PM PDT 24 | Jul 09 06:41:51 PM PDT 24 | 527165404 ps | ||
T367 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.877429014 | Jul 09 06:41:34 PM PDT 24 | Jul 09 06:41:39 PM PDT 24 | 4043030412 ps | ||
T368 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1557555519 | Jul 09 06:42:27 PM PDT 24 | Jul 09 06:42:36 PM PDT 24 | 7690099717 ps | ||
T369 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1671348301 | Jul 09 06:40:47 PM PDT 24 | Jul 09 06:41:03 PM PDT 24 | 33869591020 ps | ||
T370 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2607367301 | Jul 09 06:41:45 PM PDT 24 | Jul 09 06:43:08 PM PDT 24 | 46254090437 ps | ||
T371 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1943813330 | Jul 09 06:41:52 PM PDT 24 | Jul 09 06:44:00 PM PDT 24 | 48269264097 ps | ||
T372 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.398175375 | Jul 09 06:41:45 PM PDT 24 | Jul 09 06:41:48 PM PDT 24 | 331306528 ps | ||
T106 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3448560105 | Jul 09 06:41:29 PM PDT 24 | Jul 09 06:41:37 PM PDT 24 | 2285608916 ps | ||
T373 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1409665973 | Jul 09 06:42:05 PM PDT 24 | Jul 09 06:42:11 PM PDT 24 | 3956122142 ps | ||
T374 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.4264452802 | Jul 09 06:40:47 PM PDT 24 | Jul 09 06:40:49 PM PDT 24 | 328587683 ps | ||
T124 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2083258792 | Jul 09 06:42:35 PM PDT 24 | Jul 09 06:42:38 PM PDT 24 | 349679025 ps | ||
T375 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.4156620275 | Jul 09 06:42:23 PM PDT 24 | Jul 09 06:42:33 PM PDT 24 | 600640476 ps | ||
T376 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1559169759 | Jul 09 06:42:16 PM PDT 24 | Jul 09 06:42:22 PM PDT 24 | 2330574249 ps | ||
T377 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.738402176 | Jul 09 06:41:45 PM PDT 24 | Jul 09 06:41:50 PM PDT 24 | 341662792 ps | ||
T378 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1211098365 | Jul 09 06:42:14 PM PDT 24 | Jul 09 06:42:18 PM PDT 24 | 3423217476 ps | ||
T379 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2935642021 | Jul 09 06:42:35 PM PDT 24 | Jul 09 06:42:44 PM PDT 24 | 7825843120 ps | ||
T380 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.660230642 | Jul 09 06:42:12 PM PDT 24 | Jul 09 06:42:18 PM PDT 24 | 7144882170 ps | ||
T381 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.995545647 | Jul 09 06:40:37 PM PDT 24 | Jul 09 06:40:47 PM PDT 24 | 2193215049 ps | ||
T382 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3099807453 | Jul 09 06:41:02 PM PDT 24 | Jul 09 06:41:09 PM PDT 24 | 1174459857 ps | ||
T383 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.917039199 | Jul 09 06:42:21 PM PDT 24 | Jul 09 06:42:25 PM PDT 24 | 333518158 ps | ||
T125 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2389491672 | Jul 09 06:42:21 PM PDT 24 | Jul 09 06:42:25 PM PDT 24 | 103481392 ps | ||
T384 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.463328843 | Jul 09 06:42:21 PM PDT 24 | Jul 09 06:42:27 PM PDT 24 | 2473904067 ps | ||
T385 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2980822228 | Jul 09 06:42:17 PM PDT 24 | Jul 09 06:42:23 PM PDT 24 | 393199476 ps | ||
T386 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3640635452 | Jul 09 06:40:48 PM PDT 24 | Jul 09 06:40:50 PM PDT 24 | 720467583 ps | ||
T182 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.4069678184 | Jul 09 06:42:11 PM PDT 24 | Jul 09 06:42:35 PM PDT 24 | 12199903053 ps | ||
T387 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2014703084 | Jul 09 06:41:15 PM PDT 24 | Jul 09 06:41:21 PM PDT 24 | 596071531 ps | ||
T388 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1136049217 | Jul 09 06:41:39 PM PDT 24 | Jul 09 06:41:44 PM PDT 24 | 213774218 ps | ||
T389 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4178313784 | Jul 09 06:41:25 PM PDT 24 | Jul 09 06:41:27 PM PDT 24 | 105420346 ps | ||
T390 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.892161758 | Jul 09 06:41:45 PM PDT 24 | Jul 09 06:41:53 PM PDT 24 | 323879978 ps | ||
T391 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.353852314 | Jul 09 06:42:01 PM PDT 24 | Jul 09 06:42:05 PM PDT 24 | 61781508 ps | ||
T392 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3753029 | Jul 09 06:42:23 PM PDT 24 | Jul 09 06:42:27 PM PDT 24 | 158945959 ps | ||
T393 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3302506834 | Jul 09 06:41:49 PM PDT 24 | Jul 09 06:41:54 PM PDT 24 | 211344087 ps | ||
T394 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.4227552256 | Jul 09 06:41:13 PM PDT 24 | Jul 09 06:41:16 PM PDT 24 | 151417742 ps | ||
T395 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1671340529 | Jul 09 06:42:21 PM PDT 24 | Jul 09 06:42:32 PM PDT 24 | 628677054 ps | ||
T396 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.137435299 | Jul 09 06:41:49 PM PDT 24 | Jul 09 06:41:55 PM PDT 24 | 1376793099 ps | ||
T397 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4100972516 | Jul 09 06:41:35 PM PDT 24 | Jul 09 06:41:57 PM PDT 24 | 7765458764 ps | ||
T398 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3673933198 | Jul 09 06:42:27 PM PDT 24 | Jul 09 06:42:31 PM PDT 24 | 545805098 ps | ||
T399 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.801424751 | Jul 09 06:42:12 PM PDT 24 | Jul 09 06:42:17 PM PDT 24 | 305110185 ps | ||
T400 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2581412749 | Jul 09 06:41:07 PM PDT 24 | Jul 09 06:41:10 PM PDT 24 | 85273185 ps | ||
T401 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2055354118 | Jul 09 06:41:45 PM PDT 24 | Jul 09 06:41:48 PM PDT 24 | 102914867 ps | ||
T402 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3310767941 | Jul 09 06:41:46 PM PDT 24 | Jul 09 06:41:50 PM PDT 24 | 110368010 ps | ||
T403 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2508322415 | Jul 09 06:41:09 PM PDT 24 | Jul 09 06:41:55 PM PDT 24 | 16171649786 ps | ||
T404 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1968501928 | Jul 09 06:40:54 PM PDT 24 | Jul 09 06:40:59 PM PDT 24 | 310108397 ps | ||
T405 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2184965583 | Jul 09 06:41:14 PM PDT 24 | Jul 09 06:41:17 PM PDT 24 | 56751707 ps | ||
T406 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.44132198 | Jul 09 06:40:59 PM PDT 24 | Jul 09 06:41:00 PM PDT 24 | 79059624 ps | ||
T407 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3186597810 | Jul 09 06:41:16 PM PDT 24 | Jul 09 06:41:20 PM PDT 24 | 453387559 ps | ||
T408 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4070738762 | Jul 09 06:42:27 PM PDT 24 | Jul 09 06:42:36 PM PDT 24 | 2484442377 ps | ||
T409 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.292444078 | Jul 09 06:40:43 PM PDT 24 | Jul 09 06:40:47 PM PDT 24 | 155028884 ps | ||
T410 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4045772187 | Jul 09 06:42:37 PM PDT 24 | Jul 09 06:42:40 PM PDT 24 | 221212256 ps | ||
T411 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3329558738 | Jul 09 06:41:41 PM PDT 24 | Jul 09 06:41:44 PM PDT 24 | 139722479 ps | ||
T412 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1698850848 | Jul 09 06:41:24 PM PDT 24 | Jul 09 06:41:27 PM PDT 24 | 541876775 ps | ||
T413 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2155570174 | Jul 09 06:41:21 PM PDT 24 | Jul 09 06:42:10 PM PDT 24 | 20405059800 ps | ||
T186 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3086393010 | Jul 09 06:42:17 PM PDT 24 | Jul 09 06:42:45 PM PDT 24 | 5412945057 ps | ||
T414 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3845974365 | Jul 09 06:41:51 PM PDT 24 | Jul 09 06:42:00 PM PDT 24 | 1237978830 ps | ||
T185 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4029622904 | Jul 09 06:40:53 PM PDT 24 | Jul 09 06:41:13 PM PDT 24 | 3987234928 ps | ||
T415 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.140393301 | Jul 09 06:42:00 PM PDT 24 | Jul 09 06:42:07 PM PDT 24 | 4647785944 ps | ||
T416 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2521382706 | Jul 09 06:41:29 PM PDT 24 | Jul 09 06:42:34 PM PDT 24 | 25691277153 ps | ||
T114 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1266654179 | Jul 09 06:42:31 PM PDT 24 | Jul 09 06:42:41 PM PDT 24 | 1048663454 ps | ||
T417 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.261525164 | Jul 09 06:41:54 PM PDT 24 | Jul 09 06:41:59 PM PDT 24 | 178051978 ps | ||
T418 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2439681274 | Jul 09 06:41:35 PM PDT 24 | Jul 09 06:41:39 PM PDT 24 | 250512480 ps | ||
T115 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4163013545 | Jul 09 06:42:07 PM PDT 24 | Jul 09 06:42:14 PM PDT 24 | 690052610 ps | ||
T419 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2582079883 | Jul 09 06:42:27 PM PDT 24 | Jul 09 06:42:37 PM PDT 24 | 2924189430 ps | ||
T420 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2751985403 | Jul 09 06:41:31 PM PDT 24 | Jul 09 06:45:02 PM PDT 24 | 133451420140 ps | ||
T421 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2018764165 | Jul 09 06:40:47 PM PDT 24 | Jul 09 06:40:50 PM PDT 24 | 931198443 ps | ||
T422 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1024610067 | Jul 09 06:42:25 PM PDT 24 | Jul 09 06:42:30 PM PDT 24 | 2376141703 ps | ||
T423 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.982907359 | Jul 09 06:41:10 PM PDT 24 | Jul 09 06:41:13 PM PDT 24 | 360607140 ps | ||
T179 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3755981183 | Jul 09 06:42:22 PM PDT 24 | Jul 09 06:42:27 PM PDT 24 | 912064295 ps | ||
T424 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3569080082 | Jul 09 06:41:41 PM PDT 24 | Jul 09 06:41:46 PM PDT 24 | 314829535 ps | ||
T116 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.407247948 | Jul 09 06:40:42 PM PDT 24 | Jul 09 06:40:49 PM PDT 24 | 761470565 ps | ||
T425 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.925275041 | Jul 09 06:41:09 PM PDT 24 | Jul 09 06:41:12 PM PDT 24 | 200125210 ps | ||
T426 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.457907320 | Jul 09 06:42:28 PM PDT 24 | Jul 09 06:42:32 PM PDT 24 | 450118328 ps | ||
T427 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4157023689 | Jul 09 06:40:34 PM PDT 24 | Jul 09 06:41:00 PM PDT 24 | 1169822123 ps | ||
T428 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3425718175 | Jul 09 06:40:38 PM PDT 24 | Jul 09 06:42:04 PM PDT 24 | 59126802929 ps | ||
T429 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2292754355 | Jul 09 06:40:38 PM PDT 24 | Jul 09 06:40:41 PM PDT 24 | 53174567 ps | ||
T430 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.375181941 | Jul 09 06:42:13 PM PDT 24 | Jul 09 06:42:22 PM PDT 24 | 980669394 ps | ||
T431 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2489404049 | Jul 09 06:42:00 PM PDT 24 | Jul 09 06:42:03 PM PDT 24 | 2249729292 ps | ||
T432 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2940664090 | Jul 09 06:42:02 PM PDT 24 | Jul 09 06:42:08 PM PDT 24 | 11452481582 ps | ||
T433 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.970107821 | Jul 09 06:41:35 PM PDT 24 | Jul 09 06:41:37 PM PDT 24 | 92535657 ps | ||
T434 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4026797244 | Jul 09 06:40:35 PM PDT 24 | Jul 09 06:41:18 PM PDT 24 | 15982850471 ps | ||
T435 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3533676405 | Jul 09 06:42:06 PM PDT 24 | Jul 09 06:42:08 PM PDT 24 | 94198504 ps | ||
T436 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2925821665 | Jul 09 06:41:32 PM PDT 24 | Jul 09 06:41:33 PM PDT 24 | 174936182 ps | ||
T437 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2942718548 | Jul 09 06:40:53 PM PDT 24 | Jul 09 06:41:12 PM PDT 24 | 21421238736 ps | ||
T438 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2185886368 | Jul 09 06:40:32 PM PDT 24 | Jul 09 06:40:34 PM PDT 24 | 414866354 ps | ||
T439 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4256632963 | Jul 09 06:41:09 PM PDT 24 | Jul 09 06:45:51 PM PDT 24 | 108260291283 ps | ||
T440 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1501654917 | Jul 09 06:41:11 PM PDT 24 | Jul 09 06:41:15 PM PDT 24 | 1080038408 ps | ||
T441 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1095984312 | Jul 09 06:42:10 PM PDT 24 | Jul 09 06:42:15 PM PDT 24 | 4781996734 ps |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.639811551 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 32154790175 ps |
CPU time | 84.86 seconds |
Started | Jul 09 06:43:23 PM PDT 24 |
Finished | Jul 09 06:44:52 PM PDT 24 |
Peak memory | 213952 kb |
Host | smart-5574ebef-081e-4a34-8586-edfbde141cf3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=639811551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.639811551 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/32.rv_dm_stress_all.1451817227 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 5819829451 ps |
CPU time | 8.63 seconds |
Started | Jul 09 06:43:41 PM PDT 24 |
Finished | Jul 09 06:43:51 PM PDT 24 |
Peak memory | 213824 kb |
Host | smart-666a4ca3-5010-45a2-aadb-b11aa1c3f943 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451817227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1451817227 |
Directory | /workspace/32.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.734422206 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 55472304510 ps |
CPU time | 161.72 seconds |
Started | Jul 09 06:44:12 PM PDT 24 |
Finished | Jul 09 06:46:54 PM PDT 24 |
Peak memory | 221976 kb |
Host | smart-5b128fdb-0db3-4fae-91da-1b33c3348f41 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734422206 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.734422206 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/35.rv_dm_stress_all.2921370694 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 3995896791 ps |
CPU time | 2.91 seconds |
Started | Jul 09 06:43:43 PM PDT 24 |
Finished | Jul 09 06:43:48 PM PDT 24 |
Peak memory | 214092 kb |
Host | smart-42578c83-081a-4577-a99d-1287f9c047cb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921370694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2921370694 |
Directory | /workspace/35.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.71771839 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 7328419573 ps |
CPU time | 72.24 seconds |
Started | Jul 09 06:41:08 PM PDT 24 |
Finished | Jul 09 06:42:22 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-89af29b6-2eaa-417a-b470-901a42998f83 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71771839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.71771839 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.1459049486 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 103677370 ps |
CPU time | 0.78 seconds |
Started | Jul 09 06:43:43 PM PDT 24 |
Finished | Jul 09 06:43:45 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-914db6f4-dae1-4fef-806a-1bf52a06049d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459049486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1459049486 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.688445647 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 2332911608 ps |
CPU time | 11.15 seconds |
Started | Jul 09 06:41:41 PM PDT 24 |
Finished | Jul 09 06:41:53 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-c36f9df2-6bda-48d2-b8fe-f56e23cf04f5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688445647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.688445647 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.475788421 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 45714874 ps |
CPU time | 0.85 seconds |
Started | Jul 09 06:42:45 PM PDT 24 |
Finished | Jul 09 06:42:46 PM PDT 24 |
Peak memory | 215416 kb |
Host | smart-50bd1de8-66ce-4049-ad12-29ed3f7ad283 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=475788421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.475788421 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.4052931308 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 8928600127 ps |
CPU time | 7.59 seconds |
Started | Jul 09 06:43:39 PM PDT 24 |
Finished | Jul 09 06:43:48 PM PDT 24 |
Peak memory | 213828 kb |
Host | smart-4572495f-412c-4035-bcd9-d3910a48f41a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052931308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.4052931308 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.918137390 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 1061674521 ps |
CPU time | 3.61 seconds |
Started | Jul 09 06:42:41 PM PDT 24 |
Finished | Jul 09 06:42:45 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-0c4fa021-fd4f-4836-8d0c-2bcd081c1b92 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918137390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.918137390 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1543634237 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 8581723911 ps |
CPU time | 73.61 seconds |
Started | Jul 09 06:41:26 PM PDT 24 |
Finished | Jul 09 06:42:41 PM PDT 24 |
Peak memory | 213332 kb |
Host | smart-e2a1c72f-ddfa-42b1-a60d-1fab7d161c94 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543634237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.1543634237 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.2000511698 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 1875897668 ps |
CPU time | 4.4 seconds |
Started | Jul 09 06:42:42 PM PDT 24 |
Finished | Jul 09 06:42:48 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-10f00635-4961-4066-8ae0-ac3945c5a139 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000511698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2000511698 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.1179431257 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 127621706 ps |
CPU time | 1.14 seconds |
Started | Jul 09 06:42:57 PM PDT 24 |
Finished | Jul 09 06:43:00 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-fd1f20c1-3901-4cfb-8825-c5f1b4767f4b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1179431257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1179431257 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.3448674804 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 432616715 ps |
CPU time | 2.09 seconds |
Started | Jul 09 06:43:06 PM PDT 24 |
Finished | Jul 09 06:43:09 PM PDT 24 |
Peak memory | 237228 kb |
Host | smart-e00c733a-3eef-489f-ab8e-a19f55ef1c8b |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448674804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3448674804 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all.1357772995 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 4011801035 ps |
CPU time | 4.62 seconds |
Started | Jul 09 06:42:59 PM PDT 24 |
Finished | Jul 09 06:43:06 PM PDT 24 |
Peak memory | 213756 kb |
Host | smart-5302c192-2008-4239-b0a1-8503cea82b44 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357772995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1357772995 |
Directory | /workspace/2.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.572041539 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 38278283543 ps |
CPU time | 32.13 seconds |
Started | Jul 09 06:43:22 PM PDT 24 |
Finished | Jul 09 06:43:58 PM PDT 24 |
Peak memory | 213816 kb |
Host | smart-e5eeb41c-0bee-44ea-85de-38cb9b9e1888 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572041539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.572041539 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/33.rv_dm_stress_all.851223816 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 9404410373 ps |
CPU time | 4.92 seconds |
Started | Jul 09 06:43:44 PM PDT 24 |
Finished | Jul 09 06:43:50 PM PDT 24 |
Peak memory | 213740 kb |
Host | smart-7cab1a21-8b7e-4522-b11b-204cc567ea07 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851223816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.851223816 |
Directory | /workspace/33.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1170484863 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 1563986420 ps |
CPU time | 3.38 seconds |
Started | Jul 09 06:43:27 PM PDT 24 |
Finished | Jul 09 06:43:33 PM PDT 24 |
Peak memory | 213840 kb |
Host | smart-96010757-50de-4ec0-88f4-0b6376171183 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1170484863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1170484863 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.351627440 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 83132750 ps |
CPU time | 0.81 seconds |
Started | Jul 09 06:42:45 PM PDT 24 |
Finished | Jul 09 06:42:46 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-3be897b1-f562-4d5d-afdf-08c7cb53eeaa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=351627440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.351627440 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.612461367 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 4246873837 ps |
CPU time | 4.03 seconds |
Started | Jul 09 06:42:55 PM PDT 24 |
Finished | Jul 09 06:43:01 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-252e9389-ab29-4f50-a559-d3e2440fc91f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612461367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.612461367 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.4040802489 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 935015715 ps |
CPU time | 2.11 seconds |
Started | Jul 09 06:42:55 PM PDT 24 |
Finished | Jul 09 06:42:59 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-e6a75fbb-8e02-48ed-93e1-d028729e1a01 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040802489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.4040802489 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3093822236 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 12619231708 ps |
CPU time | 11.73 seconds |
Started | Jul 09 06:43:14 PM PDT 24 |
Finished | Jul 09 06:43:27 PM PDT 24 |
Peak memory | 213936 kb |
Host | smart-7a3d46aa-b4bf-4e8f-93a9-6784c31544fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093822236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3093822236 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/31.rv_dm_stress_all.1624687575 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 12875757717 ps |
CPU time | 19.41 seconds |
Started | Jul 09 06:43:37 PM PDT 24 |
Finished | Jul 09 06:43:58 PM PDT 24 |
Peak memory | 205644 kb |
Host | smart-8869703a-801d-4b51-93a9-389c95bfd7bb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624687575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1624687575 |
Directory | /workspace/31.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_busy.1124103410 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 2001134351 ps |
CPU time | 3.63 seconds |
Started | Jul 09 06:42:57 PM PDT 24 |
Finished | Jul 09 06:43:03 PM PDT 24 |
Peak memory | 205548 kb |
Host | smart-ec27b939-836b-42e5-be44-e5fc903516d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1124103410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1124103410 |
Directory | /workspace/1.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.570021426 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 386385525 ps |
CPU time | 6.43 seconds |
Started | Jul 09 06:42:03 PM PDT 24 |
Finished | Jul 09 06:42:10 PM PDT 24 |
Peak memory | 205188 kb |
Host | smart-5abcec0f-ded5-41d9-93ed-59272f6165b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570021426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c sr_outstanding.570021426 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3856355782 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 2233925005 ps |
CPU time | 18.73 seconds |
Started | Jul 09 06:42:12 PM PDT 24 |
Finished | Jul 09 06:42:32 PM PDT 24 |
Peak memory | 213284 kb |
Host | smart-fd44d56f-56cc-45cf-811d-94e2cd81dd57 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856355782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3 856355782 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.738480094 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 3816284826 ps |
CPU time | 11.29 seconds |
Started | Jul 09 06:43:06 PM PDT 24 |
Finished | Jul 09 06:43:19 PM PDT 24 |
Peak memory | 213944 kb |
Host | smart-82811670-e21b-40c9-8ba9-d0b1c0f4119f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738480094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.738480094 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.920610080 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 2725412217 ps |
CPU time | 19.84 seconds |
Started | Jul 09 06:42:32 PM PDT 24 |
Finished | Jul 09 06:42:54 PM PDT 24 |
Peak memory | 213336 kb |
Host | smart-361256d1-4b9b-4229-9e18-4c418fdc5571 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920610080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.920610080 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.712315770 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 13059338965 ps |
CPU time | 11.09 seconds |
Started | Jul 09 06:43:17 PM PDT 24 |
Finished | Jul 09 06:43:31 PM PDT 24 |
Peak memory | 213828 kb |
Host | smart-f638eac9-853d-49af-bc7f-1062c99dc6f2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=712315770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.712315770 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1550027037 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 3989449973 ps |
CPU time | 12.61 seconds |
Started | Jul 09 06:43:28 PM PDT 24 |
Finished | Jul 09 06:43:43 PM PDT 24 |
Peak memory | 213864 kb |
Host | smart-ea774bf4-35f0-4832-969f-e95efb5f0a93 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550027037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1550027037 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.4035278555 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 20425124171 ps |
CPU time | 27.08 seconds |
Started | Jul 09 06:43:01 PM PDT 24 |
Finished | Jul 09 06:43:31 PM PDT 24 |
Peak memory | 218476 kb |
Host | smart-c48a1c27-f8a6-41bd-ba9a-28a4faa8e948 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4035278555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.4035278555 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1976391199 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 11503818451 ps |
CPU time | 4.8 seconds |
Started | Jul 09 06:43:08 PM PDT 24 |
Finished | Jul 09 06:43:14 PM PDT 24 |
Peak memory | 213904 kb |
Host | smart-faa82770-2638-46a9-9934-d93cbb3f25bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1976391199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1976391199 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_stress_all.223652594 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 3884963521 ps |
CPU time | 11.72 seconds |
Started | Jul 09 06:43:35 PM PDT 24 |
Finished | Jul 09 06:43:48 PM PDT 24 |
Peak memory | 213720 kb |
Host | smart-e361e20e-33d1-4e84-86e5-ff18adad1294 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223652594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.223652594 |
Directory | /workspace/18.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1912757793 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 556838969 ps |
CPU time | 1.2 seconds |
Started | Jul 09 06:42:01 PM PDT 24 |
Finished | Jul 09 06:42:04 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-7b1a93b5-0761-4d0d-b0c4-9d6b5444a72d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912757793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 1912757793 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.932050445 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 7514997411 ps |
CPU time | 6.17 seconds |
Started | Jul 09 06:40:37 PM PDT 24 |
Finished | Jul 09 06:40:45 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-f9159dd9-d249-40ed-850f-bad139457020 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932050445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr _hw_reset.932050445 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3076448565 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 879929718 ps |
CPU time | 10.15 seconds |
Started | Jul 09 06:42:22 PM PDT 24 |
Finished | Jul 09 06:42:34 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-f4773b50-3420-48c8-85e1-da402335bc95 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076448565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3 076448565 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.2470637862 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 166798308 ps |
CPU time | 0.85 seconds |
Started | Jul 09 06:42:59 PM PDT 24 |
Finished | Jul 09 06:43:02 PM PDT 24 |
Peak memory | 215680 kb |
Host | smart-5ac37d44-c437-47c4-b3ae-c6e97bc06af7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2470637862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2470637862 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/13.rv_dm_stress_all.2512896447 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 5414072459 ps |
CPU time | 5.39 seconds |
Started | Jul 09 06:43:24 PM PDT 24 |
Finished | Jul 09 06:43:33 PM PDT 24 |
Peak memory | 213744 kb |
Host | smart-81256369-b650-4303-9a74-b74f59278d06 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512896447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2512896447 |
Directory | /workspace/13.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_stress_all.1781289288 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 10387234827 ps |
CPU time | 5.38 seconds |
Started | Jul 09 06:43:28 PM PDT 24 |
Finished | Jul 09 06:43:36 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-3d92cbda-e5a0-4899-98d2-4f7daaf76643 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781289288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1781289288 |
Directory | /workspace/17.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/20.rv_dm_stress_all.4219198180 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 5592534084 ps |
CPU time | 8.07 seconds |
Started | Jul 09 06:43:33 PM PDT 24 |
Finished | Jul 09 06:43:42 PM PDT 24 |
Peak memory | 205560 kb |
Host | smart-82e876ca-be7d-472f-a245-5c4ff87223d1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219198180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.4219198180 |
Directory | /workspace/20.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.258843601 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 580453066 ps |
CPU time | 1.11 seconds |
Started | Jul 09 06:42:37 PM PDT 24 |
Finished | Jul 09 06:42:40 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-027ef9f1-cc8b-4b7b-8093-d40eb8598437 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=258843601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.258843601 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2377021358 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 379084369 ps |
CPU time | 4.74 seconds |
Started | Jul 09 06:40:37 PM PDT 24 |
Finished | Jul 09 06:40:43 PM PDT 24 |
Peak memory | 213256 kb |
Host | smart-02222cec-0ccd-43f2-9eda-f58186c8c4ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377021358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2377021358 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3617307159 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 4991403573 ps |
CPU time | 11.05 seconds |
Started | Jul 09 06:41:21 PM PDT 24 |
Finished | Jul 09 06:41:33 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-4a005d56-bd03-4438-b574-6eda9316006e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617307159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3617307159 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.347666347 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 219017210 ps |
CPU time | 1.29 seconds |
Started | Jul 09 06:42:39 PM PDT 24 |
Finished | Jul 09 06:42:41 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-737d6fd0-43e9-462a-80ad-9463cbf6e8c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=347666347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.347666347 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_busy.2033771218 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 241908774 ps |
CPU time | 1.32 seconds |
Started | Jul 09 06:42:45 PM PDT 24 |
Finished | Jul 09 06:42:48 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-33811d59-71c2-40dc-b61a-624ec4b38927 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2033771218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.2033771218 |
Directory | /workspace/0.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.2182838315 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 5378887663 ps |
CPU time | 7.04 seconds |
Started | Jul 09 06:42:38 PM PDT 24 |
Finished | Jul 09 06:42:46 PM PDT 24 |
Peak memory | 213860 kb |
Host | smart-a541ba01-3f41-4074-a4e8-e4cd1fef9a4e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2182838315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2182838315 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3104754086 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 5006059670 ps |
CPU time | 14.86 seconds |
Started | Jul 09 06:42:52 PM PDT 24 |
Finished | Jul 09 06:43:09 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-9f9a6637-4b60-4d30-b126-4607e3eb2600 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3104754086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3104754086 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.351524603 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 1355088205 ps |
CPU time | 2.55 seconds |
Started | Jul 09 06:42:53 PM PDT 24 |
Finished | Jul 09 06:42:58 PM PDT 24 |
Peak memory | 205620 kb |
Host | smart-5ce50505-5f61-4c7b-a0a7-bc58393b5745 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=351524603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.351524603 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.631759468 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 959526917 ps |
CPU time | 2.18 seconds |
Started | Jul 09 06:43:18 PM PDT 24 |
Finished | Jul 09 06:43:24 PM PDT 24 |
Peak memory | 205820 kb |
Host | smart-98c5a7d1-c42e-4ec7-8801-e08dfaf5c09e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631759468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.631759468 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.258112235 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 13758449315 ps |
CPU time | 19.71 seconds |
Started | Jul 09 06:43:33 PM PDT 24 |
Finished | Jul 09 06:43:53 PM PDT 24 |
Peak memory | 222032 kb |
Host | smart-3b8407b9-b4f4-41d6-b615-53b7771ed7d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=258112235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.258112235 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.4026923536 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 748536715 ps |
CPU time | 2.56 seconds |
Started | Jul 09 06:43:31 PM PDT 24 |
Finished | Jul 09 06:43:35 PM PDT 24 |
Peak memory | 205824 kb |
Host | smart-ccec4e5c-bce3-4a9c-b32a-a4c33ab052b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026923536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.4026923536 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/22.rv_dm_stress_all.592385770 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 11183716689 ps |
CPU time | 6.91 seconds |
Started | Jul 09 06:43:45 PM PDT 24 |
Finished | Jul 09 06:43:54 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-dea000d0-b9b8-4150-a45f-3b92fcf86713 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592385770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.592385770 |
Directory | /workspace/22.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/26.rv_dm_stress_all.854550094 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 1517816587 ps |
CPU time | 2.48 seconds |
Started | Jul 09 06:43:40 PM PDT 24 |
Finished | Jul 09 06:43:44 PM PDT 24 |
Peak memory | 205532 kb |
Host | smart-c6cd4010-3a1e-447f-921a-a04779a32a4e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854550094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.854550094 |
Directory | /workspace/26.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all.3374873306 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 6472842105 ps |
CPU time | 6.21 seconds |
Started | Jul 09 06:43:02 PM PDT 24 |
Finished | Jul 09 06:43:11 PM PDT 24 |
Peak memory | 213832 kb |
Host | smart-e54a44cb-a737-4bff-8f28-d16a77e5a7c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374873306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3374873306 |
Directory | /workspace/3.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/30.rv_dm_stress_all.2161370126 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 2108763180 ps |
CPU time | 6.93 seconds |
Started | Jul 09 06:43:43 PM PDT 24 |
Finished | Jul 09 06:43:51 PM PDT 24 |
Peak memory | 205468 kb |
Host | smart-c078cb21-235c-4e88-8a71-6475780d4cdc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161370126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.2161370126 |
Directory | /workspace/30.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3981872764 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 3165610064 ps |
CPU time | 21.21 seconds |
Started | Jul 09 06:41:11 PM PDT 24 |
Finished | Jul 09 06:41:34 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-62987489-bf27-4553-9861-7a3d1e528510 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981872764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3981872764 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4157023689 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 1169822123 ps |
CPU time | 25.8 seconds |
Started | Jul 09 06:40:34 PM PDT 24 |
Finished | Jul 09 06:41:00 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-c4827520-71fa-4f7b-9a1c-fb878d8dfe17 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157023689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.4157023689 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1359138335 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 3563962490 ps |
CPU time | 27.33 seconds |
Started | Jul 09 06:40:41 PM PDT 24 |
Finished | Jul 09 06:41:09 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-5dc1a61e-8fe5-4253-9d68-43d827c9e68a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359138335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1359138335 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1203529251 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 397609175 ps |
CPU time | 2.5 seconds |
Started | Jul 09 06:40:37 PM PDT 24 |
Finished | Jul 09 06:40:41 PM PDT 24 |
Peak memory | 214264 kb |
Host | smart-5509912d-8c03-4afe-9c26-b17927e2d7ed |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203529251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1203529251 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.213352491 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 5199567448 ps |
CPU time | 5.2 seconds |
Started | Jul 09 06:40:43 PM PDT 24 |
Finished | Jul 09 06:40:50 PM PDT 24 |
Peak memory | 219812 kb |
Host | smart-2e4fda4e-608f-439f-a2bb-1f79e12fb827 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213352491 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.213352491 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.292444078 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 155028884 ps |
CPU time | 1.73 seconds |
Started | Jul 09 06:40:43 PM PDT 24 |
Finished | Jul 09 06:40:47 PM PDT 24 |
Peak memory | 213152 kb |
Host | smart-17a06305-7eb5-47b6-bd5c-6879685e8ee7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292444078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.292444078 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3425718175 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 59126802929 ps |
CPU time | 85 seconds |
Started | Jul 09 06:40:38 PM PDT 24 |
Finished | Jul 09 06:42:04 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-fca5d184-aa32-4eb0-a536-ffcbe6b7d2bf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425718175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.3425718175 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1022453232 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 2611800121 ps |
CPU time | 6.8 seconds |
Started | Jul 09 06:40:38 PM PDT 24 |
Finished | Jul 09 06:40:46 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-dc9311f8-e86c-4e56-90f8-7c1cbfef520d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022453232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.1022453232 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.635460586 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 1569984082 ps |
CPU time | 5.46 seconds |
Started | Jul 09 06:40:37 PM PDT 24 |
Finished | Jul 09 06:40:44 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-1484b1b2-711d-4e81-ac27-7a265bd5f412 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635460586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.635460586 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2305829961 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 445687530 ps |
CPU time | 0.93 seconds |
Started | Jul 09 06:40:39 PM PDT 24 |
Finished | Jul 09 06:40:42 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-0cc1e3b8-4669-4447-9ba8-93898949e9f5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305829961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.2305829961 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4026797244 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 15982850471 ps |
CPU time | 41.86 seconds |
Started | Jul 09 06:40:35 PM PDT 24 |
Finished | Jul 09 06:41:18 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-0b143e2c-d7e3-4a62-a0d8-44f4eda42bf2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026797244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.4026797244 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3433590020 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 222225587 ps |
CPU time | 0.81 seconds |
Started | Jul 09 06:40:34 PM PDT 24 |
Finished | Jul 09 06:40:36 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-22a0e533-a0bd-45d6-bc64-8bd4137e9811 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433590020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.3433590020 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2185886368 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 414866354 ps |
CPU time | 1.42 seconds |
Started | Jul 09 06:40:32 PM PDT 24 |
Finished | Jul 09 06:40:34 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-80869032-7017-4a3d-8272-cc7a5257c07a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185886368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2 185886368 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.192460788 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 48624762 ps |
CPU time | 0.68 seconds |
Started | Jul 09 06:40:39 PM PDT 24 |
Finished | Jul 09 06:40:41 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-31564a21-9bd7-4d43-80a5-f0513fa9bbdc |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192460788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part ial_access.192460788 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2292754355 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 53174567 ps |
CPU time | 0.74 seconds |
Started | Jul 09 06:40:38 PM PDT 24 |
Finished | Jul 09 06:40:41 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-e3853899-ccd6-45d4-99be-6898e786416a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292754355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2292754355 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.407247948 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 761470565 ps |
CPU time | 6.87 seconds |
Started | Jul 09 06:40:42 PM PDT 24 |
Finished | Jul 09 06:40:49 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-e316fff9-8eb5-44ac-89f7-1b60b9d54729 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407247948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c sr_outstanding.407247948 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.465297316 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 33684854748 ps |
CPU time | 28.48 seconds |
Started | Jul 09 06:40:37 PM PDT 24 |
Finished | Jul 09 06:41:06 PM PDT 24 |
Peak memory | 221396 kb |
Host | smart-01983f26-1565-4269-b68a-2218266624d6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465297316 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.465297316 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.995545647 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 2193215049 ps |
CPU time | 9.73 seconds |
Started | Jul 09 06:40:37 PM PDT 24 |
Finished | Jul 09 06:40:47 PM PDT 24 |
Peak memory | 213316 kb |
Host | smart-7d5c326d-24cf-41f7-80aa-d0dd74c9a965 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995545647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.995545647 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3779101487 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 42043560703 ps |
CPU time | 77.77 seconds |
Started | Jul 09 06:40:58 PM PDT 24 |
Finished | Jul 09 06:42:17 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-3f4df6b7-b0b0-4a15-ba54-feadf09bc923 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779101487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.3779101487 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1887072906 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 232337944 ps |
CPU time | 2.74 seconds |
Started | Jul 09 06:41:03 PM PDT 24 |
Finished | Jul 09 06:41:07 PM PDT 24 |
Peak memory | 213276 kb |
Host | smart-80530925-4960-4455-9100-baca14792212 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887072906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1887072906 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3099807453 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 1174459857 ps |
CPU time | 5.83 seconds |
Started | Jul 09 06:41:02 PM PDT 24 |
Finished | Jul 09 06:41:09 PM PDT 24 |
Peak memory | 218588 kb |
Host | smart-e8a5c878-2f79-4a0c-b2ac-f175086bda0a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099807453 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3099807453 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2581412749 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 85273185 ps |
CPU time | 2.11 seconds |
Started | Jul 09 06:41:07 PM PDT 24 |
Finished | Jul 09 06:41:10 PM PDT 24 |
Peak memory | 213160 kb |
Host | smart-0dd812ee-1f08-4a2a-bc50-ec19a6515c5c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581412749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2581412749 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1814578146 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 12602779989 ps |
CPU time | 36.59 seconds |
Started | Jul 09 06:40:53 PM PDT 24 |
Finished | Jul 09 06:41:30 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-bd7f264c-f2fe-4488-baff-89eae04577e1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814578146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.1814578146 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2942718548 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 21421238736 ps |
CPU time | 17.6 seconds |
Started | Jul 09 06:40:53 PM PDT 24 |
Finished | Jul 09 06:41:12 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-abcaa6ce-071c-4957-8636-609e12a084bb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942718548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.2942718548 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3443853551 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 2372155672 ps |
CPU time | 4.39 seconds |
Started | Jul 09 06:40:48 PM PDT 24 |
Finished | Jul 09 06:40:53 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-7d2a16df-618c-40b5-b4b1-a1522c5f5db9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443853551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.3443853551 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3847262361 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 7270958085 ps |
CPU time | 15.8 seconds |
Started | Jul 09 06:40:52 PM PDT 24 |
Finished | Jul 09 06:41:09 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-0fe47c93-5023-41a2-ac0e-2013ecb27ff4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847262361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3 847262361 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.4264452802 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 328587683 ps |
CPU time | 1.12 seconds |
Started | Jul 09 06:40:47 PM PDT 24 |
Finished | Jul 09 06:40:49 PM PDT 24 |
Peak memory | 204744 kb |
Host | smart-4fd407a7-6a2e-4b6b-9ebc-38c025142779 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264452802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.4264452802 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1671348301 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 33869591020 ps |
CPU time | 14.94 seconds |
Started | Jul 09 06:40:47 PM PDT 24 |
Finished | Jul 09 06:41:03 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-25e9cb49-9aed-4ac4-9898-36ed9e470c49 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671348301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.1671348301 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2018764165 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 931198443 ps |
CPU time | 1.9 seconds |
Started | Jul 09 06:40:47 PM PDT 24 |
Finished | Jul 09 06:40:50 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-1ec2022b-58b0-4b5d-9c13-0729ab65af73 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018764165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.2018764165 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3640635452 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 720467583 ps |
CPU time | 1.57 seconds |
Started | Jul 09 06:40:48 PM PDT 24 |
Finished | Jul 09 06:40:50 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-b65829fd-f3f1-47dd-874a-8496d21e2173 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640635452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3 640635452 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.44132198 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 79059624 ps |
CPU time | 0.71 seconds |
Started | Jul 09 06:40:59 PM PDT 24 |
Finished | Jul 09 06:41:00 PM PDT 24 |
Peak memory | 204660 kb |
Host | smart-c965be49-91a6-4792-87d9-e0d335f97fe5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44132198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_parti al_access.44132198 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3943868892 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 135281196 ps |
CPU time | 0.78 seconds |
Started | Jul 09 06:40:57 PM PDT 24 |
Finished | Jul 09 06:40:59 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-22578814-80d9-476c-a698-93d2678b0764 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943868892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3943868892 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3266943338 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 418829863 ps |
CPU time | 4.04 seconds |
Started | Jul 09 06:41:08 PM PDT 24 |
Finished | Jul 09 06:41:12 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-991824f7-8734-4517-99e0-c20b9ec8a311 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266943338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.3266943338 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1968501928 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 310108397 ps |
CPU time | 4.29 seconds |
Started | Jul 09 06:40:54 PM PDT 24 |
Finished | Jul 09 06:40:59 PM PDT 24 |
Peak memory | 213332 kb |
Host | smart-c4b42c0e-0154-4a6d-b9d4-a3a8444ada7b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968501928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1968501928 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4029622904 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 3987234928 ps |
CPU time | 19.14 seconds |
Started | Jul 09 06:40:53 PM PDT 24 |
Finished | Jul 09 06:41:13 PM PDT 24 |
Peak memory | 213272 kb |
Host | smart-24551017-6f01-47b9-8c68-b07e4f3d8fe6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029622904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.4029622904 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.356806715 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 3365286314 ps |
CPU time | 9.12 seconds |
Started | Jul 09 06:42:05 PM PDT 24 |
Finished | Jul 09 06:42:15 PM PDT 24 |
Peak memory | 221528 kb |
Host | smart-e527ebd9-d303-484b-b9c1-2be7ded33694 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356806715 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.356806715 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1382624637 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 219139867 ps |
CPU time | 2.65 seconds |
Started | Jul 09 06:42:05 PM PDT 24 |
Finished | Jul 09 06:42:09 PM PDT 24 |
Peak memory | 213184 kb |
Host | smart-c1a21b41-87a9-4c75-b953-7bd1dc129bc0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382624637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1382624637 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2940664090 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 11452481582 ps |
CPU time | 4.44 seconds |
Started | Jul 09 06:42:02 PM PDT 24 |
Finished | Jul 09 06:42:08 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-c7f6816e-78f0-4bda-a14b-4e118974afaa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940664090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.2940664090 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2489404049 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 2249729292 ps |
CPU time | 2.58 seconds |
Started | Jul 09 06:42:00 PM PDT 24 |
Finished | Jul 09 06:42:03 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-926ed6cf-c6ea-4abf-b78f-c596aec3b6d1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489404049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 2489404049 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4163013545 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 690052610 ps |
CPU time | 5.96 seconds |
Started | Jul 09 06:42:07 PM PDT 24 |
Finished | Jul 09 06:42:14 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-6730d664-baef-4d76-9191-4830d983aec5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163013545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.4163013545 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.353852314 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 61781508 ps |
CPU time | 2.45 seconds |
Started | Jul 09 06:42:01 PM PDT 24 |
Finished | Jul 09 06:42:05 PM PDT 24 |
Peak memory | 213272 kb |
Host | smart-22dcaa63-a16a-4c84-94f7-8c008c30063c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353852314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.353852314 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3936915790 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 2028164046 ps |
CPU time | 11.76 seconds |
Started | Jul 09 06:42:02 PM PDT 24 |
Finished | Jul 09 06:42:14 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-96be59f5-8399-4db0-8509-442e7e61f1cf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936915790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3 936915790 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2353450727 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 164306483 ps |
CPU time | 3.03 seconds |
Started | Jul 09 06:42:11 PM PDT 24 |
Finished | Jul 09 06:42:14 PM PDT 24 |
Peak memory | 218656 kb |
Host | smart-26af5f2a-f5f0-443a-a7f9-76b376dcd984 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353450727 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2353450727 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2355428551 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 151756734 ps |
CPU time | 1.98 seconds |
Started | Jul 09 06:42:07 PM PDT 24 |
Finished | Jul 09 06:42:10 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-17834ca6-a633-4a03-afcb-fd635e1cafc0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355428551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2355428551 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1409665973 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 3956122142 ps |
CPU time | 5.12 seconds |
Started | Jul 09 06:42:05 PM PDT 24 |
Finished | Jul 09 06:42:11 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-138ebe28-60f0-4222-835f-64d2619a641b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409665973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .rv_dm_jtag_dmi_csr_bit_bash.1409665973 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.682101403 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 3049179384 ps |
CPU time | 1.58 seconds |
Started | Jul 09 06:42:06 PM PDT 24 |
Finished | Jul 09 06:42:09 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-5135091b-4f3b-4c34-a3b3-67b58786945c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682101403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.682101403 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3533676405 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 94198504 ps |
CPU time | 0.87 seconds |
Started | Jul 09 06:42:06 PM PDT 24 |
Finished | Jul 09 06:42:08 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-f0b33e62-3816-44ab-962d-0ad84c9a1d7c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533676405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 3533676405 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1168317677 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 3225104431 ps |
CPU time | 4.66 seconds |
Started | Jul 09 06:42:11 PM PDT 24 |
Finished | Jul 09 06:42:16 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-f09c7616-fe83-43c2-9e19-902b4dfeebdd |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168317677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.1168317677 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3707861786 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 664144717 ps |
CPU time | 4.06 seconds |
Started | Jul 09 06:42:05 PM PDT 24 |
Finished | Jul 09 06:42:10 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-b42f2135-785f-48a0-8197-bfdb63de8899 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707861786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3707861786 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3156486091 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 2360004624 ps |
CPU time | 10.75 seconds |
Started | Jul 09 06:42:06 PM PDT 24 |
Finished | Jul 09 06:42:18 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-f398016b-7af1-477c-b0bc-ec2fbfe33eb2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156486091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3 156486091 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.801424751 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 305110185 ps |
CPU time | 3.66 seconds |
Started | Jul 09 06:42:12 PM PDT 24 |
Finished | Jul 09 06:42:17 PM PDT 24 |
Peak memory | 221424 kb |
Host | smart-fb98c102-122d-4594-b06c-9ea54c670526 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801424751 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.801424751 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1034104668 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 163977519 ps |
CPU time | 2.11 seconds |
Started | Jul 09 06:42:13 PM PDT 24 |
Finished | Jul 09 06:42:16 PM PDT 24 |
Peak memory | 213312 kb |
Host | smart-ae198fe0-9582-4f34-a223-93c660be0498 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034104668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1034104668 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1693407553 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 2456943270 ps |
CPU time | 2.62 seconds |
Started | Jul 09 06:42:14 PM PDT 24 |
Finished | Jul 09 06:42:18 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-1fc86bd8-e868-472a-9ce3-fe1eea5ac121 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693407553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .rv_dm_jtag_dmi_csr_bit_bash.1693407553 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1384432511 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 13216818436 ps |
CPU time | 21.61 seconds |
Started | Jul 09 06:42:14 PM PDT 24 |
Finished | Jul 09 06:42:37 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-45113744-d186-470f-92b0-89d9e97b38e7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384432511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 1384432511 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2381908014 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 254079296 ps |
CPU time | 1.23 seconds |
Started | Jul 09 06:42:12 PM PDT 24 |
Finished | Jul 09 06:42:14 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-8cfb167a-66ff-4986-a594-0b373b6abd34 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381908014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 2381908014 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.375181941 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 980669394 ps |
CPU time | 7.92 seconds |
Started | Jul 09 06:42:13 PM PDT 24 |
Finished | Jul 09 06:42:22 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-5c95acdc-6bc1-4156-91c1-7db83afd82ca |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375181941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_ csr_outstanding.375181941 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1059055278 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 555726276 ps |
CPU time | 5 seconds |
Started | Jul 09 06:42:12 PM PDT 24 |
Finished | Jul 09 06:42:19 PM PDT 24 |
Peak memory | 221424 kb |
Host | smart-8cdbcdfe-da1e-4529-86a1-fb812aebdaf6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059055278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1059055278 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.4069678184 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 12199903053 ps |
CPU time | 22.11 seconds |
Started | Jul 09 06:42:11 PM PDT 24 |
Finished | Jul 09 06:42:35 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-563a70ef-259a-4200-bf45-ff15164ee572 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069678184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.4 069678184 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.660230642 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 7144882170 ps |
CPU time | 4.63 seconds |
Started | Jul 09 06:42:12 PM PDT 24 |
Finished | Jul 09 06:42:18 PM PDT 24 |
Peak memory | 219840 kb |
Host | smart-ccde6bf3-1e0d-46c3-b7e1-d47c57c81a41 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660230642 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.660230642 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.406116264 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 1153087165 ps |
CPU time | 2.39 seconds |
Started | Jul 09 06:42:18 PM PDT 24 |
Finished | Jul 09 06:42:21 PM PDT 24 |
Peak memory | 213184 kb |
Host | smart-bfc629f1-9d52-4319-ae7a-6eaf7a088fd2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406116264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.406116264 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1095984312 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 4781996734 ps |
CPU time | 3.83 seconds |
Started | Jul 09 06:42:10 PM PDT 24 |
Finished | Jul 09 06:42:15 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-8f79ceaa-4490-4068-94e6-1f2c5f798618 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095984312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .rv_dm_jtag_dmi_csr_bit_bash.1095984312 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.452493133 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 13777847182 ps |
CPU time | 19.63 seconds |
Started | Jul 09 06:42:13 PM PDT 24 |
Finished | Jul 09 06:42:33 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-7c7eff77-c7f7-4b42-bdfe-f33a4097a9aa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452493133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.452493133 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4018834677 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 526586391 ps |
CPU time | 1.93 seconds |
Started | Jul 09 06:42:10 PM PDT 24 |
Finished | Jul 09 06:42:13 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-bb2c0efa-bf32-46c4-815e-31aa8b216f59 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018834677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 4018834677 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.594114554 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 209212325 ps |
CPU time | 6.63 seconds |
Started | Jul 09 06:42:17 PM PDT 24 |
Finished | Jul 09 06:42:25 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-f1ac5c7b-51cb-4145-8bdb-958340235fb0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594114554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_ csr_outstanding.594114554 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.852730159 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 219804285 ps |
CPU time | 5.14 seconds |
Started | Jul 09 06:42:17 PM PDT 24 |
Finished | Jul 09 06:42:24 PM PDT 24 |
Peak memory | 213104 kb |
Host | smart-4d243329-b870-4dd2-badb-57ec8c704c06 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852730159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.852730159 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1559169759 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 2330574249 ps |
CPU time | 3.62 seconds |
Started | Jul 09 06:42:16 PM PDT 24 |
Finished | Jul 09 06:42:22 PM PDT 24 |
Peak memory | 215372 kb |
Host | smart-2736e818-8caf-4fed-aaa0-7d121a2db767 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559169759 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1559169759 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3223230721 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 369790808 ps |
CPU time | 1.57 seconds |
Started | Jul 09 06:42:20 PM PDT 24 |
Finished | Jul 09 06:42:23 PM PDT 24 |
Peak memory | 213284 kb |
Host | smart-774c9cd9-f684-4822-9961-2980a5a0d1de |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223230721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3223230721 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.241745237 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 17260444395 ps |
CPU time | 49.08 seconds |
Started | Jul 09 06:42:17 PM PDT 24 |
Finished | Jul 09 06:43:08 PM PDT 24 |
Peak memory | 204780 kb |
Host | smart-560e4299-1dba-46bf-b51a-7301d64ecaa6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241745237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. rv_dm_jtag_dmi_csr_bit_bash.241745237 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1211098365 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 3423217476 ps |
CPU time | 2.62 seconds |
Started | Jul 09 06:42:14 PM PDT 24 |
Finished | Jul 09 06:42:18 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-124884ce-bf35-4052-bed8-5d79ca18ce00 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211098365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 1211098365 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4045772187 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 221212256 ps |
CPU time | 0.9 seconds |
Started | Jul 09 06:42:37 PM PDT 24 |
Finished | Jul 09 06:42:40 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-bac04081-3786-4bae-b077-03313f8ed5cc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045772187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 4045772187 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1391346333 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 1114813921 ps |
CPU time | 8.19 seconds |
Started | Jul 09 06:42:18 PM PDT 24 |
Finished | Jul 09 06:42:28 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-45698f5a-3094-4ed9-a981-2947838cc6e7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391346333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.1391346333 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2980822228 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 393199476 ps |
CPU time | 4.86 seconds |
Started | Jul 09 06:42:17 PM PDT 24 |
Finished | Jul 09 06:42:23 PM PDT 24 |
Peak memory | 213244 kb |
Host | smart-2d810e1a-00e6-4551-a315-76d661449778 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980822228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2980822228 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3086393010 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 5412945057 ps |
CPU time | 26.3 seconds |
Started | Jul 09 06:42:17 PM PDT 24 |
Finished | Jul 09 06:42:45 PM PDT 24 |
Peak memory | 213348 kb |
Host | smart-611134ec-c619-4dcd-bb1d-10b4888aa3a3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086393010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3 086393010 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.917039199 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 333518158 ps |
CPU time | 2.31 seconds |
Started | Jul 09 06:42:21 PM PDT 24 |
Finished | Jul 09 06:42:25 PM PDT 24 |
Peak memory | 213328 kb |
Host | smart-e9c7f2b1-ab07-4ea2-b6b6-3f76ea6fd580 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917039199 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.917039199 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2389491672 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 103481392 ps |
CPU time | 1.52 seconds |
Started | Jul 09 06:42:21 PM PDT 24 |
Finished | Jul 09 06:42:25 PM PDT 24 |
Peak memory | 213232 kb |
Host | smart-1223ad16-713f-41b2-8921-bf539836cb5a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389491672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2389491672 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.4033016917 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 13275928113 ps |
CPU time | 33.56 seconds |
Started | Jul 09 06:42:22 PM PDT 24 |
Finished | Jul 09 06:42:57 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-7173a6b8-1fb5-42f9-bd0e-beaba251307f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033016917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .rv_dm_jtag_dmi_csr_bit_bash.4033016917 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.463328843 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 2473904067 ps |
CPU time | 4.33 seconds |
Started | Jul 09 06:42:21 PM PDT 24 |
Finished | Jul 09 06:42:27 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-c0e27eaa-c615-4a10-a6f3-ed57dc791ac7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463328843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.463328843 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.22218127 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 226413248 ps |
CPU time | 1.23 seconds |
Started | Jul 09 06:42:17 PM PDT 24 |
Finished | Jul 09 06:42:20 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-1c5e5e93-933c-48bf-a15b-8f8b8d51d064 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22218127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.22218127 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.973335549 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 362812056 ps |
CPU time | 6.55 seconds |
Started | Jul 09 06:42:21 PM PDT 24 |
Finished | Jul 09 06:42:29 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-dd026409-2d11-4828-8855-0f15dda1a216 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973335549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_ csr_outstanding.973335549 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3755981183 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 912064295 ps |
CPU time | 3.44 seconds |
Started | Jul 09 06:42:22 PM PDT 24 |
Finished | Jul 09 06:42:27 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-61b14b91-2efd-4380-99f7-9464e019c1ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755981183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3755981183 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3930037942 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 836496489 ps |
CPU time | 2.59 seconds |
Started | Jul 09 06:42:24 PM PDT 24 |
Finished | Jul 09 06:42:28 PM PDT 24 |
Peak memory | 217424 kb |
Host | smart-a1e124f4-682a-43b4-aa45-3d9027cc1d5a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930037942 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3930037942 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3753029 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 158945959 ps |
CPU time | 2.5 seconds |
Started | Jul 09 06:42:23 PM PDT 24 |
Finished | Jul 09 06:42:27 PM PDT 24 |
Peak memory | 213196 kb |
Host | smart-56c1b93f-c4fa-4f83-af47-0fc37a5ff11d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3753029 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1024610067 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 2376141703 ps |
CPU time | 4.81 seconds |
Started | Jul 09 06:42:25 PM PDT 24 |
Finished | Jul 09 06:42:30 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-2e9bd73d-7e93-455b-aa65-f654ed5f6ba2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024610067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .rv_dm_jtag_dmi_csr_bit_bash.1024610067 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2161180149 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 5115474967 ps |
CPU time | 2.44 seconds |
Started | Jul 09 06:42:23 PM PDT 24 |
Finished | Jul 09 06:42:27 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-04cc4475-5217-4791-b3f1-924997d08c2e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161180149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 2161180149 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1735883156 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 582594577 ps |
CPU time | 1.54 seconds |
Started | Jul 09 06:42:23 PM PDT 24 |
Finished | Jul 09 06:42:26 PM PDT 24 |
Peak memory | 204648 kb |
Host | smart-d735e1ec-5091-4018-899c-46120cf1c29d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735883156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 1735883156 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.4156620275 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 600640476 ps |
CPU time | 7.87 seconds |
Started | Jul 09 06:42:23 PM PDT 24 |
Finished | Jul 09 06:42:33 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-3194d886-3a5f-4adc-a51e-770c6af64c68 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156620275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.4156620275 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3246476525 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 264823571 ps |
CPU time | 4.34 seconds |
Started | Jul 09 06:42:24 PM PDT 24 |
Finished | Jul 09 06:42:30 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-225f024e-1244-43d8-9b27-c7146ac5bd67 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246476525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3246476525 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1671340529 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 628677054 ps |
CPU time | 9.33 seconds |
Started | Jul 09 06:42:21 PM PDT 24 |
Finished | Jul 09 06:42:32 PM PDT 24 |
Peak memory | 213276 kb |
Host | smart-7aa94289-c2f0-48f2-806a-815a9c7f0a7c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671340529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1 671340529 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.457907320 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 450118328 ps |
CPU time | 2.66 seconds |
Started | Jul 09 06:42:28 PM PDT 24 |
Finished | Jul 09 06:42:32 PM PDT 24 |
Peak memory | 221420 kb |
Host | smart-e4fee573-a504-4dee-8875-09698936be00 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457907320 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.457907320 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3851424479 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 156418264 ps |
CPU time | 2.23 seconds |
Started | Jul 09 06:42:28 PM PDT 24 |
Finished | Jul 09 06:42:31 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-a739260c-fd36-4ec4-92e1-1be635248301 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851424479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3851424479 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3463686525 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 23563599702 ps |
CPU time | 20.78 seconds |
Started | Jul 09 06:42:29 PM PDT 24 |
Finished | Jul 09 06:42:51 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-faf180e7-b286-483d-959a-70dbc3b4ab78 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463686525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.3463686525 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4070738762 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 2484442377 ps |
CPU time | 7.74 seconds |
Started | Jul 09 06:42:27 PM PDT 24 |
Finished | Jul 09 06:42:36 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-d9ba9296-ccd0-435b-b872-56de34da22c4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070738762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 4070738762 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1461374073 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 253787005 ps |
CPU time | 1.28 seconds |
Started | Jul 09 06:42:26 PM PDT 24 |
Finished | Jul 09 06:42:28 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-beebdaae-a10c-422c-949e-07a47c5b47b7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461374073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 1461374073 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1557555519 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 7690099717 ps |
CPU time | 8.18 seconds |
Started | Jul 09 06:42:27 PM PDT 24 |
Finished | Jul 09 06:42:36 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-d655a5c9-f67c-42c5-baf9-7141741457db |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557555519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.1557555519 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3673933198 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 545805098 ps |
CPU time | 3.24 seconds |
Started | Jul 09 06:42:27 PM PDT 24 |
Finished | Jul 09 06:42:31 PM PDT 24 |
Peak memory | 215696 kb |
Host | smart-5a0ab779-5f0f-48de-8630-f08f996aa195 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673933198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3673933198 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2582079883 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 2924189430 ps |
CPU time | 8.37 seconds |
Started | Jul 09 06:42:27 PM PDT 24 |
Finished | Jul 09 06:42:37 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-1208a6d3-cec5-4c3e-9674-372a3505dbb6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582079883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2 582079883 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.546407431 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 281987558 ps |
CPU time | 3.93 seconds |
Started | Jul 09 06:42:34 PM PDT 24 |
Finished | Jul 09 06:42:39 PM PDT 24 |
Peak memory | 219196 kb |
Host | smart-d9c2d0a6-018b-4ddb-bc4d-d0942833eff9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546407431 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.546407431 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2083258792 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 349679025 ps |
CPU time | 2.36 seconds |
Started | Jul 09 06:42:35 PM PDT 24 |
Finished | Jul 09 06:42:38 PM PDT 24 |
Peak memory | 213260 kb |
Host | smart-d20fbdd3-8048-4635-8d7a-62aff802ac03 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083258792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2083258792 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1119146000 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 79665986034 ps |
CPU time | 53.35 seconds |
Started | Jul 09 06:42:31 PM PDT 24 |
Finished | Jul 09 06:43:27 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-d2fd022b-5353-4c73-8fe4-68d165001627 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119146000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.1119146000 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.992668952 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 13564471776 ps |
CPU time | 18.11 seconds |
Started | Jul 09 06:42:38 PM PDT 24 |
Finished | Jul 09 06:42:57 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-ff7ec4bf-b8fd-4f7f-9964-c38f7e1e9046 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992668952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.992668952 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.295503387 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 80412447 ps |
CPU time | 0.87 seconds |
Started | Jul 09 06:42:34 PM PDT 24 |
Finished | Jul 09 06:42:36 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-631bfba8-e7f7-4635-b4ab-2d50a989bab8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295503387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.295503387 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.910457546 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 992499920 ps |
CPU time | 7.42 seconds |
Started | Jul 09 06:42:33 PM PDT 24 |
Finished | Jul 09 06:42:42 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-49df599f-dc87-4931-8eb1-90b9ec3a3f48 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910457546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_ csr_outstanding.910457546 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1930136996 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 192106650 ps |
CPU time | 4.78 seconds |
Started | Jul 09 06:42:34 PM PDT 24 |
Finished | Jul 09 06:42:40 PM PDT 24 |
Peak memory | 213200 kb |
Host | smart-2379f7c8-1bbd-4a0c-a863-0599e7b678f0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930136996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1930136996 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4236145178 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 1143289414 ps |
CPU time | 11.59 seconds |
Started | Jul 09 06:42:37 PM PDT 24 |
Finished | Jul 09 06:42:49 PM PDT 24 |
Peak memory | 213188 kb |
Host | smart-feef6385-ee94-4d91-b305-898fc0ecfa3d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236145178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4 236145178 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4080000993 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 70086781 ps |
CPU time | 2.73 seconds |
Started | Jul 09 06:42:33 PM PDT 24 |
Finished | Jul 09 06:42:37 PM PDT 24 |
Peak memory | 218292 kb |
Host | smart-2ad7cbb9-086b-4795-8733-64a913496e83 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080000993 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.4080000993 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.145254662 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 307510137 ps |
CPU time | 1.62 seconds |
Started | Jul 09 06:42:33 PM PDT 24 |
Finished | Jul 09 06:42:36 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-45064da1-985b-42c8-99c4-dad3afe316c9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145254662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.145254662 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.593201809 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 8990612838 ps |
CPU time | 26.62 seconds |
Started | Jul 09 06:42:35 PM PDT 24 |
Finished | Jul 09 06:43:02 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-3764e54c-6856-48e6-b168-84877a276663 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593201809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. rv_dm_jtag_dmi_csr_bit_bash.593201809 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2935642021 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 7825843120 ps |
CPU time | 7.56 seconds |
Started | Jul 09 06:42:35 PM PDT 24 |
Finished | Jul 09 06:42:44 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-9b9110f6-1f69-4b35-9fc6-0d14182036a2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935642021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 2935642021 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.514799460 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 732160712 ps |
CPU time | 1.62 seconds |
Started | Jul 09 06:42:32 PM PDT 24 |
Finished | Jul 09 06:42:36 PM PDT 24 |
Peak memory | 204760 kb |
Host | smart-656e12da-eb69-4596-84e2-48ae5597f818 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514799460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.514799460 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1266654179 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 1048663454 ps |
CPU time | 7.66 seconds |
Started | Jul 09 06:42:31 PM PDT 24 |
Finished | Jul 09 06:42:41 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-4f9d23e7-32e8-434e-bb69-2e4ca23aa454 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266654179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.1266654179 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2786608786 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 326334570 ps |
CPU time | 4.44 seconds |
Started | Jul 09 06:42:36 PM PDT 24 |
Finished | Jul 09 06:42:41 PM PDT 24 |
Peak memory | 215756 kb |
Host | smart-b6a383b9-bc87-4f41-9b53-1b73705ae96f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786608786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2786608786 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2495423995 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 2142783437 ps |
CPU time | 30.73 seconds |
Started | Jul 09 06:41:04 PM PDT 24 |
Finished | Jul 09 06:41:36 PM PDT 24 |
Peak memory | 213228 kb |
Host | smart-f9ef0fa0-9351-4b07-8036-901cd573dd50 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495423995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.2495423995 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3636685132 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 11757864532 ps |
CPU time | 30.89 seconds |
Started | Jul 09 06:41:15 PM PDT 24 |
Finished | Jul 09 06:41:47 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-aa078629-5a8f-4cac-a5db-d4a717136727 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636685132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3636685132 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2283576628 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 85764877 ps |
CPU time | 1.61 seconds |
Started | Jul 09 06:41:15 PM PDT 24 |
Finished | Jul 09 06:41:18 PM PDT 24 |
Peak memory | 213272 kb |
Host | smart-8f911929-b9b3-4e9a-965c-574e1e25a6f3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283576628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2283576628 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1419243549 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 5248195046 ps |
CPU time | 4.88 seconds |
Started | Jul 09 06:41:13 PM PDT 24 |
Finished | Jul 09 06:41:20 PM PDT 24 |
Peak memory | 220216 kb |
Host | smart-0df1d779-676d-4f4b-98f4-6c7e6e07f2e9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419243549 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1419243549 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2184965583 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 56751707 ps |
CPU time | 1.52 seconds |
Started | Jul 09 06:41:14 PM PDT 24 |
Finished | Jul 09 06:41:17 PM PDT 24 |
Peak memory | 213324 kb |
Host | smart-4a9750d2-56be-4b5f-a848-db71e79dc576 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184965583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2184965583 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2561831248 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 61186351051 ps |
CPU time | 149.32 seconds |
Started | Jul 09 06:41:10 PM PDT 24 |
Finished | Jul 09 06:43:40 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-d9488351-7810-4488-865c-aefca50abdb4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561831248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.2561831248 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4256632963 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 108260291283 ps |
CPU time | 279.94 seconds |
Started | Jul 09 06:41:09 PM PDT 24 |
Finished | Jul 09 06:45:51 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-ed5ee661-17b5-4802-8f8b-6f7790f8a807 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256632963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. rv_dm_jtag_dmi_csr_bit_bash.4256632963 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2508322415 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 16171649786 ps |
CPU time | 44.28 seconds |
Started | Jul 09 06:41:09 PM PDT 24 |
Finished | Jul 09 06:41:55 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-10d1d7b3-85af-405f-a1a6-826671e22e6b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508322415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.2508322415 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1501654917 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 1080038408 ps |
CPU time | 1.93 seconds |
Started | Jul 09 06:41:11 PM PDT 24 |
Finished | Jul 09 06:41:15 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-2080fccc-854a-468a-a14d-1701d98f2468 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501654917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1 501654917 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3574751496 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 779374589 ps |
CPU time | 0.88 seconds |
Started | Jul 09 06:41:08 PM PDT 24 |
Finished | Jul 09 06:41:10 PM PDT 24 |
Peak memory | 204732 kb |
Host | smart-21ff374c-8bb9-4e37-a366-b51dda64af37 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574751496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.3574751496 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3442205294 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 7975614486 ps |
CPU time | 12.29 seconds |
Started | Jul 09 06:41:09 PM PDT 24 |
Finished | Jul 09 06:41:23 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-9408ea99-8574-452a-acd6-dcd361c0930f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442205294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.3442205294 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3016245338 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 123793009 ps |
CPU time | 0.98 seconds |
Started | Jul 09 06:41:08 PM PDT 24 |
Finished | Jul 09 06:41:10 PM PDT 24 |
Peak memory | 204644 kb |
Host | smart-80b9e856-fd2a-409f-8a09-9840d20e3b6f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016245338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.3016245338 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.982907359 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 360607140 ps |
CPU time | 1.43 seconds |
Started | Jul 09 06:41:10 PM PDT 24 |
Finished | Jul 09 06:41:13 PM PDT 24 |
Peak memory | 204752 kb |
Host | smart-9b0a1d00-c2eb-4360-99dc-a584d6cbb0f8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982907359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.982907359 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.4227552256 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 151417742 ps |
CPU time | 1.04 seconds |
Started | Jul 09 06:41:13 PM PDT 24 |
Finished | Jul 09 06:41:16 PM PDT 24 |
Peak memory | 204632 kb |
Host | smart-536b6db3-3c66-4ed6-b57e-0b9f6673ff81 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227552256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.4227552256 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.612943405 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 49867614 ps |
CPU time | 0.71 seconds |
Started | Jul 09 06:41:16 PM PDT 24 |
Finished | Jul 09 06:41:18 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-c7e0944f-5f52-443a-a338-56c6eb760e57 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612943405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.612943405 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2014703084 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 596071531 ps |
CPU time | 3.61 seconds |
Started | Jul 09 06:41:15 PM PDT 24 |
Finished | Jul 09 06:41:21 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-183c048e-4468-4a33-a424-619434ed1ac3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014703084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.2014703084 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.925275041 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 200125210 ps |
CPU time | 2.48 seconds |
Started | Jul 09 06:41:09 PM PDT 24 |
Finished | Jul 09 06:41:12 PM PDT 24 |
Peak memory | 213204 kb |
Host | smart-90ba13af-374c-4cb8-899a-481a8763bba9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925275041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.925275041 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.492778613 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 716682249 ps |
CPU time | 27.43 seconds |
Started | Jul 09 06:41:15 PM PDT 24 |
Finished | Jul 09 06:41:45 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-c7f98be0-5ac9-43ed-b4a2-2656f7f768b5 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492778613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 3.rv_dm_csr_aliasing.492778613 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2239231349 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 14887360211 ps |
CPU time | 69.46 seconds |
Started | Jul 09 06:41:25 PM PDT 24 |
Finished | Jul 09 06:42:35 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-91470943-d295-4cfc-a580-b97f47ce3917 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239231349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2239231349 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3535570760 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 619061712 ps |
CPU time | 2.69 seconds |
Started | Jul 09 06:41:26 PM PDT 24 |
Finished | Jul 09 06:41:30 PM PDT 24 |
Peak memory | 213312 kb |
Host | smart-4a092457-15bf-48ea-8979-590530efedab |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535570760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3535570760 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4282732762 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 2096568634 ps |
CPU time | 4.97 seconds |
Started | Jul 09 06:41:25 PM PDT 24 |
Finished | Jul 09 06:41:32 PM PDT 24 |
Peak memory | 218636 kb |
Host | smart-39f3bf47-da36-4cc2-aece-b3ae0e5c74db |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282732762 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.4282732762 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1172475458 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 165605883 ps |
CPU time | 1.74 seconds |
Started | Jul 09 06:41:27 PM PDT 24 |
Finished | Jul 09 06:41:30 PM PDT 24 |
Peak memory | 213136 kb |
Host | smart-c37b57bc-e300-46b5-8122-306705ff986c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172475458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1172475458 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.975699072 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 22123923143 ps |
CPU time | 34.22 seconds |
Started | Jul 09 06:41:22 PM PDT 24 |
Finished | Jul 09 06:41:57 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-6356ca91-5e4f-4da4-90c1-40829d1ea123 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975699072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr _aliasing.975699072 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2212564230 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 7978690186 ps |
CPU time | 6.34 seconds |
Started | Jul 09 06:41:19 PM PDT 24 |
Finished | Jul 09 06:41:27 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-8c4d8591-f12f-4aaf-8f01-ac884252dfb9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212564230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rv_dm_jtag_dmi_csr_bit_bash.2212564230 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.880280268 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 6775771566 ps |
CPU time | 10.95 seconds |
Started | Jul 09 06:41:19 PM PDT 24 |
Finished | Jul 09 06:41:32 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-4efc13a3-1822-4764-941d-a712a58332d1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880280268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr _hw_reset.880280268 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.371771520 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 5463604239 ps |
CPU time | 13.84 seconds |
Started | Jul 09 06:41:20 PM PDT 24 |
Finished | Jul 09 06:41:35 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-0f5f15fa-d32e-48ee-8456-875442b8469e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371771520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.371771520 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3186597810 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 453387559 ps |
CPU time | 1.86 seconds |
Started | Jul 09 06:41:16 PM PDT 24 |
Finished | Jul 09 06:41:20 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-a4125e65-79dd-4c0b-98b1-16f92de88b28 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186597810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.3186597810 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2155570174 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 20405059800 ps |
CPU time | 47.63 seconds |
Started | Jul 09 06:41:21 PM PDT 24 |
Finished | Jul 09 06:42:10 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-ed4f2a54-50b3-45a0-bd8c-af14c22cb3c6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155570174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.2155570174 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3492028356 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 293505377 ps |
CPU time | 1.09 seconds |
Started | Jul 09 06:41:14 PM PDT 24 |
Finished | Jul 09 06:41:17 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-439fe1db-708b-47f5-a97b-38299f42e4e4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492028356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.3492028356 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1116444447 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 232533061 ps |
CPU time | 0.97 seconds |
Started | Jul 09 06:41:22 PM PDT 24 |
Finished | Jul 09 06:41:24 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-48162b2e-893e-45bf-8c19-73a635401877 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116444447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1 116444447 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1165938384 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 62396302 ps |
CPU time | 0.83 seconds |
Started | Jul 09 06:41:27 PM PDT 24 |
Finished | Jul 09 06:41:29 PM PDT 24 |
Peak memory | 204616 kb |
Host | smart-f730f406-5802-4689-8a78-dbbc1e6e035b |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165938384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.1165938384 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4178313784 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 105420346 ps |
CPU time | 0.75 seconds |
Started | Jul 09 06:41:25 PM PDT 24 |
Finished | Jul 09 06:41:27 PM PDT 24 |
Peak memory | 204732 kb |
Host | smart-a4e1d66d-875f-4ce5-947c-23c1659a4ab1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178313784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.4178313784 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2295485176 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 186356525 ps |
CPU time | 6.65 seconds |
Started | Jul 09 06:41:25 PM PDT 24 |
Finished | Jul 09 06:41:33 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-8c4c792b-c908-4754-a205-1c8ff772e659 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295485176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.2295485176 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2598604709 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 20941199888 ps |
CPU time | 60.13 seconds |
Started | Jul 09 06:41:19 PM PDT 24 |
Finished | Jul 09 06:42:21 PM PDT 24 |
Peak memory | 221468 kb |
Host | smart-cdb4a15b-a45c-448b-8749-0e63e3c43f94 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598604709 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2598604709 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2482681868 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 1124781743 ps |
CPU time | 5.41 seconds |
Started | Jul 09 06:41:19 PM PDT 24 |
Finished | Jul 09 06:41:26 PM PDT 24 |
Peak memory | 213232 kb |
Host | smart-3e6cbed1-8997-4fc6-b58b-7466a30e921f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482681868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2482681868 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.642751235 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 5980497265 ps |
CPU time | 32.9 seconds |
Started | Jul 09 06:41:36 PM PDT 24 |
Finished | Jul 09 06:42:10 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-8a4ee358-19b0-44a8-9b16-cb54e9d0121a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642751235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.642751235 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4100962230 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 412504462 ps |
CPU time | 2.47 seconds |
Started | Jul 09 06:41:36 PM PDT 24 |
Finished | Jul 09 06:41:40 PM PDT 24 |
Peak memory | 213220 kb |
Host | smart-486d4855-869a-4cef-b3ae-a5df1f90e143 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100962230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.4100962230 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.877429014 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 4043030412 ps |
CPU time | 3.91 seconds |
Started | Jul 09 06:41:34 PM PDT 24 |
Finished | Jul 09 06:41:39 PM PDT 24 |
Peak memory | 221212 kb |
Host | smart-357e4b6c-80ad-4578-a3eb-51ab14d46b6f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877429014 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.877429014 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1563643377 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 130691092 ps |
CPU time | 1.36 seconds |
Started | Jul 09 06:41:35 PM PDT 24 |
Finished | Jul 09 06:41:38 PM PDT 24 |
Peak memory | 213172 kb |
Host | smart-e71e463c-f82c-4c81-a6e7-0cf109afee32 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563643377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1563643377 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2751985403 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 133451420140 ps |
CPU time | 211.15 seconds |
Started | Jul 09 06:41:31 PM PDT 24 |
Finished | Jul 09 06:45:02 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-ec63e54b-dca1-4394-9d13-635a7640c9e7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751985403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.2751985403 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2521382706 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 25691277153 ps |
CPU time | 64.7 seconds |
Started | Jul 09 06:41:29 PM PDT 24 |
Finished | Jul 09 06:42:34 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-10ed7833-c513-4c57-a0ad-825fe17c8ff4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521382706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. rv_dm_jtag_dmi_csr_bit_bash.2521382706 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3448560105 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 2285608916 ps |
CPU time | 6.99 seconds |
Started | Jul 09 06:41:29 PM PDT 24 |
Finished | Jul 09 06:41:37 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-78c29910-ad30-448f-bb2f-1f6f728a6f29 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448560105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.3448560105 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2029201031 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 5499112110 ps |
CPU time | 4.27 seconds |
Started | Jul 09 06:41:29 PM PDT 24 |
Finished | Jul 09 06:41:34 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-2c64f865-37b4-40f3-ae7c-565c70ff2c90 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029201031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2 029201031 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2925821665 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 174936182 ps |
CPU time | 0.78 seconds |
Started | Jul 09 06:41:32 PM PDT 24 |
Finished | Jul 09 06:41:33 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-3a8d9a88-93bc-4992-9b07-110ee1e8307d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925821665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.2925821665 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3205683653 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 21315387792 ps |
CPU time | 53.03 seconds |
Started | Jul 09 06:41:31 PM PDT 24 |
Finished | Jul 09 06:42:24 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-c0336410-53a0-4d8a-81f2-fb8682607feb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205683653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.3205683653 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1698850848 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 541876775 ps |
CPU time | 1.95 seconds |
Started | Jul 09 06:41:24 PM PDT 24 |
Finished | Jul 09 06:41:27 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-5cc85400-c71e-401c-8119-af009361e904 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698850848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.1698850848 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1030136674 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 632616889 ps |
CPU time | 1.54 seconds |
Started | Jul 09 06:41:24 PM PDT 24 |
Finished | Jul 09 06:41:26 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-6c68d8fa-a68a-4a2c-8f6d-6694189b2641 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030136674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1 030136674 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.970107821 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 92535657 ps |
CPU time | 0.69 seconds |
Started | Jul 09 06:41:35 PM PDT 24 |
Finished | Jul 09 06:41:37 PM PDT 24 |
Peak memory | 204684 kb |
Host | smart-9372055d-b135-4bac-8fee-7b25ccb27d96 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970107821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part ial_access.970107821 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2060335817 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 33475222 ps |
CPU time | 0.68 seconds |
Started | Jul 09 06:41:35 PM PDT 24 |
Finished | Jul 09 06:41:37 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-90f45f12-fac3-4342-a556-fc965c10dae3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060335817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2060335817 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1136049217 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 213774218 ps |
CPU time | 3.8 seconds |
Started | Jul 09 06:41:39 PM PDT 24 |
Finished | Jul 09 06:41:44 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-05f08b76-78a3-40fe-aa9f-897d36c221d6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136049217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.1136049217 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2439681274 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 250512480 ps |
CPU time | 2.9 seconds |
Started | Jul 09 06:41:35 PM PDT 24 |
Finished | Jul 09 06:41:39 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-840d53ba-fcaa-430a-967e-ea3554820f7e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439681274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2439681274 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4100972516 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 7765458764 ps |
CPU time | 20.41 seconds |
Started | Jul 09 06:41:35 PM PDT 24 |
Finished | Jul 09 06:41:57 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-c7a50e2c-04f9-41a4-9833-fe37c1eeb0a6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100972516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.4100972516 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3569080082 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 314829535 ps |
CPU time | 3.75 seconds |
Started | Jul 09 06:41:41 PM PDT 24 |
Finished | Jul 09 06:41:46 PM PDT 24 |
Peak memory | 218812 kb |
Host | smart-e5887635-2f20-4102-b327-0d6e030ead6a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569080082 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3569080082 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3329558738 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 139722479 ps |
CPU time | 2.39 seconds |
Started | Jul 09 06:41:41 PM PDT 24 |
Finished | Jul 09 06:41:44 PM PDT 24 |
Peak memory | 213132 kb |
Host | smart-99fbb355-d8df-48a5-88a0-76587dd1cd27 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329558738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3329558738 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2143838676 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 47120566589 ps |
CPU time | 26.03 seconds |
Started | Jul 09 06:41:39 PM PDT 24 |
Finished | Jul 09 06:42:06 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-8a8fd5fb-02ad-40b9-846b-c6da5761f7ee |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143838676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. rv_dm_jtag_dmi_csr_bit_bash.2143838676 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.283447621 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 3684231794 ps |
CPU time | 5.25 seconds |
Started | Jul 09 06:41:41 PM PDT 24 |
Finished | Jul 09 06:41:48 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-935c1a3b-415c-4c9c-a920-5bad3dd7efbc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283447621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.283447621 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3827717902 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 954898291 ps |
CPU time | 1.21 seconds |
Started | Jul 09 06:41:36 PM PDT 24 |
Finished | Jul 09 06:41:38 PM PDT 24 |
Peak memory | 204732 kb |
Host | smart-1fbb4f2d-eeda-46e3-9760-ba754064d98e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827717902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3 827717902 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.984518752 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 743676256 ps |
CPU time | 6.36 seconds |
Started | Jul 09 06:41:40 PM PDT 24 |
Finished | Jul 09 06:41:47 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-62d43a51-1a81-4e8f-aff8-7a0f7d2c30ea |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984518752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c sr_outstanding.984518752 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3206428107 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 131542224 ps |
CPU time | 4.02 seconds |
Started | Jul 09 06:41:42 PM PDT 24 |
Finished | Jul 09 06:41:47 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-ae2cf299-733e-4c36-b390-b4572af0fc5b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206428107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3206428107 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2055354118 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 102914867 ps |
CPU time | 2.26 seconds |
Started | Jul 09 06:41:45 PM PDT 24 |
Finished | Jul 09 06:41:48 PM PDT 24 |
Peak memory | 221472 kb |
Host | smart-d9beb54e-0473-422f-afa3-5dad2f7da1a5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055354118 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2055354118 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.738402176 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 341662792 ps |
CPU time | 2.44 seconds |
Started | Jul 09 06:41:45 PM PDT 24 |
Finished | Jul 09 06:41:50 PM PDT 24 |
Peak memory | 213224 kb |
Host | smart-3814d550-3423-4919-b3d8-c425159fc90a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738402176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.738402176 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2066794099 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 35938940926 ps |
CPU time | 25.81 seconds |
Started | Jul 09 06:41:46 PM PDT 24 |
Finished | Jul 09 06:42:14 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-c917fcf6-eb4d-456d-bb05-b2f17d2bef84 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066794099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. rv_dm_jtag_dmi_csr_bit_bash.2066794099 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3823047099 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 9499613333 ps |
CPU time | 24.78 seconds |
Started | Jul 09 06:41:45 PM PDT 24 |
Finished | Jul 09 06:42:12 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-047342f1-dda0-44d8-bfe0-57a9e0032adc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823047099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3 823047099 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.398175375 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 331306528 ps |
CPU time | 1.43 seconds |
Started | Jul 09 06:41:45 PM PDT 24 |
Finished | Jul 09 06:41:48 PM PDT 24 |
Peak memory | 204684 kb |
Host | smart-f4bfb5af-3fc4-43ae-96ef-24550d7cb281 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398175375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.398175375 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.892161758 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 323879978 ps |
CPU time | 6.34 seconds |
Started | Jul 09 06:41:45 PM PDT 24 |
Finished | Jul 09 06:41:53 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-e44adb79-054a-4fdb-8c5e-656f75e6861a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892161758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c sr_outstanding.892161758 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2607367301 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 46254090437 ps |
CPU time | 81 seconds |
Started | Jul 09 06:41:45 PM PDT 24 |
Finished | Jul 09 06:43:08 PM PDT 24 |
Peak memory | 221464 kb |
Host | smart-c1a7a1f1-93fc-4ffd-b7f8-576ead5a6802 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607367301 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.2607367301 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3310767941 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 110368010 ps |
CPU time | 2.09 seconds |
Started | Jul 09 06:41:46 PM PDT 24 |
Finished | Jul 09 06:41:50 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-24d75737-04c3-41f4-a5ab-87c3fa37bf81 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310767941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3310767941 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1431037257 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 7682015603 ps |
CPU time | 9.78 seconds |
Started | Jul 09 06:41:45 PM PDT 24 |
Finished | Jul 09 06:41:56 PM PDT 24 |
Peak memory | 213280 kb |
Host | smart-e694cf55-bd41-4a85-9d23-0a3dc0f182f9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431037257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1431037257 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.178769331 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 336326344 ps |
CPU time | 2.47 seconds |
Started | Jul 09 06:41:51 PM PDT 24 |
Finished | Jul 09 06:41:55 PM PDT 24 |
Peak memory | 213316 kb |
Host | smart-c98adc57-7373-4dda-a4c5-debef1f95029 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178769331 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.178769331 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3302506834 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 211344087 ps |
CPU time | 2.55 seconds |
Started | Jul 09 06:41:49 PM PDT 24 |
Finished | Jul 09 06:41:54 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-565b5a7f-40e2-477f-b0b4-a6f33e52919a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302506834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3302506834 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1943813330 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 48269264097 ps |
CPU time | 126.75 seconds |
Started | Jul 09 06:41:52 PM PDT 24 |
Finished | Jul 09 06:44:00 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-998c06da-1d41-40ed-a775-b6bc8b35e15d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943813330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. rv_dm_jtag_dmi_csr_bit_bash.1943813330 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.633301043 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 2845255138 ps |
CPU time | 2.2 seconds |
Started | Jul 09 06:41:45 PM PDT 24 |
Finished | Jul 09 06:41:49 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-833ab495-2d77-473b-8f63-62909df2ddbc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633301043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.633301043 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3672189123 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 527165404 ps |
CPU time | 2.04 seconds |
Started | Jul 09 06:41:47 PM PDT 24 |
Finished | Jul 09 06:41:51 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-4c83bc40-70c0-4d55-b735-0998b1558fd2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672189123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3 672189123 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1139654029 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 162054860 ps |
CPU time | 3.52 seconds |
Started | Jul 09 06:41:50 PM PDT 24 |
Finished | Jul 09 06:41:56 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-a4a7a892-9501-46f0-b5c3-4621c1f42bde |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139654029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.1139654029 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.261525164 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 178051978 ps |
CPU time | 3.61 seconds |
Started | Jul 09 06:41:54 PM PDT 24 |
Finished | Jul 09 06:41:59 PM PDT 24 |
Peak memory | 213216 kb |
Host | smart-333a31f9-dcb4-4a81-b7c4-ba9960aebdf1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261525164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.261525164 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4233306282 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 964251251 ps |
CPU time | 11.51 seconds |
Started | Jul 09 06:41:55 PM PDT 24 |
Finished | Jul 09 06:42:07 PM PDT 24 |
Peak memory | 213256 kb |
Host | smart-465c444a-60e1-4c2b-b031-c86ddcce40a9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233306282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.4233306282 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3049796949 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 4343343784 ps |
CPU time | 5.23 seconds |
Started | Jul 09 06:41:56 PM PDT 24 |
Finished | Jul 09 06:42:02 PM PDT 24 |
Peak memory | 220548 kb |
Host | smart-3d16dcd8-a1f0-4525-874c-da209ed916dd |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049796949 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3049796949 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1213010835 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 104852481 ps |
CPU time | 2.13 seconds |
Started | Jul 09 06:41:56 PM PDT 24 |
Finished | Jul 09 06:41:59 PM PDT 24 |
Peak memory | 213184 kb |
Host | smart-778766c3-b014-4181-b054-a8907cd46045 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213010835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1213010835 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.541246701 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 116415728 ps |
CPU time | 0.72 seconds |
Started | Jul 09 06:41:52 PM PDT 24 |
Finished | Jul 09 06:41:54 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-17206f5e-296a-472a-8f32-2c6d34ca4933 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541246701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r v_dm_jtag_dmi_csr_bit_bash.541246701 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.137435299 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 1376793099 ps |
CPU time | 3.81 seconds |
Started | Jul 09 06:41:49 PM PDT 24 |
Finished | Jul 09 06:41:55 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-d69f1e6c-6670-4d79-8198-c927ce92b3a9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137435299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.137435299 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1254970126 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 366358057 ps |
CPU time | 1.13 seconds |
Started | Jul 09 06:41:50 PM PDT 24 |
Finished | Jul 09 06:41:53 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-8f0f9180-4a66-452a-a9e5-4d4317734d15 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254970126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1 254970126 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2903765478 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 1388708902 ps |
CPU time | 4.54 seconds |
Started | Jul 09 06:41:57 PM PDT 24 |
Finished | Jul 09 06:42:03 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-f103cfaa-d8e0-4c5b-b25e-8c204a6353e5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903765478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.2903765478 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3845974365 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 1237978830 ps |
CPU time | 6.99 seconds |
Started | Jul 09 06:41:51 PM PDT 24 |
Finished | Jul 09 06:42:00 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-68a4f729-f53f-478f-ace6-549374042f2a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845974365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3845974365 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.811261374 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 2369706204 ps |
CPU time | 10.68 seconds |
Started | Jul 09 06:41:56 PM PDT 24 |
Finished | Jul 09 06:42:07 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-51291715-80a5-4eee-aa3e-ef7e6b5182cf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811261374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.811261374 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.140393301 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 4647785944 ps |
CPU time | 5.4 seconds |
Started | Jul 09 06:42:00 PM PDT 24 |
Finished | Jul 09 06:42:07 PM PDT 24 |
Peak memory | 219808 kb |
Host | smart-ddced721-64ff-434a-882d-10388dff9cd8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140393301 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.140393301 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1693380601 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 230903450 ps |
CPU time | 2.42 seconds |
Started | Jul 09 06:42:00 PM PDT 24 |
Finished | Jul 09 06:42:03 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-ff109428-f243-4078-af9c-1123444a5db3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693380601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1693380601 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2212505229 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 43543998703 ps |
CPU time | 44.42 seconds |
Started | Jul 09 06:41:56 PM PDT 24 |
Finished | Jul 09 06:42:41 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-5f2bea26-bd22-4041-80be-1307c570bdab |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212505229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.2212505229 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2020544332 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 1019102455 ps |
CPU time | 3.28 seconds |
Started | Jul 09 06:41:57 PM PDT 24 |
Finished | Jul 09 06:42:01 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-6cac048f-a933-4537-8b7a-1b6da48f554a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020544332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2 020544332 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1571227722 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 614507590 ps |
CPU time | 1.12 seconds |
Started | Jul 09 06:41:56 PM PDT 24 |
Finished | Jul 09 06:41:59 PM PDT 24 |
Peak memory | 204748 kb |
Host | smart-d5ba62ff-d273-4c6b-97c3-23e1af23c92d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571227722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1 571227722 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.787227864 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 44086908281 ps |
CPU time | 38.84 seconds |
Started | Jul 09 06:41:56 PM PDT 24 |
Finished | Jul 09 06:42:36 PM PDT 24 |
Peak memory | 221452 kb |
Host | smart-95fe5180-1dcd-4b66-aa93-cbf8b778bf6a |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787227864 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.787227864 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2748744439 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 293454038 ps |
CPU time | 2.28 seconds |
Started | Jul 09 06:41:55 PM PDT 24 |
Finished | Jul 09 06:41:58 PM PDT 24 |
Peak memory | 213204 kb |
Host | smart-aff3263f-5b7f-42c1-840d-fd368844ba98 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748744439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2748744439 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3568048641 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 2948285053 ps |
CPU time | 18.3 seconds |
Started | Jul 09 06:42:01 PM PDT 24 |
Finished | Jul 09 06:42:20 PM PDT 24 |
Peak memory | 213540 kb |
Host | smart-ef72955a-d8f4-465d-8ef0-a53418c64958 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568048641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3568048641 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.4278310634 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 135787369 ps |
CPU time | 0.85 seconds |
Started | Jul 09 06:42:46 PM PDT 24 |
Finished | Jul 09 06:42:48 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-fc6fc131-afe5-4df5-8782-8faf9cd53f46 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278310634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.4278310634 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1114893313 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 5735619103 ps |
CPU time | 5.94 seconds |
Started | Jul 09 06:42:39 PM PDT 24 |
Finished | Jul 09 06:42:46 PM PDT 24 |
Peak memory | 213920 kb |
Host | smart-87d304e0-e72c-4bca-9bc1-ee52d4e9f09a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1114893313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1114893313 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2943781646 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 3465701032 ps |
CPU time | 3.8 seconds |
Started | Jul 09 06:42:37 PM PDT 24 |
Finished | Jul 09 06:42:42 PM PDT 24 |
Peak memory | 213872 kb |
Host | smart-50cfb52b-146e-4352-9957-49eeae621c37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2943781646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2943781646 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.2608775232 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 634326479 ps |
CPU time | 2.32 seconds |
Started | Jul 09 06:42:36 PM PDT 24 |
Finished | Jul 09 06:42:39 PM PDT 24 |
Peak memory | 205376 kb |
Host | smart-13e57e87-366f-439a-a382-eafa19436685 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608775232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2608775232 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2455076481 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 131077613 ps |
CPU time | 1.03 seconds |
Started | Jul 09 06:42:39 PM PDT 24 |
Finished | Jul 09 06:42:41 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-b511e8dc-5e94-4b5e-929b-f41e76941649 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2455076481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2455076481 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1414316561 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 1182879796 ps |
CPU time | 2.14 seconds |
Started | Jul 09 06:42:39 PM PDT 24 |
Finished | Jul 09 06:42:43 PM PDT 24 |
Peak memory | 213792 kb |
Host | smart-9bf490b5-edf7-4107-96d9-51ab538b8bfc |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1414316561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t l_access.1414316561 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3072660952 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 355658957 ps |
CPU time | 0.92 seconds |
Started | Jul 09 06:42:37 PM PDT 24 |
Finished | Jul 09 06:42:38 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-1c128878-bb86-478d-8758-1e4d65ba1561 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3072660952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3072660952 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.3344109399 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 285619997 ps |
CPU time | 1.48 seconds |
Started | Jul 09 06:42:40 PM PDT 24 |
Finished | Jul 09 06:42:43 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-1f7bc483-3418-44e7-9253-ad5a55359c62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3344109399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3344109399 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1112518949 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 452036015 ps |
CPU time | 1.15 seconds |
Started | Jul 09 06:42:45 PM PDT 24 |
Finished | Jul 09 06:42:47 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-38100044-6a87-40a5-abd6-3b4d685d7a63 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112518949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1112518949 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1811386947 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 698597116 ps |
CPU time | 2.66 seconds |
Started | Jul 09 06:42:45 PM PDT 24 |
Finished | Jul 09 06:42:49 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-21ca628a-b71c-4fff-b38f-7aefa7fc81a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1811386947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1811386947 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.959275829 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 869425009 ps |
CPU time | 1.2 seconds |
Started | Jul 09 06:42:45 PM PDT 24 |
Finished | Jul 09 06:42:48 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-64c19991-a04f-4012-afe9-93b56245ba84 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=959275829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.959275829 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2428931479 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 278192392 ps |
CPU time | 0.85 seconds |
Started | Jul 09 06:42:51 PM PDT 24 |
Finished | Jul 09 06:42:54 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-96083af9-5d1c-4d12-b773-f4108b7dc909 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428931479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2428931479 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.295570511 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 146991833 ps |
CPU time | 0.86 seconds |
Started | Jul 09 06:42:38 PM PDT 24 |
Finished | Jul 09 06:42:40 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-952e9cea-b616-42fd-950b-9d965b95cea1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=295570511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.295570511 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.659453613 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 797015306 ps |
CPU time | 2.41 seconds |
Started | Jul 09 06:42:39 PM PDT 24 |
Finished | Jul 09 06:42:42 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-67dc79c0-1df2-4310-b31d-dcf5361b1dbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=659453613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.659453613 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.3760783605 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 153306999 ps |
CPU time | 0.87 seconds |
Started | Jul 09 06:42:47 PM PDT 24 |
Finished | Jul 09 06:42:50 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-da143990-732f-42b6-b1cc-fae21c6a9f18 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760783605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3760783605 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.4285367608 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 214536772 ps |
CPU time | 1.29 seconds |
Started | Jul 09 06:42:45 PM PDT 24 |
Finished | Jul 09 06:42:47 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-fde88741-c40a-4e42-9c4f-b06f3d44c998 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4285367608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.4285367608 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.1766483112 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 56773866 ps |
CPU time | 0.88 seconds |
Started | Jul 09 06:43:56 PM PDT 24 |
Finished | Jul 09 06:43:58 PM PDT 24 |
Peak memory | 213628 kb |
Host | smart-d0197173-f1b5-4fa8-b549-bcdd7ddc6403 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1766483112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1766483112 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.3335392043 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 1133669770 ps |
CPU time | 1.19 seconds |
Started | Jul 09 06:42:47 PM PDT 24 |
Finished | Jul 09 06:42:50 PM PDT 24 |
Peak memory | 237484 kb |
Host | smart-d70d9533-7f39-4a4a-9276-4bf3e8fe4431 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335392043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3335392043 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.3222561901 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 3850178000 ps |
CPU time | 2.92 seconds |
Started | Jul 09 06:42:33 PM PDT 24 |
Finished | Jul 09 06:42:38 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-cd72a505-65b6-43d2-950d-3f0928ab98b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3222561901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3222561901 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all.2340426424 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 10298756914 ps |
CPU time | 13.28 seconds |
Started | Jul 09 06:42:47 PM PDT 24 |
Finished | Jul 09 06:43:02 PM PDT 24 |
Peak memory | 205552 kb |
Host | smart-90fba52f-4b3e-478f-b9c7-3df2fe059f9f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340426424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2340426424 |
Directory | /workspace/0.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.2447224795 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 5610220040 ps |
CPU time | 9.11 seconds |
Started | Jul 09 06:42:35 PM PDT 24 |
Finished | Jul 09 06:42:45 PM PDT 24 |
Peak memory | 205628 kb |
Host | smart-f66230ca-fe11-487b-b6df-9cc7b456ccba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447224795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2447224795 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.280136855 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 206756966 ps |
CPU time | 0.82 seconds |
Started | Jul 09 06:42:57 PM PDT 24 |
Finished | Jul 09 06:43:00 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-e3fc5678-142b-47b2-b13d-6fbb30ae0931 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=280136855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.280136855 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.2851646248 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 166932737 ps |
CPU time | 1.14 seconds |
Started | Jul 09 06:42:59 PM PDT 24 |
Finished | Jul 09 06:43:03 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-2628f6e3-8845-466b-a279-28f69b0d739f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851646248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2851646248 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.450629794 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 11390322780 ps |
CPU time | 30.63 seconds |
Started | Jul 09 06:42:49 PM PDT 24 |
Finished | Jul 09 06:43:22 PM PDT 24 |
Peak memory | 213876 kb |
Host | smart-8c645636-8cdb-45bf-8e33-d472e6d97fb7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=450629794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.450629794 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.599038251 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 8708828512 ps |
CPU time | 3.12 seconds |
Started | Jul 09 06:42:51 PM PDT 24 |
Finished | Jul 09 06:42:56 PM PDT 24 |
Peak memory | 213936 kb |
Host | smart-d1e6baca-6bb5-49f7-94c9-0f73522f7561 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=599038251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.599038251 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.2633775520 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 282224788 ps |
CPU time | 1.43 seconds |
Started | Jul 09 06:42:50 PM PDT 24 |
Finished | Jul 09 06:42:54 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-84221f4a-f657-4281-98a9-58b342dfe9bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2633775520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2633775520 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.3630392319 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 2404160123 ps |
CPU time | 7.02 seconds |
Started | Jul 09 06:42:50 PM PDT 24 |
Finished | Jul 09 06:42:59 PM PDT 24 |
Peak memory | 205400 kb |
Host | smart-11536aba-b7e3-43fd-aec7-fe8837b5a014 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3630392319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3630392319 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3991900505 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 510757176 ps |
CPU time | 1.52 seconds |
Started | Jul 09 06:42:49 PM PDT 24 |
Finished | Jul 09 06:42:53 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-e88cc49c-60c5-4e0f-9476-dd89df50568d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3991900505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3991900505 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.806913466 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 767658000 ps |
CPU time | 2.6 seconds |
Started | Jul 09 06:42:51 PM PDT 24 |
Finished | Jul 09 06:42:56 PM PDT 24 |
Peak memory | 205380 kb |
Host | smart-2f299264-684a-4a81-be20-07e37a89ce62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=806913466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.806913466 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2310789761 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 286944419 ps |
CPU time | 0.79 seconds |
Started | Jul 09 06:42:50 PM PDT 24 |
Finished | Jul 09 06:42:53 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-075ecfdd-09f8-45fa-a293-eb537e836135 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310789761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2310789761 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3381908382 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 2322034518 ps |
CPU time | 6.53 seconds |
Started | Jul 09 06:42:52 PM PDT 24 |
Finished | Jul 09 06:43:00 PM PDT 24 |
Peak memory | 213852 kb |
Host | smart-b00eec84-1634-493d-a5a6-08b9ddd7a0e9 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3381908382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t l_access.3381908382 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.4034548921 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 1387101138 ps |
CPU time | 1.46 seconds |
Started | Jul 09 06:42:52 PM PDT 24 |
Finished | Jul 09 06:42:55 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-5ab73a35-1b61-4d7f-8f36-9bf373bf6e45 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4034548921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.4034548921 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.1352742926 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 307493826 ps |
CPU time | 1.51 seconds |
Started | Jul 09 06:42:51 PM PDT 24 |
Finished | Jul 09 06:42:54 PM PDT 24 |
Peak memory | 205508 kb |
Host | smart-cc2fbfaf-0c87-4d75-8ede-b5e41ab3f349 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1352742926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1352742926 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1515281553 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 1041634085 ps |
CPU time | 1.17 seconds |
Started | Jul 09 06:42:50 PM PDT 24 |
Finished | Jul 09 06:42:53 PM PDT 24 |
Peak memory | 205576 kb |
Host | smart-b8ae9d80-3f81-442c-bf75-34e1f7507cda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1515281553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1515281553 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2235172942 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 2642719192 ps |
CPU time | 3.02 seconds |
Started | Jul 09 06:42:55 PM PDT 24 |
Finished | Jul 09 06:43:00 PM PDT 24 |
Peak memory | 205576 kb |
Host | smart-c526708e-03df-4fd5-8b4a-18d62ee18d99 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2235172942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2235172942 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3324352139 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 549574800 ps |
CPU time | 1.96 seconds |
Started | Jul 09 06:42:55 PM PDT 24 |
Finished | Jul 09 06:42:59 PM PDT 24 |
Peak memory | 204648 kb |
Host | smart-56138177-d57b-4076-a930-497be16aa370 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3324352139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3324352139 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2572134443 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 505230413 ps |
CPU time | 0.94 seconds |
Started | Jul 09 06:42:55 PM PDT 24 |
Finished | Jul 09 06:42:58 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-28862682-db26-4724-af1e-cfb112c2b105 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572134443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2572134443 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2087818958 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 214132426 ps |
CPU time | 1.26 seconds |
Started | Jul 09 06:42:49 PM PDT 24 |
Finished | Jul 09 06:42:53 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-f5ebb2c4-2693-47bf-8454-d96344302689 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2087818958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2087818958 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.516468917 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 240806117 ps |
CPU time | 1.25 seconds |
Started | Jul 09 06:42:50 PM PDT 24 |
Finished | Jul 09 06:42:54 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-b5748efa-f706-4a2c-9e7e-4eb59358a5ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=516468917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.516468917 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3514517652 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 3386770167 ps |
CPU time | 2.75 seconds |
Started | Jul 09 06:42:50 PM PDT 24 |
Finished | Jul 09 06:42:55 PM PDT 24 |
Peak memory | 205616 kb |
Host | smart-72cd92c8-070b-4b76-9668-8bc3c708deb9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3514517652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3514517652 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.267593440 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 679228723 ps |
CPU time | 2.49 seconds |
Started | Jul 09 06:42:59 PM PDT 24 |
Finished | Jul 09 06:43:04 PM PDT 24 |
Peak memory | 229464 kb |
Host | smart-174ab797-7fec-45ca-8294-f64d810166b9 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267593440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.267593440 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.675961406 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 2770769275 ps |
CPU time | 2.22 seconds |
Started | Jul 09 06:42:50 PM PDT 24 |
Finished | Jul 09 06:42:55 PM PDT 24 |
Peak memory | 205664 kb |
Host | smart-bbd20589-398d-4afa-a1e8-1b24421462bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=675961406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.675961406 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.145261030 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 116117381 ps |
CPU time | 0.75 seconds |
Started | Jul 09 06:43:17 PM PDT 24 |
Finished | Jul 09 06:43:21 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-0c234e05-668e-4b89-beaa-8671a394f8c4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145261030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.145261030 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3658552596 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 19386073587 ps |
CPU time | 47.73 seconds |
Started | Jul 09 06:43:16 PM PDT 24 |
Finished | Jul 09 06:44:07 PM PDT 24 |
Peak memory | 213920 kb |
Host | smart-72538dbe-1eff-4dca-a415-4aabc68f05a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3658552596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3658552596 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2686550905 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 2699655223 ps |
CPU time | 7.14 seconds |
Started | Jul 09 06:43:15 PM PDT 24 |
Finished | Jul 09 06:43:25 PM PDT 24 |
Peak memory | 213920 kb |
Host | smart-381b8dc0-a332-4634-bdcf-ea978474c60d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2686550905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_ tl_access.2686550905 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.1765246008 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 4898800851 ps |
CPU time | 15 seconds |
Started | Jul 09 06:43:18 PM PDT 24 |
Finished | Jul 09 06:43:37 PM PDT 24 |
Peak memory | 205552 kb |
Host | smart-007c0ac8-3d41-405d-955a-fe6eaf915360 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765246008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1765246008 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.1429560623 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 63560650 ps |
CPU time | 0.73 seconds |
Started | Jul 09 06:43:17 PM PDT 24 |
Finished | Jul 09 06:43:21 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-2c7a46f0-ca08-409e-b2c2-afeceb74a22f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429560623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1429560623 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2024811423 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 15530572384 ps |
CPU time | 46.73 seconds |
Started | Jul 09 06:43:21 PM PDT 24 |
Finished | Jul 09 06:44:11 PM PDT 24 |
Peak memory | 213960 kb |
Host | smart-fde9ce71-fef8-46a7-a4ba-49c21ae1b907 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2024811423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2024811423 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.3483242253 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 1368319756 ps |
CPU time | 4.54 seconds |
Started | Jul 09 06:43:21 PM PDT 24 |
Finished | Jul 09 06:43:29 PM PDT 24 |
Peak memory | 205600 kb |
Host | smart-7304a33e-5c35-4256-8e9c-bd2e73122762 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3483242253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3483242253 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3031161584 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 6332025370 ps |
CPU time | 17.89 seconds |
Started | Jul 09 06:43:17 PM PDT 24 |
Finished | Jul 09 06:43:39 PM PDT 24 |
Peak memory | 222028 kb |
Host | smart-3eb2a025-134d-48aa-8d5f-7179c44911cb |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3031161584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.3031161584 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.631448904 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 10157376783 ps |
CPU time | 13.65 seconds |
Started | Jul 09 06:43:17 PM PDT 24 |
Finished | Jul 09 06:43:34 PM PDT 24 |
Peak memory | 213820 kb |
Host | smart-8f81123e-5efd-4748-850f-f8d332441f0f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631448904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.631448904 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.3413837179 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 6595530271 ps |
CPU time | 6.57 seconds |
Started | Jul 09 06:43:17 PM PDT 24 |
Finished | Jul 09 06:43:27 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-bef7fba8-0446-491b-a43f-17abea4701e4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413837179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3413837179 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.3317682680 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 39519064 ps |
CPU time | 0.76 seconds |
Started | Jul 09 06:43:24 PM PDT 24 |
Finished | Jul 09 06:43:29 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-106f82e6-63d2-44f6-838e-d3d0060f3b02 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317682680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3317682680 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.16383236 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 43697158908 ps |
CPU time | 107.88 seconds |
Started | Jul 09 06:43:17 PM PDT 24 |
Finished | Jul 09 06:45:07 PM PDT 24 |
Peak memory | 213940 kb |
Host | smart-3fc81183-0904-407f-8f2d-1b7e6e20c809 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=16383236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.16383236 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.4249948434 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 1984071896 ps |
CPU time | 5.41 seconds |
Started | Jul 09 06:43:17 PM PDT 24 |
Finished | Jul 09 06:43:25 PM PDT 24 |
Peak memory | 205520 kb |
Host | smart-3ab211fd-c076-4071-bfcc-900e2ebff459 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4249948434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.4249948434 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3752673104 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 2852981487 ps |
CPU time | 8.25 seconds |
Started | Jul 09 06:43:17 PM PDT 24 |
Finished | Jul 09 06:43:29 PM PDT 24 |
Peak memory | 213812 kb |
Host | smart-2d1919e2-e154-427f-99ca-9ee9551bfdc3 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3752673104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_ tl_access.3752673104 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.3968583567 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 2903317848 ps |
CPU time | 5.76 seconds |
Started | Jul 09 06:43:16 PM PDT 24 |
Finished | Jul 09 06:43:25 PM PDT 24 |
Peak memory | 213868 kb |
Host | smart-7a08b1ea-8b18-4e1c-bf76-689c8dec841c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968583567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3968583567 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_stress_all.3681677527 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 4345921690 ps |
CPU time | 3.74 seconds |
Started | Jul 09 06:43:24 PM PDT 24 |
Finished | Jul 09 06:43:32 PM PDT 24 |
Peak memory | 213748 kb |
Host | smart-1b586603-2cac-4bd7-bb41-1baec581860d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681677527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3681677527 |
Directory | /workspace/12.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.746179569 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 141887989 ps |
CPU time | 0.76 seconds |
Started | Jul 09 06:43:24 PM PDT 24 |
Finished | Jul 09 06:43:29 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-8c2dfefb-8d7d-44b4-bcab-0fd2e5c0d321 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746179569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.746179569 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1711238230 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 13655232950 ps |
CPU time | 27.42 seconds |
Started | Jul 09 06:43:22 PM PDT 24 |
Finished | Jul 09 06:43:54 PM PDT 24 |
Peak memory | 213928 kb |
Host | smart-25100439-31ed-4ffc-8ac0-9ee08b7dc388 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711238230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1711238230 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.106277719 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 5379860909 ps |
CPU time | 13.11 seconds |
Started | Jul 09 06:43:23 PM PDT 24 |
Finished | Jul 09 06:43:40 PM PDT 24 |
Peak memory | 213868 kb |
Host | smart-c8429b48-3d00-4971-9886-d63a14348702 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=106277719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.106277719 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3804276803 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 596289986 ps |
CPU time | 1.71 seconds |
Started | Jul 09 06:43:21 PM PDT 24 |
Finished | Jul 09 06:43:27 PM PDT 24 |
Peak memory | 205624 kb |
Host | smart-eee16ce1-453a-47a3-a63a-63291a97705a |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3804276803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_ tl_access.3804276803 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.3388592995 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 5794664468 ps |
CPU time | 4.86 seconds |
Started | Jul 09 06:43:22 PM PDT 24 |
Finished | Jul 09 06:43:31 PM PDT 24 |
Peak memory | 213848 kb |
Host | smart-8d56dd75-dad8-415d-a5a2-6c874e07285b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388592995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3388592995 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.2436586997 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 173312014 ps |
CPU time | 0.79 seconds |
Started | Jul 09 06:43:22 PM PDT 24 |
Finished | Jul 09 06:43:26 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-6ef000f0-cdb4-47ca-a72d-cbbf9262b2f4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436586997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2436586997 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4019317305 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 557178406 ps |
CPU time | 1.35 seconds |
Started | Jul 09 06:43:23 PM PDT 24 |
Finished | Jul 09 06:43:28 PM PDT 24 |
Peak memory | 205500 kb |
Host | smart-4a242da0-6f70-45cf-84b4-77c95ad238a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4019317305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.4019317305 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.495701641 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 2299329819 ps |
CPU time | 4.42 seconds |
Started | Jul 09 06:43:23 PM PDT 24 |
Finished | Jul 09 06:43:31 PM PDT 24 |
Peak memory | 213800 kb |
Host | smart-d9671086-9c70-49dc-8516-924b6a71db12 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=495701641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t l_access.495701641 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.3364191799 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 3447482723 ps |
CPU time | 1.81 seconds |
Started | Jul 09 06:43:21 PM PDT 24 |
Finished | Jul 09 06:43:26 PM PDT 24 |
Peak memory | 213844 kb |
Host | smart-c013352a-c474-420e-a612-cc7afe3e837f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3364191799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3364191799 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.461800928 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 32197962 ps |
CPU time | 0.79 seconds |
Started | Jul 09 06:43:28 PM PDT 24 |
Finished | Jul 09 06:43:31 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-dd5dd59f-a614-4f27-a5e5-f6eaf7fd990a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461800928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.461800928 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.645639697 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 2365207157 ps |
CPU time | 6.81 seconds |
Started | Jul 09 06:43:23 PM PDT 24 |
Finished | Jul 09 06:43:34 PM PDT 24 |
Peak memory | 213896 kb |
Host | smart-63fe38b3-1475-4cbc-8c8e-b2ae05acce96 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645639697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.645639697 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.4034031395 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 4906021110 ps |
CPU time | 3.69 seconds |
Started | Jul 09 06:43:22 PM PDT 24 |
Finished | Jul 09 06:43:30 PM PDT 24 |
Peak memory | 213900 kb |
Host | smart-c3ee291e-1147-4eee-b1c6-30a5f2ccbe2e |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4034031395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_ tl_access.4034031395 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.1644949877 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 8926176605 ps |
CPU time | 23.49 seconds |
Started | Jul 09 06:43:22 PM PDT 24 |
Finished | Jul 09 06:43:50 PM PDT 24 |
Peak memory | 205724 kb |
Host | smart-e3e5f391-8daa-4a57-a9fc-ba66cd8d1954 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1644949877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1644949877 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_stress_all.3931611550 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 3014243196 ps |
CPU time | 3.78 seconds |
Started | Jul 09 06:43:28 PM PDT 24 |
Finished | Jul 09 06:43:34 PM PDT 24 |
Peak memory | 213684 kb |
Host | smart-d704d3a6-6c4b-4386-bfd9-89e80d465272 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931611550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3931611550 |
Directory | /workspace/15.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.3962361361 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 37429879 ps |
CPU time | 0.77 seconds |
Started | Jul 09 06:43:28 PM PDT 24 |
Finished | Jul 09 06:43:31 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-bcc92ff0-1d6f-4edf-9d61-081ae7f39847 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962361361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3962361361 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1138697077 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 3214898200 ps |
CPU time | 9.63 seconds |
Started | Jul 09 06:43:28 PM PDT 24 |
Finished | Jul 09 06:43:40 PM PDT 24 |
Peak memory | 205636 kb |
Host | smart-d5d86fc6-cd4a-46db-bff0-905923b78d1a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1138697077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1138697077 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3717203738 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 8933807796 ps |
CPU time | 7.02 seconds |
Started | Jul 09 06:43:26 PM PDT 24 |
Finished | Jul 09 06:43:36 PM PDT 24 |
Peak memory | 205672 kb |
Host | smart-cbaed977-f998-4cda-b88f-a42f2b34f00e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3717203738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3717203738 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3300948047 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 6113298080 ps |
CPU time | 16.57 seconds |
Started | Jul 09 06:43:28 PM PDT 24 |
Finished | Jul 09 06:43:47 PM PDT 24 |
Peak memory | 213884 kb |
Host | smart-f6f8c924-d216-47ac-aef3-eaa698f82be4 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3300948047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_ tl_access.3300948047 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.617719193 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 1882793549 ps |
CPU time | 3.57 seconds |
Started | Jul 09 06:43:30 PM PDT 24 |
Finished | Jul 09 06:43:35 PM PDT 24 |
Peak memory | 205648 kb |
Host | smart-f86aa7cd-92e0-4c67-b86f-1c030a7876a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=617719193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.617719193 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.3447586330 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 2990898344 ps |
CPU time | 5.25 seconds |
Started | Jul 09 06:43:26 PM PDT 24 |
Finished | Jul 09 06:43:35 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-10606091-cc15-4b24-9d1d-9511d3903e05 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447586330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3447586330 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.1829258670 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 64050342 ps |
CPU time | 0.74 seconds |
Started | Jul 09 06:43:34 PM PDT 24 |
Finished | Jul 09 06:43:36 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-38832b90-bb47-474a-ad48-20c463922b90 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829258670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1829258670 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.327281913 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 5574150731 ps |
CPU time | 8.32 seconds |
Started | Jul 09 06:43:28 PM PDT 24 |
Finished | Jul 09 06:43:39 PM PDT 24 |
Peak memory | 205656 kb |
Host | smart-07d42dc3-0b71-4aa8-baaf-148242e95979 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=327281913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t l_access.327281913 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.3813806639 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 3701101675 ps |
CPU time | 3.5 seconds |
Started | Jul 09 06:43:30 PM PDT 24 |
Finished | Jul 09 06:43:35 PM PDT 24 |
Peak memory | 205652 kb |
Host | smart-d223172c-4272-4036-be14-0a0386a1bd08 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3813806639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3813806639 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.2468571854 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 100449518 ps |
CPU time | 0.67 seconds |
Started | Jul 09 06:43:34 PM PDT 24 |
Finished | Jul 09 06:43:37 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-e2474e53-58de-4679-8f6a-f89e4c3aac13 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468571854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2468571854 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.724988627 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 92087851865 ps |
CPU time | 92.54 seconds |
Started | Jul 09 06:43:32 PM PDT 24 |
Finished | Jul 09 06:45:05 PM PDT 24 |
Peak memory | 221940 kb |
Host | smart-bf1a754d-e14c-421a-828f-240db04e368b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724988627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.724988627 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2236980916 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 6600193955 ps |
CPU time | 17.43 seconds |
Started | Jul 09 06:43:31 PM PDT 24 |
Finished | Jul 09 06:43:49 PM PDT 24 |
Peak memory | 205716 kb |
Host | smart-38cd4cbf-0541-49e0-a42e-ea974cf1ad32 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2236980916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_ tl_access.2236980916 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.752557397 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 12526598321 ps |
CPU time | 31.55 seconds |
Started | Jul 09 06:43:33 PM PDT 24 |
Finished | Jul 09 06:44:05 PM PDT 24 |
Peak memory | 205732 kb |
Host | smart-bc31b389-09af-40ef-8374-fcd77b70fd6f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=752557397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.752557397 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.3995308313 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 120266066 ps |
CPU time | 0.93 seconds |
Started | Jul 09 06:43:33 PM PDT 24 |
Finished | Jul 09 06:43:36 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-d13b478a-e28a-4b22-be78-c15300e9849d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995308313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3995308313 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2991413205 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 2024654290 ps |
CPU time | 2.82 seconds |
Started | Jul 09 06:43:34 PM PDT 24 |
Finished | Jul 09 06:43:39 PM PDT 24 |
Peak memory | 205596 kb |
Host | smart-ad3a1f1c-4fd3-4aac-9c6f-2ed4baa721d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2991413205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2991413205 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.219201997 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 5563371623 ps |
CPU time | 16.18 seconds |
Started | Jul 09 06:43:34 PM PDT 24 |
Finished | Jul 09 06:43:52 PM PDT 24 |
Peak memory | 213812 kb |
Host | smart-999263a0-9d4d-4b5b-aab5-9a2fb79b602e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219201997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.219201997 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2793795081 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 848316266 ps |
CPU time | 3.06 seconds |
Started | Jul 09 06:43:31 PM PDT 24 |
Finished | Jul 09 06:43:35 PM PDT 24 |
Peak memory | 205812 kb |
Host | smart-c9e0efcd-1a10-4950-986e-03d562613530 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2793795081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.2793795081 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.1120286351 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 2465818265 ps |
CPU time | 3.94 seconds |
Started | Jul 09 06:43:33 PM PDT 24 |
Finished | Jul 09 06:43:39 PM PDT 24 |
Peak memory | 205676 kb |
Host | smart-6554e281-d1bb-4117-87b0-2d0a98edf57b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120286351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1120286351 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.762827353 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 70953873 ps |
CPU time | 0.72 seconds |
Started | Jul 09 06:42:55 PM PDT 24 |
Finished | Jul 09 06:42:57 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-0fd655e5-5599-4314-ac63-fa49c9749160 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762827353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.762827353 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.828552884 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 6632331552 ps |
CPU time | 6.37 seconds |
Started | Jul 09 06:42:55 PM PDT 24 |
Finished | Jul 09 06:43:03 PM PDT 24 |
Peak memory | 213924 kb |
Host | smart-f40cbeb4-f105-4bfb-bcd3-fb3887e4f74e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=828552884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.828552884 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1192657711 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 5877161866 ps |
CPU time | 7.15 seconds |
Started | Jul 09 06:42:55 PM PDT 24 |
Finished | Jul 09 06:43:05 PM PDT 24 |
Peak memory | 214160 kb |
Host | smart-828adcc8-65f8-4f4d-bdb3-9b80d283f681 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1192657711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1192657711 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3263766156 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 893973073 ps |
CPU time | 2.21 seconds |
Started | Jul 09 06:42:58 PM PDT 24 |
Finished | Jul 09 06:43:03 PM PDT 24 |
Peak memory | 205564 kb |
Host | smart-230767f6-68f0-4a96-a0ba-6f7c3b7394e3 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3263766156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t l_access.3263766156 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.318227452 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 1059824613 ps |
CPU time | 1.48 seconds |
Started | Jul 09 06:42:57 PM PDT 24 |
Finished | Jul 09 06:43:00 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-45fc19cc-85c5-46a8-9d2f-ee32dc1b2ef9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=318227452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.318227452 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.153863223 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 12376832734 ps |
CPU time | 16.87 seconds |
Started | Jul 09 06:42:56 PM PDT 24 |
Finished | Jul 09 06:43:16 PM PDT 24 |
Peak memory | 222012 kb |
Host | smart-8b0092c2-98fc-4d3c-880f-9c1c5876aed6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=153863223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.153863223 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.2429999382 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 541939150 ps |
CPU time | 1.78 seconds |
Started | Jul 09 06:42:57 PM PDT 24 |
Finished | Jul 09 06:43:01 PM PDT 24 |
Peak memory | 237208 kb |
Host | smart-23fab9dc-a181-4a90-a8c1-6dc8c8c04a13 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429999382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2429999382 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.2473260592 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 61298476 ps |
CPU time | 0.8 seconds |
Started | Jul 09 06:43:33 PM PDT 24 |
Finished | Jul 09 06:43:36 PM PDT 24 |
Peak memory | 205368 kb |
Host | smart-3d0e92e9-5b02-4932-bee6-035597287565 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473260592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2473260592 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.955701602 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 165331600 ps |
CPU time | 0.87 seconds |
Started | Jul 09 06:43:39 PM PDT 24 |
Finished | Jul 09 06:43:41 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-f18240e0-2451-4dfd-a51a-3793d2595ceb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955701602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.955701602 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.1220225737 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 231829247 ps |
CPU time | 0.78 seconds |
Started | Jul 09 06:43:45 PM PDT 24 |
Finished | Jul 09 06:43:47 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-605a6ae7-ccdf-442d-97fc-61ae6e62d433 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220225737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1220225737 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.3454572360 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 97094593 ps |
CPU time | 0.77 seconds |
Started | Jul 09 06:43:43 PM PDT 24 |
Finished | Jul 09 06:43:45 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-3bcc0b3c-a803-48d1-bc8d-09133935535c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454572360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3454572360 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.1273558540 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 2747257499 ps |
CPU time | 8.54 seconds |
Started | Jul 09 06:43:38 PM PDT 24 |
Finished | Jul 09 06:43:48 PM PDT 24 |
Peak memory | 205620 kb |
Host | smart-1fb935a0-251b-4be1-a72c-6a6f02b648c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273558540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1273558540 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.3397638189 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 93854553 ps |
CPU time | 0.85 seconds |
Started | Jul 09 06:43:42 PM PDT 24 |
Finished | Jul 09 06:43:44 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-008f2e1c-cad9-4176-9625-f67faaaf8d5a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397638189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3397638189 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_stress_all.507583117 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 3726627473 ps |
CPU time | 4.45 seconds |
Started | Jul 09 06:43:39 PM PDT 24 |
Finished | Jul 09 06:43:46 PM PDT 24 |
Peak memory | 205600 kb |
Host | smart-3d7bfdbf-3a46-498a-8ed1-a890bfa6255e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507583117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.507583117 |
Directory | /workspace/24.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.2314693121 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 46561824 ps |
CPU time | 0.79 seconds |
Started | Jul 09 06:43:42 PM PDT 24 |
Finished | Jul 09 06:43:44 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-6fdecd8e-14db-477f-99a1-919e4794d59b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314693121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2314693121 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.237861583 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 7751196233 ps |
CPU time | 7.8 seconds |
Started | Jul 09 06:43:45 PM PDT 24 |
Finished | Jul 09 06:43:54 PM PDT 24 |
Peak memory | 213772 kb |
Host | smart-ef4c488b-0010-42a9-8cf0-ef259b8f7257 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237861583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.237861583 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.1992351638 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 150029459 ps |
CPU time | 0.75 seconds |
Started | Jul 09 06:43:40 PM PDT 24 |
Finished | Jul 09 06:43:43 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-b90ea919-a27a-4e0c-8537-d49372e131fe |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992351638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1992351638 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.4186430657 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 31553270 ps |
CPU time | 0.73 seconds |
Started | Jul 09 06:43:45 PM PDT 24 |
Finished | Jul 09 06:43:47 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-305cc3df-3b48-4309-85c0-c0a902564f78 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186430657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.4186430657 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.2618832195 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 8303994118 ps |
CPU time | 14.27 seconds |
Started | Jul 09 06:43:37 PM PDT 24 |
Finished | Jul 09 06:43:52 PM PDT 24 |
Peak memory | 213752 kb |
Host | smart-de590718-4b3b-4821-bd23-02fc6773350d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618832195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2618832195 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.645526666 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 130381442 ps |
CPU time | 0.91 seconds |
Started | Jul 09 06:43:40 PM PDT 24 |
Finished | Jul 09 06:43:43 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-06248b8c-e04e-41c9-bdd7-6ea15ea4120b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645526666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.645526666 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.3094161532 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 174245175 ps |
CPU time | 0.72 seconds |
Started | Jul 09 06:43:40 PM PDT 24 |
Finished | Jul 09 06:43:42 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-90dad268-9815-4a9b-b69d-a30d1cd1645e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094161532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3094161532 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/29.rv_dm_stress_all.2356407264 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 2289801340 ps |
CPU time | 2.72 seconds |
Started | Jul 09 06:43:43 PM PDT 24 |
Finished | Jul 09 06:43:47 PM PDT 24 |
Peak memory | 205536 kb |
Host | smart-b84404d6-0e59-443c-84b5-328959d41308 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356407264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.2356407264 |
Directory | /workspace/29.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.192171713 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 78530981 ps |
CPU time | 0.88 seconds |
Started | Jul 09 06:43:03 PM PDT 24 |
Finished | Jul 09 06:43:06 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-1e407396-5277-4f5b-9ad1-25d2a22d0092 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192171713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.192171713 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3440469890 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 2403454467 ps |
CPU time | 2.86 seconds |
Started | Jul 09 06:43:01 PM PDT 24 |
Finished | Jul 09 06:43:07 PM PDT 24 |
Peak memory | 205740 kb |
Host | smart-3ed54300-5072-45b5-a624-76c51d4d268a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3440469890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3440469890 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1000572591 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 1259963911 ps |
CPU time | 2.33 seconds |
Started | Jul 09 06:43:01 PM PDT 24 |
Finished | Jul 09 06:43:06 PM PDT 24 |
Peak memory | 213848 kb |
Host | smart-79596392-71d0-46df-b794-d85cde183228 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000572591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1000572591 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.190317332 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 7986308692 ps |
CPU time | 6.66 seconds |
Started | Jul 09 06:43:05 PM PDT 24 |
Finished | Jul 09 06:43:13 PM PDT 24 |
Peak memory | 205584 kb |
Host | smart-2ec28385-ef06-4f8d-8b0d-caa15c1bc6fc |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=190317332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl _access.190317332 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.2466708597 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 131895325 ps |
CPU time | 0.97 seconds |
Started | Jul 09 06:43:01 PM PDT 24 |
Finished | Jul 09 06:43:05 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-042d03ec-a5b8-4829-a56b-388c18a3a1c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466708597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2466708597 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.2780384354 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 13465525890 ps |
CPU time | 25.14 seconds |
Started | Jul 09 06:43:01 PM PDT 24 |
Finished | Jul 09 06:43:29 PM PDT 24 |
Peak memory | 205624 kb |
Host | smart-5fcd8886-ec43-4333-98cb-143fbcf4d1e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2780384354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2780384354 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.1055100624 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 791763893 ps |
CPU time | 3.09 seconds |
Started | Jul 09 06:43:02 PM PDT 24 |
Finished | Jul 09 06:43:08 PM PDT 24 |
Peak memory | 229452 kb |
Host | smart-504097fa-5d95-40a8-8078-c8e17f3ee7ce |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055100624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1055100624 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.3465712674 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 58839017 ps |
CPU time | 0.7 seconds |
Started | Jul 09 06:43:38 PM PDT 24 |
Finished | Jul 09 06:43:40 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-8cfc12c6-9b03-4d69-acca-4fc7b5038d25 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465712674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3465712674 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.2641699333 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 140155587 ps |
CPU time | 1.01 seconds |
Started | Jul 09 06:43:45 PM PDT 24 |
Finished | Jul 09 06:43:47 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-f6552d93-e3e3-4aaa-9e4e-a28bc466984e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641699333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2641699333 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.2842630167 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 133197552 ps |
CPU time | 0.73 seconds |
Started | Jul 09 06:43:39 PM PDT 24 |
Finished | Jul 09 06:43:42 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-46c2fcf8-b920-48e9-8acb-94078ec2bfb3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842630167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2842630167 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.3558042208 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 138902083 ps |
CPU time | 0.75 seconds |
Started | Jul 09 06:43:45 PM PDT 24 |
Finished | Jul 09 06:43:48 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-3c86e426-4be6-42f8-bf58-02b3fac16264 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558042208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3558042208 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.4047461385 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 140715728 ps |
CPU time | 0.76 seconds |
Started | Jul 09 06:43:47 PM PDT 24 |
Finished | Jul 09 06:43:49 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-42a07fb9-0e58-4bcb-aa71-646d0a87d19e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047461385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.4047461385 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.1752048416 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 40055023 ps |
CPU time | 0.78 seconds |
Started | Jul 09 06:43:46 PM PDT 24 |
Finished | Jul 09 06:43:48 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-717cfff6-d4d7-4396-896b-d6efe2d2219f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752048416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1752048416 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.2463835029 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 46730519 ps |
CPU time | 0.77 seconds |
Started | Jul 09 06:43:48 PM PDT 24 |
Finished | Jul 09 06:43:50 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-b2e13f24-f83c-4dd3-a95c-080ab734fcbf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463835029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2463835029 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_stress_all.1256365502 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 11338613684 ps |
CPU time | 33.91 seconds |
Started | Jul 09 06:43:45 PM PDT 24 |
Finished | Jul 09 06:44:21 PM PDT 24 |
Peak memory | 213724 kb |
Host | smart-5fb413c7-a9e3-42c7-96dc-b68febc37af0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256365502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1256365502 |
Directory | /workspace/36.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.2949703127 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 63996092 ps |
CPU time | 0.76 seconds |
Started | Jul 09 06:43:44 PM PDT 24 |
Finished | Jul 09 06:43:46 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-7fff91a9-c961-4f56-bd21-b1351cc7294f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949703127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2949703127 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_stress_all.2983007812 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 15693178903 ps |
CPU time | 14.03 seconds |
Started | Jul 09 06:43:45 PM PDT 24 |
Finished | Jul 09 06:44:01 PM PDT 24 |
Peak memory | 205464 kb |
Host | smart-c4af341f-5da0-4726-a8eb-121b4beec749 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983007812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2983007812 |
Directory | /workspace/37.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.1571634127 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 69470349 ps |
CPU time | 0.71 seconds |
Started | Jul 09 06:43:46 PM PDT 24 |
Finished | Jul 09 06:43:49 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-66a70fce-bdf7-4659-b854-117583966554 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571634127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1571634127 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_stress_all.1945396126 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 2112479486 ps |
CPU time | 6.32 seconds |
Started | Jul 09 06:43:44 PM PDT 24 |
Finished | Jul 09 06:43:51 PM PDT 24 |
Peak memory | 205588 kb |
Host | smart-5f4216bd-fe8a-4f2a-b2f3-3b11f771659c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945396126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1945396126 |
Directory | /workspace/38.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.1714739506 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 63697832 ps |
CPU time | 0.73 seconds |
Started | Jul 09 06:43:46 PM PDT 24 |
Finished | Jul 09 06:43:48 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-b094585e-bd33-433e-9174-2083c9300829 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714739506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1714739506 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.801047721 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 5869779337 ps |
CPU time | 15.49 seconds |
Started | Jul 09 06:43:44 PM PDT 24 |
Finished | Jul 09 06:44:01 PM PDT 24 |
Peak memory | 213816 kb |
Host | smart-f6323769-a244-4a12-a796-8728b910f013 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801047721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.801047721 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.3213975327 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 353453754 ps |
CPU time | 0.8 seconds |
Started | Jul 09 06:43:09 PM PDT 24 |
Finished | Jul 09 06:43:11 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-7587d800-184c-425b-a487-b16c833af4b7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213975327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3213975327 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1052983499 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 13440843935 ps |
CPU time | 23.93 seconds |
Started | Jul 09 06:43:01 PM PDT 24 |
Finished | Jul 09 06:43:28 PM PDT 24 |
Peak memory | 222076 kb |
Host | smart-aeb6bfd6-1f98-4d4c-adf6-69b3d9ccd628 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052983499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1052983499 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3812091378 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 5502640519 ps |
CPU time | 9.04 seconds |
Started | Jul 09 06:43:04 PM PDT 24 |
Finished | Jul 09 06:43:14 PM PDT 24 |
Peak memory | 213868 kb |
Host | smart-8c64378f-fb9d-4feb-b690-b670bf04a7fc |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3812091378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.3812091378 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.187590394 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 1193444087 ps |
CPU time | 0.93 seconds |
Started | Jul 09 06:43:00 PM PDT 24 |
Finished | Jul 09 06:43:04 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-b23d0eaa-4630-4f71-8b4d-310439141256 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187590394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.187590394 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.727775335 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 3268458972 ps |
CPU time | 2.94 seconds |
Started | Jul 09 06:43:00 PM PDT 24 |
Finished | Jul 09 06:43:06 PM PDT 24 |
Peak memory | 205712 kb |
Host | smart-ec9e4564-541f-408d-9cda-48ce88902ce1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=727775335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.727775335 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all.3052951041 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 5245936240 ps |
CPU time | 3.2 seconds |
Started | Jul 09 06:43:07 PM PDT 24 |
Finished | Jul 09 06:43:11 PM PDT 24 |
Peak memory | 205512 kb |
Host | smart-4af9ea8e-7836-4d31-9fa2-e7ce4dfd72fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052951041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3052951041 |
Directory | /workspace/4.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.803019891 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 63237552 ps |
CPU time | 0.7 seconds |
Started | Jul 09 06:43:46 PM PDT 24 |
Finished | Jul 09 06:43:49 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-e20fd732-e8af-4865-b288-bc58ab6b8dc6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803019891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.803019891 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.3645206057 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 7325970029 ps |
CPU time | 3.12 seconds |
Started | Jul 09 06:43:43 PM PDT 24 |
Finished | Jul 09 06:43:48 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-037ef279-0394-4890-8b4f-7e76aa43fc46 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645206057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3645206057 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/41.rv_dm_stress_all.396207968 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 6605848198 ps |
CPU time | 17.62 seconds |
Started | Jul 09 06:43:45 PM PDT 24 |
Finished | Jul 09 06:44:04 PM PDT 24 |
Peak memory | 213704 kb |
Host | smart-2b1e01fd-0351-47e5-a5b4-774c2655949f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396207968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.396207968 |
Directory | /workspace/41.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.3146531585 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 101792040 ps |
CPU time | 0.9 seconds |
Started | Jul 09 06:43:45 PM PDT 24 |
Finished | Jul 09 06:43:48 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-eb1b6c2d-0913-4144-8290-582a19310f1a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146531585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3146531585 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.601342748 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 9890132254 ps |
CPU time | 7.05 seconds |
Started | Jul 09 06:43:47 PM PDT 24 |
Finished | Jul 09 06:43:56 PM PDT 24 |
Peak memory | 213796 kb |
Host | smart-cc0de2e3-e39a-412f-b856-95103339de94 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601342748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.601342748 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.908053769 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 71129192 ps |
CPU time | 0.71 seconds |
Started | Jul 09 06:43:50 PM PDT 24 |
Finished | Jul 09 06:43:52 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-1668cd53-5424-44f7-b25e-4490258d9c1c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908053769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.908053769 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.2404087330 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 11252756835 ps |
CPU time | 25.54 seconds |
Started | Jul 09 06:43:51 PM PDT 24 |
Finished | Jul 09 06:44:18 PM PDT 24 |
Peak memory | 205604 kb |
Host | smart-23723d66-aee8-46a4-95c0-647518df5b87 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404087330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.2404087330 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.1389615221 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 38095581 ps |
CPU time | 0.72 seconds |
Started | Jul 09 06:43:52 PM PDT 24 |
Finished | Jul 09 06:43:54 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-e438d08c-8b3f-47ce-a33b-9f2a411bd36c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389615221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1389615221 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.910440933 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 3451401748 ps |
CPU time | 1.58 seconds |
Started | Jul 09 06:43:51 PM PDT 24 |
Finished | Jul 09 06:43:54 PM PDT 24 |
Peak memory | 205616 kb |
Host | smart-f338f49d-55c8-4abb-9a18-cfc46845a10b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910440933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.910440933 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.1819657238 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 123877426 ps |
CPU time | 0.72 seconds |
Started | Jul 09 06:43:50 PM PDT 24 |
Finished | Jul 09 06:43:53 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-88892615-2cb2-4a14-92b2-52f95f45d1f8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819657238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1819657238 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_stress_all.3767012762 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 6539895255 ps |
CPU time | 16.71 seconds |
Started | Jul 09 06:43:50 PM PDT 24 |
Finished | Jul 09 06:44:08 PM PDT 24 |
Peak memory | 205640 kb |
Host | smart-f6d0d454-02c3-4f29-b021-be1458743bdd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767012762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3767012762 |
Directory | /workspace/45.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.1337835539 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 81898052 ps |
CPU time | 0.78 seconds |
Started | Jul 09 06:43:49 PM PDT 24 |
Finished | Jul 09 06:43:51 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-9529015e-5e91-42aa-b266-1aae7a879314 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337835539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1337835539 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.3275978881 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 5654084138 ps |
CPU time | 14.59 seconds |
Started | Jul 09 06:43:49 PM PDT 24 |
Finished | Jul 09 06:44:05 PM PDT 24 |
Peak memory | 205576 kb |
Host | smart-4e75c672-fb29-4b78-8c25-e7fcc63ea3e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275978881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3275978881 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.1358382932 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 65276747 ps |
CPU time | 0.76 seconds |
Started | Jul 09 06:43:49 PM PDT 24 |
Finished | Jul 09 06:43:51 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-555c2a95-8d34-457d-94d9-cfdc9fe59804 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358382932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1358382932 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_stress_all.2865193317 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 4853694681 ps |
CPU time | 6.77 seconds |
Started | Jul 09 06:43:48 PM PDT 24 |
Finished | Jul 09 06:43:56 PM PDT 24 |
Peak memory | 213708 kb |
Host | smart-ff5df584-3e06-48eb-ae89-4461b2b29e10 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865193317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2865193317 |
Directory | /workspace/47.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.439904331 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 65577597 ps |
CPU time | 0.75 seconds |
Started | Jul 09 06:43:50 PM PDT 24 |
Finished | Jul 09 06:43:52 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-871f9664-fc29-4a98-8621-2ffbe455447e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439904331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.439904331 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.2414145440 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 7908260106 ps |
CPU time | 22.26 seconds |
Started | Jul 09 06:43:51 PM PDT 24 |
Finished | Jul 09 06:44:15 PM PDT 24 |
Peak memory | 205540 kb |
Host | smart-1b4a5a54-5f7e-491d-84fc-3f2a5ca5ec3e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414145440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2414145440 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.2469784014 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 149646788 ps |
CPU time | 0.76 seconds |
Started | Jul 09 06:43:56 PM PDT 24 |
Finished | Jul 09 06:43:58 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-34f4fee2-7895-4d96-b87f-f3cb4a9d0c66 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469784014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2469784014 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.1800969996 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 49258472 ps |
CPU time | 0.75 seconds |
Started | Jul 09 06:43:06 PM PDT 24 |
Finished | Jul 09 06:43:08 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-75680170-9761-4e59-8449-93410049af5e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800969996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1800969996 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3581312317 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 19636967299 ps |
CPU time | 27.68 seconds |
Started | Jul 09 06:43:08 PM PDT 24 |
Finished | Jul 09 06:43:36 PM PDT 24 |
Peak memory | 213852 kb |
Host | smart-538fce40-a211-4966-8574-a1001dd64879 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3581312317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3581312317 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1920296519 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 14593687839 ps |
CPU time | 26.98 seconds |
Started | Jul 09 06:43:11 PM PDT 24 |
Finished | Jul 09 06:43:39 PM PDT 24 |
Peak memory | 213824 kb |
Host | smart-a982c296-485e-4eaf-bd1f-c7b35954e499 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1920296519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t l_access.1920296519 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.2996679358 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 3957658777 ps |
CPU time | 5.9 seconds |
Started | Jul 09 06:43:06 PM PDT 24 |
Finished | Jul 09 06:43:13 PM PDT 24 |
Peak memory | 213924 kb |
Host | smart-12b11558-1206-4b87-9101-d3b197c4e508 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996679358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2996679358 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.962457571 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 5947511259 ps |
CPU time | 10.4 seconds |
Started | Jul 09 06:43:11 PM PDT 24 |
Finished | Jul 09 06:43:23 PM PDT 24 |
Peak memory | 213764 kb |
Host | smart-97693989-5cc3-4a0a-bbff-efbce95f4d4b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962457571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.962457571 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.1849304400 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 49360717 ps |
CPU time | 0.73 seconds |
Started | Jul 09 06:43:12 PM PDT 24 |
Finished | Jul 09 06:43:14 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-8a7e5b0e-df10-4d95-90f0-246de50aba68 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849304400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1849304400 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.4205576865 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 61499971138 ps |
CPU time | 12.09 seconds |
Started | Jul 09 06:43:12 PM PDT 24 |
Finished | Jul 09 06:43:26 PM PDT 24 |
Peak memory | 215468 kb |
Host | smart-aadc3058-71fe-466a-96db-5a372a86dbab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205576865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.4205576865 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.4270196169 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 14456948195 ps |
CPU time | 14.22 seconds |
Started | Jul 09 06:43:07 PM PDT 24 |
Finished | Jul 09 06:43:22 PM PDT 24 |
Peak memory | 213820 kb |
Host | smart-5fef7271-28fa-4c4e-b84b-7a8b762a8b00 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4270196169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t l_access.4270196169 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.2877858501 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 5807656134 ps |
CPU time | 4.17 seconds |
Started | Jul 09 06:43:08 PM PDT 24 |
Finished | Jul 09 06:43:13 PM PDT 24 |
Peak memory | 213836 kb |
Host | smart-06ebda73-96ba-4001-b2a2-5a47d6e6d9ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877858501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2877858501 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.2164194026 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 2984221686 ps |
CPU time | 1.89 seconds |
Started | Jul 09 06:43:13 PM PDT 24 |
Finished | Jul 09 06:43:17 PM PDT 24 |
Peak memory | 213808 kb |
Host | smart-f75f8d45-a527-462f-b8de-3dce96ad52f2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164194026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2164194026 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.3935976286 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 95905748 ps |
CPU time | 0.76 seconds |
Started | Jul 09 06:43:15 PM PDT 24 |
Finished | Jul 09 06:43:18 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-8f623fa3-a690-40fa-b4d4-a9be4a18693a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935976286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3935976286 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.69318093 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 3449120944 ps |
CPU time | 3.32 seconds |
Started | Jul 09 06:43:11 PM PDT 24 |
Finished | Jul 09 06:43:15 PM PDT 24 |
Peak memory | 213900 kb |
Host | smart-f67149b7-d62f-458b-8893-5aae91ecbb9d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69318093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.69318093 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.638723645 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 2678513222 ps |
CPU time | 7.9 seconds |
Started | Jul 09 06:43:12 PM PDT 24 |
Finished | Jul 09 06:43:21 PM PDT 24 |
Peak memory | 205632 kb |
Host | smart-014fb570-7205-437a-9f94-bbdf5ede53c1 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=638723645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl _access.638723645 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.1037782814 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 1356700012 ps |
CPU time | 2.84 seconds |
Started | Jul 09 06:43:13 PM PDT 24 |
Finished | Jul 09 06:43:18 PM PDT 24 |
Peak memory | 205600 kb |
Host | smart-d22be45a-505a-49b2-a2f1-e948b5125d37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1037782814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1037782814 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.3314885168 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 12306676130 ps |
CPU time | 10.61 seconds |
Started | Jul 09 06:43:15 PM PDT 24 |
Finished | Jul 09 06:43:28 PM PDT 24 |
Peak memory | 213968 kb |
Host | smart-81a66fe8-301c-40fe-b407-5981f2043184 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314885168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3314885168 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.1077593116 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 62323497 ps |
CPU time | 0.71 seconds |
Started | Jul 09 06:43:13 PM PDT 24 |
Finished | Jul 09 06:43:16 PM PDT 24 |
Peak memory | 205508 kb |
Host | smart-c5e38065-ec82-47b4-bd6c-5848c37c7a8b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077593116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1077593116 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2013257000 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 113524357931 ps |
CPU time | 52.46 seconds |
Started | Jul 09 06:43:15 PM PDT 24 |
Finished | Jul 09 06:44:11 PM PDT 24 |
Peak memory | 220224 kb |
Host | smart-d2e1ed08-bf5f-4770-b429-8a218e3a9cd8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2013257000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2013257000 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3567185917 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 7093144653 ps |
CPU time | 17.01 seconds |
Started | Jul 09 06:43:12 PM PDT 24 |
Finished | Jul 09 06:43:31 PM PDT 24 |
Peak memory | 213920 kb |
Host | smart-344061e2-4cb4-46a0-bb8d-2392b8384b0c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567185917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3567185917 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2585662330 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 1131133875 ps |
CPU time | 2.46 seconds |
Started | Jul 09 06:43:13 PM PDT 24 |
Finished | Jul 09 06:43:17 PM PDT 24 |
Peak memory | 205580 kb |
Host | smart-7fdb0e4c-b226-4ce1-9444-68d7faadfaa4 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2585662330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t l_access.2585662330 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.810890612 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 3128756722 ps |
CPU time | 1.75 seconds |
Started | Jul 09 06:43:12 PM PDT 24 |
Finished | Jul 09 06:43:16 PM PDT 24 |
Peak memory | 205732 kb |
Host | smart-4902034e-7867-40f5-bc03-6435d2682d35 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=810890612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.810890612 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.2694186132 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 114485271 ps |
CPU time | 0.73 seconds |
Started | Jul 09 06:43:16 PM PDT 24 |
Finished | Jul 09 06:43:19 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-253a4b91-3d85-470a-b049-114d367eaa9b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694186132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2694186132 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1951819529 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 4877042722 ps |
CPU time | 5.76 seconds |
Started | Jul 09 06:43:17 PM PDT 24 |
Finished | Jul 09 06:43:26 PM PDT 24 |
Peak memory | 205664 kb |
Host | smart-bfa8186b-653b-4317-a50a-12e01e61c34f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1951819529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1951819529 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1414436437 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 3801636779 ps |
CPU time | 10.9 seconds |
Started | Jul 09 06:43:18 PM PDT 24 |
Finished | Jul 09 06:43:33 PM PDT 24 |
Peak memory | 205696 kb |
Host | smart-35ddb9d8-d8f5-457a-86fe-467becbb8d60 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1414436437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1414436437 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1901566896 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 5709906321 ps |
CPU time | 3.47 seconds |
Started | Jul 09 06:43:13 PM PDT 24 |
Finished | Jul 09 06:43:19 PM PDT 24 |
Peak memory | 214708 kb |
Host | smart-70669c05-e353-472f-a8ba-db3d06000b30 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1901566896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.1901566896 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.3608700030 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 8496935643 ps |
CPU time | 6.89 seconds |
Started | Jul 09 06:43:14 PM PDT 24 |
Finished | Jul 09 06:43:23 PM PDT 24 |
Peak memory | 213808 kb |
Host | smart-1be79b13-d470-4c5e-80fb-bfafda381eba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3608700030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3608700030 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.2282460346 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 6179913053 ps |
CPU time | 3.76 seconds |
Started | Jul 09 06:43:18 PM PDT 24 |
Finished | Jul 09 06:43:25 PM PDT 24 |
Peak memory | 205616 kb |
Host | smart-999e634e-dcc2-43a3-85d0-d9501b8b5b7c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282460346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.2282460346 |
Directory | /workspace/9.rv_dm_stress_all/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |